Prosecution Insights
Last updated: July 17, 2026
Application No. 18/327,968

INTEGRATED CIRCUIT DEVICES WITH FISHBONE CAPACITOR STRUCTURES

Non-Final OA §102§103
Filed
Jun 02, 2023
Examiner
TRAPANESE, WILLIAM C
Art Unit
Tech Center
Assignee
Intel Corporation
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
493 granted / 640 resolved
+17.0% vs TC avg
Strong +21% interview lift
Without
With
+20.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
25 currently pending
Career history
667
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
78.2%
+38.2% vs TC avg
§102
15.2%
-24.8% vs TC avg
§112
0.4%
-39.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 640 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-6, 14-17, 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yen et al. (hereinafter Yen, US 2013/0228894). In regards to independent claim 1, Yen teaches an integrated circuit (IC) device, comprising: a die, comprising an IC (32); a metallization stack over the IC (36); and a capacitor structure in a layer of the metallization stack (40), the capacitor structure comprising a first capacitor electrode, a second capacitor electrode, and a third capacitor electrode (44,46,48), wherein the first capacitor electrode is a first line with protrusions on a side of the first line, the second capacitor electrode is a second line with protrusions on a first side of the second line and protrusions on a second side of the second line, the third capacitor electrode is a third line with protrusions on a side of the third line, the protrusions on the side of the first line and the protrusions on the first side of the second line form a first interdigitated capacitor structure, and the protrusions on the side of the third line and the protrusions on the second side of the second line form a second interdigitated capacitor structure (44, 72, 74, 76, 46, 78, 80, 48, 82, 84, [0045-0048], Fig. 6-9). In regards to dependent claim 2, Yen teaches the IC device according to claim 1, wherein the second capacitor electrode is between the first capacitor electrode and the third capacitor electrode (44, 46, 48, Fig. 6). In regards to dependent claim 3, Yen teaches the IC device according to claim 1, wherein the protrusions on the side of the first line and the protrusions on the side of the third line are symmetric with respect to the second line (46, 48, 44, [0041]). In regards to dependent claim 4, Yen teaches the IC device according to claim 1, wherein the protrusions on the first side of the second line and the protrusions on the second side of the second line are symmetric with respect to the second line ([0041], Fig. 4-6). In regards to dependent claim 5, Yen teaches the IC device according to claim 1, further comprising a first insulator material between the first capacitor electrode and the second capacitor electrode, and a second insulator material between the third capacitor electrode and the second capacitor electrode (44, 46, 48, [0040]). In regards to dependent claim 6, Yen teaches the IC device according to claim 5, wherein at least one of the first insulator material and the second insulator material includes a high-k dielectric ([0040]). In regards to independent claim 14, Yen teaches an integrated circuit (IC) device, comprising: a support structure (32); a plurality of layers of an insulator material above the support structure (36); and a capacitor structure in one of the plurality of layers, the capacitor structure comprising a first capacitor electrode, a second capacitor electrode, and a third capacitor electrode (40, 44, 46, 48), wherein the second capacitor electrode is between the first capacitor electrode and the third capacitor electrode and has a fishbone structure, the first capacitor electrode includes stubs interlacing with stubs of a first side of the fishbone structure, and the third capacitor electrode includes stubs interlacing with stubs of a second side of the fishbone structure, [0048], Fig. 6-9, 44, 46, 48, 80, 84, 74, 76). In regards to dependent claim 15, Yen teaches the IC device according to claim 14, wherein at least a portion of the third capacitor electrode is symmetric with the first capacitor electrode ([0041], Fig. 4-6). In regards to dependent claim 16, Yen teaches the IC device according to claim 14, wherein the stubs of the first side of the fishbone structure are symmetric with the stubs of the second side of the fishbone structure ([0041], Fig. 4-6). In regards to dependent claim 17, Yen teaches the IC device according to claim 14, further comprising a conductive line in the one of the plurality of layers, wherein a thickness of the capacitor structure is substantially same as a thickness of the conductive line ([0034], Fig. 4-6). In regards to independent claim 19, Yen teaches An integrated circuit (IC) package, comprising: an IC die, comprising an IC device; and a further component, coupled to the IC die ([0028]), wherein the IC device includes a substrate (32) and a capacitor structure (40) over the substrate, the capacitor structure comprising a first capacitor electrode, a second capacitor electrode, and a third capacitor electrode (44, 46, 48), wherein the first capacitor electrode is a first line with stubs on a side of the first line, the second capacitor electrode is a second line with stubs on a first side of the second line and stubs on a second side of the second line, the third capacitor electrode is a third line with stubs on a side of the third line, the stubs on the side of the first line and the stubs on the first side of the second line form a first interdigitated capacitor structure, and the stubs on the side of the third line and the stubs on the second side of the second line form a second interdigitated capacitor structure (44, 46, 48, 72, 74, 76, 78, 82, 84). In regards to dependent claim 20, Yen teaches the IC package according to claim 19, wherein the further component is one of a package substrate, an interposer, or a further IC die ([0028]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 7-13, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yen in view of Yen et al (hereinafter Realtek, US2021/0091173). In regards to dependent claim 7, Yen fails to explicitly teach wherein the capacitor structure further includes a fourth capacitor electrode, the fourth capacitor electrode is a fourth line with protrusions on a side of the fourth line, the third line is between the second line and the fourth line, and the protrusions on the side of the fourth line extend towards the third line. Realtek teaches wherein the capacitor structure further includes a fourth capacitor electrode, the fourth capacitor electrode is a fourth line with protrusions on a side of the fourth line, the third line is between the second line and the fourth line, and the protrusions on the side of the fourth line extend towards the third line (CC1, CC2, CC3, M1, M2, M3, S1, S2, S3, [0026], [0029, [0035], Fig. 2). It would have been obvious to one of ordinary skill in the art, having the teachings of Yen and Realtek before him before the effective filing date of the claimed invention, to modify the fishbone capacitor taught by Yen to include the large scale capacitor of Realtek in order to obtain a fishbone capacitor of a large number of iterations. One would have been motivated to make such a combination because it allows the designer to adjust capacitance while also using a smaller footprint. In regards to dependent claim 8, Yen fails to explicitly teach wherein the side of the third line is a first side of the third line, the third capacitor electrode further includes protrusions on a second side of the third line, and the protrusions on the side of the fourth line and the protrusions on the second side of the third line form a third interdigitated capacitor structure. Realtek teaches wherein the side of the third line is a first side of the third line, the third capacitor electrode further includes protrusions on a second side of the third line, and the protrusions on the side of the fourth line and the protrusions on the second side of the third line form a third interdigitated capacitor structure (CC1, CC2, CC3, M1, M2, M3, S1, S2, S3, [0026], [0029, [0035], Fig. 2). It would have been obvious to one of ordinary skill in the art, having the teachings of Yen and Realtek before him before the effective filing date of the claimed invention, to modify the fishbone capacitor taught by Yen to include the large scale capacitor of Realtek in order to obtain a fishbone capacitor of a large number of iterations. One would have been motivated to make such a combination because it allows the designer to adjust capacitance while also using a smaller footprint. In regards to dependent claim 9, Yen fails to explicitly teach wherein the protrusions on the second side of the second line and the protrusions on the side of the fourth line are symmetric with respect to the third line. Realtek teaches the IC device according to claim 7, wherein the protrusions on the second side of the second line and the protrusions on the side of the fourth line are symmetric with respect to the third line (CC1, CC2, CC3, M1, M2, M3, S1, S2, S3, [0026], [0029, [0035], Fig. 2). In regards to dependent claim 10, Yen fails to explicitly teach the IC device according to claim 7, wherein the protrusions on the first side of the third line and the protrusions on the second side of the third line are symmetric with respect to the third line. Realtek teaches wherein the protrusions on the first side of the third line and the protrusions on the second side of the third line are symmetric with respect to the third line (CC1, CC2, CC3, M1, M2, M3, S1, S2, S3, [0026], [0029, [0035], Fig. 2). It would have been obvious to one of ordinary skill in the art, having the teachings of Yen and Realtek before him before the effective filing date of the claimed invention, to modify the fishbone capacitor taught by Yen to include the large scale capacitor of Realtek in order to obtain a fishbone capacitor of a large number of iterations. One would have been motivated to make such a combination because it allows the designer to adjust capacitance while also using a smaller footprint. In regards to dependent claim 11, Yen fails to explicitly teach the IC device according to claim 7, wherein a shape of the second capacitor electrode is substantially same as a shape of the third capacitor electrode. Realtek teaches the IC device according to claim 7, wherein a shape of the second capacitor electrode is substantially same as a shape of the third capacitor electrode. (CC1, CC2, CC3, M1, M2, M3, S1, S2, S3, [0026], [0029, [0035], Fig. 2). It would have been obvious to one of ordinary skill in the art, having the teachings of Yen and Realtek before him before the effective filing date of the claimed invention, to modify the fishbone capacitor taught by Yen to include the large scale capacitor of Realtek in order to obtain a fishbone capacitor of a large number of iterations. One would have been motivated to make such a combination because it allows the designer to adjust capacitance while also using a smaller footprint. In regards to dependent claim 12, Yen fails to explicitly teach the IC device according to claim 7, further comprising a further insulator material between the third capacitor electrode and the fourth capacitor electrode. Realtek teaches a further insulator material between the third capacitor electrode and the fourth capacitor electrode. (CC1, CC2, CC3, M1, M2, M3, S1, S2, S3, [0026], [0029, [0035], Fig. 2). It would have been obvious to one of ordinary skill in the art, having the teachings of Yen and Realtek before him before the effective filing date of the claimed invention, to modify the fishbone capacitor taught by Yen to include the large scale capacitor of Realtek in order to obtain a fishbone capacitor of a large number of iterations. One would have been motivated to make such a combination because it allows the designer to adjust capacitance while also using a smaller footprint. In regards to dependent claim 13, Yen fails to explicitly teach the IC device according to claim 12, wherein the further insulator material includes a high-k dielectric. Realtek teaches wherein the further insulator material includes a high-k dielectric. (CC1, CC2, CC3, M1, M2, M3, S1, S2, S3, [0026], [0029, [0035], Fig. 2). It would have been obvious to one of ordinary skill in the art, having the teachings of Yen and Realtek before him before the effective filing date of the claimed invention, to modify the fishbone capacitor taught by Yen to include the large scale capacitor of Realtek in order to obtain a fishbone capacitor of a large number of iterations. One would have been motivated to make such a combination because it allows the designer to adjust capacitance while also using a smaller footprint. In regards to dependent claim 18, Yen fails to explicitly teach the IC device according to claim 14, further comprising a fourth capacitor electrode, wherein the third capacitor electrode is between the second capacitor electrode and the fourth capacitor electrode and further includes stubs interlacing with stubs of the fourth capacitor electrode. Realtek teaches a fourth capacitor electrode, wherein the third capacitor electrode is between the second capacitor electrode and the fourth capacitor electrode and further includes stubs interlacing with stubs of the fourth capacitor electrode. (CC1, CC2, CC3, M1, M2, M3, S1, S2, S3, [0026], [0029, [0035], Fig. 2). It would have been obvious to one of ordinary skill in the art, having the teachings of Yen and Realtek before him before the effective filing date of the claimed invention, to modify the fishbone capacitor taught by Yen to include the large scale capacitor of Realtek in order to obtain a fishbone capacitor of a large number of iterations. One would have been motivated to make such a combination because it allows the designer to adjust capacitance while also using a smaller footprint. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM C TRAPANESE whose telephone number is (571)270-3304. The examiner can normally be reached Monday - Friday 7am-12pm & 8pm-10pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WILLIAM C TRAPANESE/Primary Examiner, Art Unit 2812
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Prosecution Timeline

Jun 02, 2023
Application Filed
Oct 11, 2023
Response after Non-Final Action
Jul 01, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
98%
With Interview (+20.9%)
3y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 640 resolved cases by this examiner. Grant probability derived from career allowance rate.

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