DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/12/2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Status
Previous action: claims 1, 2, and 10 through 13 rejected, claims 3 through 9 objected
Present action: claim 1 through 3 and 10 through 13 are rejected, claims 5 through 9 are objected
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 1, 2, 3, 4, 11, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saito (US 2016/0148973)
Regarding claim 1.
Saito teaches:
A micro light-emitting chip structure (fig 3:1; [para 0090]), comprising:
a first-type semiconductor layer (fig 3:221; [para 0105]);
a light-emitting layer (fig 3:23; [para 0105]) disposed on the first-type semiconductor layer (fig 3:221; [para 0105]);
a second-type semiconductor layer (fig 3:212; [para 0103]) disposed on the light-emitting layer (fig 3:23; [para 0105]) and having a peripheral surface and an end surface that is connected to the peripheral surface;
a first insulating layer (fig 3:51; [para 0116]) disposed on the second-type semiconductor layer (fig 3:212; [para 0103]);
a reflective layer (fig 3:53; [para 0116]) disposed on the first insulating layer (fig 3:51; [para 0116]) and covering the end surface;
an electrode (fig 3:730; [para 0126]) disposed on the end surface and connected to the second-type semiconductor layer (fig 3:212; [para 0103]),
wherein the electrode penetrates
the reflective layer (fig 3:53; [para 0116]), and the first insulating layer (fig 3:51; [para 0116]);
and a dielectric structure (fig 3:52; [para 0116]) laterally disposed between the electrode (fig 3:730; [para 0126]) and the reflective layer (fig 3:53; [para 0116]) and surrounding the electrode (fig 3:730; [para 0126]),
wherein the dielectric structure (fig 3:52; [para 0116]) has a first annular sidewall facing the electrode (fig 3:730; [para 0126]),
wherein the first annular sidewall has a first end away from the second-type semiconductor layer (fig 3:212; [para 0103]) and a second end close to the second-type semiconductor layer (fig 3:212; [para 0103]),
and an inner diameter of the first end is greater than or equal to an inner diameter of the second end,
and the dielectric structure (fig 3:52; [para 0116]) is disposed in direct contact with the first insulating layer (fig 3:51; [para 0116]) on the end surface in a longitudinal direction that is parallel to a stacking direction from the light-emitting layer (fig 3:23; [para 0105]) towards the electrode (fig 3:730; [para 0126]).
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Saito does not teach a second insulating layer in the embodiment.
Saito teaches a second embodiment comprising:
A micro light-emitting chip structure, comprising:
a reflective layer (fig 36:53D; [para 0303]) disposed on the first insulating layer (fig 36:512D; [para 0303]),
a second insulating layer (fig 36:522D; [para 0303]) disposed on the reflective layer (fig 36:53D; [para 0303]),
wherein the electrode (fig 36:730D) penetrates the second insulating layer (fig 36:522D; [para 0303]),
the reflective layer (fig 36:53D; [para 0303]),
and the first insulating layer (fig 36:512d; [para 0301]);
and wherein the second insulating layer (fig 36:522D; [para 0303]) is laterally in direct contact with the electrode (fig 36:730D),
and the dielectric structure (fig 36:521D; [para 0303]) is disposed between and in direct contact with the first insulating layer (fig 36:512D; [para 0301]) and the second insulating layer (fig 36:522D; [para 0303]) on the end surface in a longitudinal direction (fig 36:Z) that is parallel to a stacking direction (fig 36:Z) from the light-emitting layer (fig 36:20D) towards the electrode (fig 36:730d).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a second insulating layer in order to provide addition protection and support for the structure (paragraph 0306).
Regarding claim 2.
Saito teaches the micro light-emitting chip structure as claimed in claim 1, further
Saito teaches:
the first annular sidewall (annotated fig 3 above) is in direct contact with the electrode (fig 3:730; [para 0126]).
Regarding claim 3.
Saito teaches the micro light-emitting chip structure as claimed in claim 1, further
Saito teaches:
wherein the second insulating layer (fig 36:522D; [para 0303]) has a second annular sidewall facing the electrode (fig 36:730D; [para 0303]),
and the second annular sidewall has a third end away from the dielectric structure (fig 36:521D; [para 0303]) and a fourth end close to the dielectric structure (fig 36:521D; [para 0303]).
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Regarding claim 4.
Saito teaches the micro light-emitting chip structure as claimed in claim 3, further
Saito teaches:
wherein the inner diameter of the first end is less than an inner diameter of the fourth end (annotated figure 36).
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Regarding claim 11.
Saito teaches the micro light-emitting chip structure as claimed in claim 1, further
Saito teaches:
wherein the first-type semiconductor layer (fig 3:221; [para 0105]),
the light-emitting layer (fig 3:23; [para 0105]),
and the second-type semiconductor layer (fig 3:212; [para 0105]) form an epitaxial light-emitting unit (fig 3:1; [para 0089]),
the micro light-emitting chip structure (fig 21:810; [para 0209]) comprises a plurality of epitaxial light-emitting units (fig 21:1; [para 0209]),
and two adjacent epitaxial light-emitting units (fig 21:1; [para 0209]).
Saito teaches:
the second insulating layer (fig 36:522d; [para 0303]) covers light-emitting unit (fig 36:1; [para 0305]).
Regarding claim 12.
Saito teaches the micro light-emitting chip structure as claimed in claim 1, further
Saito teaches:
a thickness of the dielectric structure (fig 3:52; [para 0116]) is equal to a thickness of the reflective layer (fig 3:53; [para 0116]).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saito (US 2016/0148973) as applied to claim 1 and further in view of Ko (US 2018/0130924)
Regarding claim 10.
Saito teaches the structure of claim 1 above.
Saito not teach the second insulating layer is a reflective material.
Ko further teaches:
forming an insulating layer (fig 8a:70; [para 0032]) is a multi-layer dielectric reflective (Bragg) coating ([para 0032]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the second insulating layer a reflective multilayer dielectric coating in order to further improve the reflectance of the device mirror structure.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saito (US 2016/0148973) in view of Wu (US 2019/0115333)
Regarding claim 13.
Saito teaches:
A micro display structure, comprising:
a display substrate (fig 19:810; [para 0207]);
micro light-emitting chip structures (fig 3,19:1; [para 0207]) arranged on the display substrate (fig 19:810; [para 0207]),
wherein each of the micro light-emitting chip structures (fig 3,19:1; [para 0207]) comprises:
a first-type semiconductor layer (fig 3:221; [para 0105]);
a light-emitting layer (fig 3:23; [para 0105]) disposed on the first-type semiconductor layer (fig 3:221; [para 0105]);
a second-type semiconductor layer (fig 3:212; [para 0103]) disposed on the light-emitting layer (fig 3:23; [para 0105]) and having a peripheral surface and an end surface that is connected to the peripheral surface (fig 3);
a first insulating layer (fig 3:51; [para 0116]) disposed on the second-type semiconductor layer (fig 3:212; [para 0103]);
a reflective layer (fig 3:53; [para 0116]) disposed on the first insulating layer (fig 3:51; [para 0116]) and covering the end surface;
;
an electrode (fig 3:730; [para 0126]) disposed on the end surface and connected to the second-type semiconductor layer (fig 3:212; [para 0103]),
wherein the electrode penetrates (fig 3:730; [para 0126]) , the reflective layer (fig 3:53; [para 0116]), and the first insulating layer (fig 3:51; [para 0116]);
and a dielectric structure (fig 3:52; [para 0017]) laterally disposed between the electrode (fig 3:730; [para 0126]) and the reflective layer (fig 3:53; [para 0116]) and surrounding the electrode (fig 3:730; [para 0126]),
wherein the dielectric structure (fig 3:52; [para 0017]) has a first annular sidewall facing the electrode (fig 3:730; [para 0126]),
wherein the first annular sidewall has a first end away from the second-type semiconductor layer (fig 3:212; [para 0103]) and a second end close to the second-type semiconductor layer (fig 3:212; [para 0103]),
and an inner diameter of the first end is greater than or equal to an inner diameter of the second end;
,
and the dielectric structure (fig 3:52; [para 0017]) is disposed in direct contact with the first insulating layer (fig 3:51; [para 0116]) on the end surface in a longitudinal direction that is parallel to a stacking direction from the light-emitting layer (fig 3:23; [para 0105]) towards the electrode (fig 3:730; [para 0126]);
and an ohmic contact layer (fig 3:222,710; [para 0105]) patterned [on] the micro light-emitting chip structures (fig 3,19:1; [para 0207]) and electrically connected to the first-type semiconductor layer (fig 3:221; [para 0105]) of the micro-light-emitting chip structures (fig 3,19:1; [para 0207]).
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Saito does not teach a second insulating layer in this embodiment.
Saito teaches in a second embodiment:
A micro display structure, comprising:
wherein each of the micro light-emitting chip structures comprises:
a first insulating layer (fig 36:512D; [para 0303])
a reflective layer (fig 36:53D; [para 0303]) disposed on the first insulating layer (fig 36:512D; [para 0303]) and covering the end surface;
a second insulating layer (fig 36:522D; [para 0303]) disposed on the reflective layer (fig 36:53D; [para 0303]);
wherein the electrode (fig 36:730D; [para 0303]) penetrates the second insulating layer (fig 36:522D; [para 0303]), the reflective layer (fig 36:53D; [para 0303]), and the first insulating layer (fig 36:512D; [para 0303]);
and a dielectric structure (fig 36:521d; [para 0303]) laterally disposed between the electrode and the reflective layer (fig 36:53D; [para 0303]) and surrounding the electrode (fig 36:730D; [para 0303]),
and wherein the second insulating layer (fig 36:522D; [para 0303]) is laterally in direct contact with the electrode (fig 36:730D; [para 0303]),
and the dielectric structure (fig 36:521D; [para 0303]) is disposed between and in direct contact with the first insulating layer (fig 36:512D; [para 0303]) and the second insulating layer (fig 36:522D; [para 0303]) on the end surface in a longitudinal direction that is parallel to a stacking direction from the light-emitting layer towards the electrode (fig 36:730D; [para 0303]);
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a second insulating layer in order to provide addition protection and support for the structure (paragraph 0306).
Saito does not teach the ohmic contact layer is patterned between structures.
Wu teaches:
forming an ohmic contact layer (fig 1a,1b:130a; [para 0035]) between the micro light-emitting chip structures (fig 1b:120; [para 0031]) and electrically connected to the first-type semiconductor layer (fig 1b:122c; [para 0034]) of the micro-light-emitting chip structures (fig 1b:120; [para 0031]).
It would have been obvious to one of ordinary skill in the art to provide an ohmic contact layer between structures in order to energize multiple structures.
Allowable Subject Matter
Claims 5 through 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, the prior art does not teach in combination with the other elements of the claim a micro light-emitting chip structure, comprising: a dielectric structure laterally disposed between the electrode and the reflective layer and surrounding the electrode, wherein the dielectric structure has a first annular sidewall facing the electrode, wherein the first annular sidewall has a first end away from the second-type semiconductor layer and a second end close to the second-type semiconductor layer, and an inner diameter of the first end is greater than or equal to an inner diameter of the second end, and wherein the second insulating layer is laterally in direct contact with the electrode, and the dielectric structure is disposed between and in direct contact with the first insulating layer and the second insulating layer on the end surface in a longitudinal direction that is parallel to a stacking direction from the light-emitting layer towards the electrode, an orthogonal projection of the first end on the second-type semiconductor layer fully overlaps an orthogonal projection of the fourth end on the second-type semiconductor layer.
Regarding claim 6, the prior art does not teach in combination with the other elements of the claima micro light-emitting chip structure, comprising: a dielectric structure laterally disposed between the electrode and the reflective layer and surrounding the electrode, wherein the dielectric structure has a first annular sidewall facing the electrode, wherein the first annular sidewall has a first end away from the second-type semiconductor layer and a second end close to the second-type semiconductor layer, and an inner diameter of the first end is greater than or equal to an inner diameter of the second end, and wherein the second insulating layer is laterally in direct contact with the electrode, and the dielectric structure is disposed between and in direct contact with the first insulating layer and the second insulating layer on the end surface in a longitudinal direction that is parallel to a stacking direction from the light-emitting layer towards the electrode, the inner diameter of the first end is greater than an inner diameter of the fourth end, and the difference between the inner diameter of the first end and the inner diameter of the fourth end is less than 50% of a thickness of the dielectric structure.
Regarding claim 7, the prior art does not teach in combination with the other elements of the claim a micro light-emitting chip structure, comprising: a dielectric structure laterally disposed between the electrode and the reflective layer and surrounding the electrode, wherein the dielectric structure has a first annular sidewall facing the electrode, wherein the first annular sidewall has a first end away from the second-type semiconductor layer and a second end close to the second-type semiconductor layer, and an inner diameter of the first end is greater than or equal to an inner diameter of the second end, and wherein the second insulating layer is laterally in direct contact with the electrode, and the dielectric structure is disposed between and in direct contact with the first insulating layer and the second insulating layer on the end surface in a longitudinal direction that is parallel to a stacking direction from the light-emitting layer towards the electrode, the first insulating layer has a third annular sidewall facing the electrode, and the difference between a maximum inner diameter and a minimum inner diameter of the first annular sidewall, the second annular sidewall, and the third annular sidewall is less than 50% of a total thickness of the first insulating layer, the dielectric structure, and the second insulating layer.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 through 13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The applicant argues that the amended claims overcome the previous applied rejection. However, newly applied obviousness rejection over Saito (US 2016/0148973) anticipates the claims (see above).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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