Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s remarks/amendments of claims 1-13 in the reply filed on March 23th, 2026, are acknowledged. Claims 1, 9 and 12 have been amended. Claims 14-28 have been cancelled. Claims 29-31 have been added. Claims 1-13 and 29-31 are pending.
Action on merits of Group I, claims 1-13 and 29-31 as follows.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-4, 8-13, 29-30 and 31 are rejected under 35 U.S.C. 103 (as being unpatentable over Choi (US 2020/0258901, hereinafter Choi ‘901) in view of Lee (US 2019/0027492, hereinafter as Lee ‘492).
Regarding Claim 1, Choi ‘901 teaches a semiconductor device comprising:
a first gate structure (Fig. 5, (G1_Annotated) including first interlayer dielectric layers (Fig. 6, (101); [0094]) and first gate lines (Fig. 6, (103); [0094]) that are alternately stacked;
a plurality of first supports (131A; [0087]) passing through the first gate structure (see Fig. 6);
a second gate structure (Fig. 5, (G2_Annotated) including second interlayer dielectric layers (Fig. 6, (101); [0094]) and second gate lines that are alternately stacked (Fig. 6, (103); [0094]);
a plurality of second supports (131A; [0087]) passing through the second gate structure (see Fig. 6) (see Fig. 6); and
an isolation structure (131E; [0087]) disposed between the first gate structure (G1_Annotated) and the second gate structure (G2_Annotated); the isolation structure including first protrusions (P1_Annotated) and second protrusion (P2_Annotated).
Thus, Choi ‘901 is shown to teach all the features of the claim with the exception of explicitly the features: “the isolation structure to separate the first gate structure and the second gate structure”.
Lee ‘492 teaches the isolation structure (Fig. 2, (SI); [0036]) to separate the first gate structure (GST1; [0045]) and the second gate structure (GST2; [0045]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Choi ‘901 and Lee ‘492 by having the isolation structure to separate the first gate structure and the second gate structure in order to isolate gate stack structures adjacent to a boundary between memory blocks (see para. [0036]) as suggested by Lee ‘492.
Thus, Choi ‘901 and Lee ‘492 are shown to teach all the features of the claim with the exception of explicitly the features: “the first protrusion protruding between the first supports and the second protrusion protruding between the second supports”.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first/second protrusions that can be arranged in any order, thus the first protrusion protruding between the first supports and the second protrusion protruding between the second supports involves only routine skill in the art. In re Einstein, 8 USPQ 167. A person of ordinary skills in the art is motivated to perform the arrangement of the first protrusion protruding between the first supports and the second protrusion protruding between the second supports when this improves the performance of the semiconductor device.
Regarding Claim 9, Choi ‘901 teaches a semiconductor device comprising:
a first gate structure (G1_Annotated) including a first cell region (Fig. 5, (AR1_1); [0085]) and a first contact region (AR2_1; [0085]);
a second gate structure (G2_Annotated) including a second cell region (Fig. 5, (AR1_2); [0085]) and a second contact region (AR2_2; [0085]);
an isolation structure (131E; [0087]) disposed between the first gate structure (G1_Annotated) and the second gate structure (G2_Annotated);
the isolation structure including first protrusions (P1_Annotated) protruding toward the first gate structure (G1_Annotated) and a second protrusion (P2_Annotated) protruding toward the second gate structure (G2_Annotated);
a first support (131A_left; [0087]) passing through the first contact region (AR2_1) (see Figs. 5 and 6); and
a second support (131A_right; [0087]) passing through the second contact region (AR2_2) (see Figs. 5 and 6), the second support arranged asymmetrically with the first support with the isolation structure (131E) interposed between the second support (131A_right) and the first support (131A_left) (see Fig. 5_Annotated).
Thus, Choi ‘901 is shown to teach all the features of the claim with the exception of explicitly the features: “the isolation structure to separate the first gate structure and the second gate structure”.
Lee ‘492 teaches the isolation structure (Fig. 2, (SI); [0036]) to separate the first gate structure (GST1; [0045]) and the second gate structure (GST2; [0045]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Choi ‘901 and Lee ‘492 by having the isolation structure to separate the first gate structure and the second gate structure in order to isolate gate stack structures adjacent to a boundary between memory blocks (see para. [0036]) as suggested by Lee ‘492.
Regarding Claim 31, Choi ‘901 teaches a semiconductor device comprising:
a first gate structure (Fig. 5, (G1_Annotated) including first gate lines (Fig. 6, (103); [0094]) which are stacked;
a plurality of first supports (131A; [0087]) extending through the first gate structure (see Fig. 6);
a second gate structure (Fig. 5, (G2_Annotated) including second gate lines which are stacked (Fig. 6, (103); [0094]);
a plurality of second supports (131A; [0087]) extending through the second gate structure (see Fig. 6) (see Fig. 6); and
an isolation structure (131E; [0087]) disposed between the first gate structure (G1_Annotated) and the second gate structure (G2_Annotated).
Thus, Choi ‘901 is shown to teach all the features of the claim with the exception of explicitly the features: “the isolation structure to separate the first gate structure and the second gate structure”.
Lee ‘492 teaches the isolation structure (Fig. 2, (SI); [0036]) to separate the first gate structure (GST1; [0045]) and the second gate structure (GST2; [0045]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Choi ‘901 and Lee ‘492 by having the isolation structure to separate the first gate structure and the second gate structure in order to isolate gate stack structures adjacent to a boundary between memory blocks (see para. [0036]) as suggested by Lee ‘492.
Thus, Choi ‘901 and Lee ‘492 are shown to teach all the features of the claim with the exception of explicitly the features: “the isolation structure including first protrusions each extending between adjacent first supports and second protrusions each extending between adjacent second supports”.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first/second protrusions that can be arranged in any order, thus first protrusions each extending between adjacent first supports and second protrusions each extending between adjacent second supports involves only routine skill in the art. In re Einstein, 8 USPQ 167. A person of ordinary skills in the art is motivated to perform the arrangement of the first/second protrusions when this improves the performance of the semiconductor device.
Regarding Claim 2, Choi ‘901 teaches each of the plurality of first supports (131A; [0087]) includes a first protruding pattern (see Fig. 5).
Thus, Choi ‘901 is shown to teach all the features of the claim with the exception of explicitly the features: “the first protruding pattern protruding between the first protrusions”.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first protruding pattern that can be arranged in any order, thus the first protruding pattern protruding between the first protrusions involves only routine skill in the art. In re Einstein, 8 USPQ 167. A person of ordinary skills in the art is motivated to perform the arrangement of the first protruding pattern protruding between the first protrusions when this improves the performance of the semiconductor device.
[AltContent: arrow][AltContent: textbox (G2)][AltContent: arrow][AltContent: textbox (G1)][AltContent: arrow][AltContent: textbox (AR1_2)][AltContent: arrow][AltContent: textbox (AR2_2)][AltContent: arrow][AltContent: textbox (AR2_1)][AltContent: arrow][AltContent: textbox (AR1_1)][AltContent: arrow][AltContent: arrow][AltContent: textbox (P2)][AltContent: textbox (P1)][AltContent: connector]
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Fig. 5 (Choi ‘901_Annotated)
Regarding Claim 3, Choi ‘901 teaches each of the plurality of second supports (131A; [0087]) includes a second protruding pattern (see Fig. 5).
Thus, Choi ‘901 and Lee ‘492 are shown to teach all the features of the claim with the exception of explicitly the features: “the second protruding pattern protruding between the second protrusions”.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the second protruding pattern that can be arranged in any order, thus the second protruding pattern protruding between the second protrusions involves only routine skill in the art. In re Einstein, 8 USPQ 167. A person of ordinary skills in the art is motivated to perform the arrangement of the second protruding pattern protruding between the second protrusions when this improves the performance of the semiconductor device
Regarding Claim 4, Choi ‘901 teaches the first gate structure (G1_Annotated) includes a first cell region (AR1; [0085]) where a first channel structure (115; [0085]) is disposed and a first contact region (AR2; [0085]) where the first supports (131A) are disposed; and the second gate structure (G2_Annotated) includes a second cell region (AR1) where a second channel structure (115; [0085]) is disposed and a second contact region (AR2) where the second supports (131A) are disposed (see Fig. 5).
Regarding Claim 8, Choi ‘901 teaches a lower part of the first support (131A) has a narrower width than an upper part of the first support (131A) (see Fig. 6).
Regarding Claim 10, Choi ‘901 teaches a first channel structure (115; [0085]) passing through the first cell region (AR1_1); and a second channel structure (115; [0085]) passing through the second cell region (AR1_2), the second channel structure arranged symmetrically with the first channel structure with the isolation structure interposed between the second channel structure and the first channel structure (see Fig. 5).
Regarding Claim 11, Choi ‘901 teaches a first channel structure (115; [0085]) passing through the first cell region (AR1_1); and a second channel structure (115; [0085]) passing through the second cell region (AR1_2), the second channel structure arranged symmetrically with the first channel structure with the isolation structure interposed between the second channel structure and the first channel structure (see Fig. 5).
Thus, Choi ‘901 and Lee ‘492 are shown to teach all the features of the claim with the exception of explicitly the features: “the second channel structure arranged asymmetrically with the first channel structure”.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the second channel structure that can be arranged in any order, thus the second channel structure arranged asymmetrically with the first channel structure involves only routine skill in the art. In re Einstein, 8 USPQ 167. A person of ordinary skills in the art is motivated to perform the arrangement of the second channel structure when this improves the performance of the semiconductor device.
Regarding Claim 12, Choi ‘901 teaches a lower part of each of the first support (131A) has a narrower width than an upper part of each of the first support (131A) (see Fig. 6).
Regarding Claim 13, Choi ‘901 teaches the first gate structure (Fig. 5, (G1_Annotated)) includes first interlayer dielectric layers (Fig. 6, (101); [0094]) and first gate lines (Fig. 6, (103); [0094]) that are alternately stacked; and the second gate structure (Fig. 5, (G2_Annotated) includes second interlayer dielectric layers (Fig. 6, (101); [0094]) and second gate lines (Fig. 6, (103); [0094]) that are alternately stacked.
Regarding Claim 29, Choi ‘901 teaches the first protrusion (P1) and two adjacent first supports (131A).
Thus, Choi ‘901 and Lee ‘492 are shown to teach all the features of the claim with the exception of explicitly the features: “the first protrusion extends between two adjacent first supports”.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first protrusion that can be arranged in any order, thus the first protrusion extends between two adjacent first supports involves only routine skill in the art. In re Einstein, 8 USPQ 167. A person of ordinary skills in the art is motivated to perform the arrangement of the first protrusion when this improves the performance of the semiconductor device.
Regarding Claim 30, Choi ‘901 teaches the second protrusion (P2) and two adjacent second supports (131A).
Thus, Choi ‘901 and Lee ‘492 are shown to teach all the features of the claim with the exception of explicitly the features: “the first protrusion extends between two adjacent second supports”.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the second protrusion that can be arranged in any order, thus the second protrusion extends between two adjacent second supports involves only routine skill in the art. In re Einstein, 8 USPQ 167. A person of ordinary skills in the art is motivated to perform the arrangement of the second protrusion when this improves the performance of the semiconductor device.
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Choi ‘901 and Lee ‘492 as applied to claim 4 above, and further in view of Lee (US 2019/0252406, hereinafter Lee ‘406).
Regarding Claim 5, Choi ‘901 teaches the isolation structure (131E).
Thus, Choi ‘901 and Lee ‘492 are shown to teach all the features of the claim with the exception of explicitly the features: “the isolation structure is interposed between the first channel structure and the second channel structure; and the first channel structure and the second channel structure are symmetrically arranged with the isolation structure interposed therebetween”.
Lee ‘406 teaches the isolation structure (Fig. 2, (SI); [0037]) is interposed between the first channel structure (GR1; [0038]) and the second channel structure (GR2; [0038]); and the first channel structure and the second channel structure are symmetrically arranged with the isolation structure interposed therebetween (see Fig. 2).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Choi ‘901 and Lee ‘492 by having the isolation structure is interposed between the first channel structure and the second channel structure; and the first channel structure and the second channel structure are symmetrically arranged with the isolation structure interposed therebetween for the purpose of isolating gate stack structures adjacent to a boundary between memory blocks (see para. [0036]) as suggested by Lee ‘406.
Regarding Claim 6, Choi ‘901 teaches the isolation structure (131E; [0087]) is interposed between the first channel structure and the second channel structure (115; [0085]);
Lee ‘406 teaches the first channel structure and the second channel structure are asymmetrically arranged with the isolation structure (SI) interposed therebetween (see Fig. 2 and para. [0039]).
Regarding Claim 7, Choi ‘901 teaches the isolation structure (131E) is interposed between the first supports and the second supports (131A); and the first supports and the second supports (131A) are asymmetrically arranged with the isolation structure interposed therebetween (see Fig. 5).
Response to Arguments
Applicant’s arguments with respect to claims 1-13 and 29-31, filed on March 23th, 2026, have been considered but are moot in view of the new ground of rejection.
Interviews After Final
Applicants note that an interview after a final rejection is permitted in order to place the application in condition for allowance or to resolve issues prior to appeal. However, prior to the interview, the intended purpose and content of the interview should be presented briefly, preferably in writing. Upon review of the agenda, the Examiner may grant the interview if the examiner is convinced that disposal or clarification for appeal may be accomplished with only nominal further consideration. Interviews merely to restate arguments of record or to discuss new limitations will be denied. See MPEP § 714.13
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner Dzung Tran whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Supervisor Sue Purvis can be reached on 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DZUNG TRAN/
Primary Examiner, Art Unit 2893
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