Prosecution Insights
Last updated: July 17, 2026
Application No. 18/328,786

PACKAGE STRUCTURE AND PACKAGING METHOD

Final Rejection §103
Filed
Jun 05, 2023
Priority
Dec 05, 2022 — TW 111146524
Examiner
VALENZUELA, PATRICIA D
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Richtek Technology Corporation
OA Round
2 (Final)
90%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
647 granted / 717 resolved
+22.2% vs TC avg
Minimal +2% lift
Without
With
+2.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
63 currently pending
Career history
794
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
86.7%
+46.7% vs TC avg
§102
4.8%
-35.2% vs TC avg
§112
1.8%
-38.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 717 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 3-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dimaano Jr(USPGPUB DOCUMENT: 2019/0051585, hereinafter Dimaano Jr) in view of Kim (USPGPUB DOCUMENT: 2019/0237382, hereinafter Kim). Re claim 1 Dimaano Jr discloses in Fig 5d a package structure, comprising: a lead frame(410), including a die pad(112) and a plurality of lead pads(114) around the die pad(112); a chip die(130), disposed on the die pad(112), wherein the lead pads(114) are electrically connected with the chip die(130) via a plurality of lead wires(180/182), respectively; a thermal conductive adhesive layer(382), disposed on the chip die(130) at a same elevation level as a part of the lead wires(180/182) above the chip die(130); and a packaging material(185), encapsulating the lead frame(410), the chip die(130), the thermal conductive adhesive layer(382), and the lead frame(410) is exposed on a bottom surface of the package material; wherein the package structure includes an upper thermal conduction path(since 382 is thermally conductive this may be interpreted as the package structure includes an upper thermal conduction path) and a lower thermal conduction path(by way of 135/120)[0053,0054], the upper thermal conduction path passing through the chip die(130), the thermal conductive adhesive layer(382), and the lower thermal conduction path(by way of 135/120)[0053,0054] passing through the chip die(130) and the lead frame(410). Dimaano Jr does not disclose a thermal conductive plate, and the thermal conductive plate, wherein the thermal conductive plate is exposed on a top surface of the package material, the upper thermal conduction path passing through the chip die(130), the thermal conductive adhesive layer(382), and the thermal conductive plate, and the lower thermal conduction path passing through the chip die(130) and the lead frame(410); wherein the thermal conductive plate does not directly contact the lead frame. Dimaano Jr does not disclose wherein the thermal conductive plate does not directly contact the lead frame. Kim disclose in Fig 7 a thermal conductive plate(left130/right130), and the thermal conductive plate, wherein the thermal conductive plate(left130/right130) does not directly contact the lead frame(114). It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Kim to the teachings of Dimaano Jr in order to have a semiconductor package with improved reliability [0004, Kim]. wherein the thermal conductive plate(left130/right130 of Kim) is exposed on a top surface of the package material, the upper thermal conduction path passing through the chip die(130), the thermal conductive adhesive layer(382), and the thermal conductive plate, and the lower thermal conduction path passing through the chip die(130) and the lead frame(410); Re claim 3 Dimaano Jr and Kim disclose the package structure according to claim 1, wherein a part of the lead wires(180/182) above the chip die(130) are buried in the thermal conductive adhesive layer(382); or, a part of the lead wires(180/182) above the chip die(130) are disposed outside the thermal conductive adhesive layer(382). Re claim 4 Dimaano Jr and Kim disclose the package structure according to claim 1, wherein the lead frame(410), the chip die(130), the thermal conductive adhesive layer(382), and the thermal conductive plate are respectively disposed at different elevation levels. Re claim 5 Dimaano Jr and Kim disclose the package structure according to claim 1, wherein in a manufacturing process of the package structure, a plurality of thermal conductive plates are disposed on a tape by corresponding thermal conductive adhesive (382) layers, ; thereafter each set, including the thermal conductive plate and the thermal conductive adhesive layer is removed from the tape, to be disposed on a corresponding one of a plurality of chip die(130)s. The limitations “wherein in a manufacturing process of the package structure, a plurality of thermal conductive plates are disposed on a tape by corresponding thermal conductive adhesive (382) layers, ; thereafter each set, including the thermal conductive plate and the thermal conductive adhesive layer is removed from the tape, to be disposed on a corresponding one of a plurality of chip die(130)s” are(is) considered to be process limitations that do not carry weight in a claim drawn to structure. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), MPEP 2113. Re claim 6 Dimaano Jr and Kim disclose the package structure according to claim 1, wherein the package structure is applied to a package of quad flat no lead (QFN), quad flat package (QFP), ball grid array (BGA), land grid array (LGA), or dual flat no lead (DFN)[0019]. Re claim 7 Dimaano Jr and Kim disclose the package structure according to claim 1, wherein an exposed portion of the thermal conductive plate on the package material includes a shape of square, rectangular, circle, oval, triangular, or polygonal (Fig 4B). Response to Arguments Applicant’s arguments with respect to claim(s) 1 has/have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Jun 05, 2023
Application Filed
Jan 16, 2026
Non-Final Rejection mailed — §103
Mar 19, 2026
Response Filed
May 14, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12677712
SEMICONDUCTOR PACKAGE HAVING MULTIPLE REDISTRIBUTION LAYERS AND METHOD OF MAKING THE SAME
3y 0m to grant Granted Jul 07, 2026
Patent 12677656
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
2y 11m to grant Granted Jul 07, 2026
Patent 12672539
THIN FILM RESISTOR, THERMISTOR AND METHOD OF PRODUCING THE SAME
3y 0m to grant Granted Jun 30, 2026
Patent 12666951
SEMICONDUCTOR DEVICE
3y 1m to grant Granted Jun 23, 2026
Patent 12666952
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
3y 1m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
90%
Grant Probability
92%
With Interview (+2.1%)
2y 2m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 717 resolved cases by this examiner. Grant probability derived from career allowance rate.

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