DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/5/23 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 19 recites the limitation "further comprises a gate structure disposed on the nanosheet stack structure and the fin field-effect transistor further comprises a metal contact contacted with the gate structure of the nanosheet field-effect transistor" in lines 1-5 of the claim. This limitations creates confusion with the parent claim, Claim 17, as Claim 17 already includes “a first gate structure” and “a second gate structure” and it is unknown whether an additional gate is supposed to be created or whether the language is intended to refer to previously created elements.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 6-12, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Jagannathan et al. (US Patent No. 10,636,792)(“Jagannathan”) in view of Bi et al. (US Patent Application Publication No. 2020/0119015) (“Bi”) and Tomishima (US Patent Application Publication No. 2021/0151437) (“Tomishima”).
Regarding Claim 1, Jagannathan teaches a semiconductor structure, comprising: a field-effect transistor (see Figure 1, see bottom row of finFETs); and a fin field-effect transistor comprising a set of vertical fins (see Figure 1, see upper row of finFETs), wherein the nanosheet field-effect transistor and the fin field-effect transistor are in a stacked configuration (see Figure 1).
Jagannathan does not specifically teach the fin field effect transistors comprises an oxide semiconductor material. However, Tomishima teaches using oxide semiconductor fins in DRAMs (¶0014) it would have been obvious to a person having ordinary skill in the art at the time of effective filing to use oxide semiconductor material as taught by Tomishima as the fins of Jagannathan, since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960). MPEP § 2144.07.
Jagannathan as modified does not specifically teach the first row of transistors are nanosheet field-effect transistors comprising a nanosheet stack structure, however Jagannathan does teach other types of transistors are well-known to be used in place of finFET devices (column 4, lines 39-44). Bi teaches forming stacked CMOS transistors for out of nanosheet field effect transistors comprising a nanosheet stack structure (see Figure 20). It would have been obvious to a person having ordinary skill in the art at the time of effective filing to use the nanosheet structures of Bi in the device of Jagannathan, as Jagannathan indicates multiple types of transistors can be used in place of finFETs (column 4, lines 39-44) and it has been held that a conclusion of obviousness can be drawn from “combining prior art elements according to known methods to yield predictable results,” such as forming recesses in a interconnect area of a substrate, in KSR International Co. v. Teleflex Inc., 550 U.S. 398, 420, 82 USPQ2d 1385, 1397 (2007).
Regarding Claim 2, Jagannathan as modified further teaches the nanosheet field-effect transistor is in an orthogonal configuration relative to the fin field-effect transistor (see Figure 1, note certain bottom row transistors are orthogonal to certain upper row transistors).
Regarding Claim 3, Bi further teaches the nanosheet field-effect transistor further comprises a first source/drain region disposed on a first side of the nanosheet stack structure and a second source/drain region disposed on a second side of the nanosheet stack structure (see Figure 18, S/D regions 290 and associated text).
Regarding Claim 4, Bi further teaches the nanosheet field-effect transistor further comprises a first metal contact disposed on the first source/drain region and a second metal contact disposed on the second source/drain region (see Figure 20).
Regarding Claim 6, Bi further teaches the nanosheet field-effect transistor further comprises a first gate structure disposed on the nanosheet stack structure (See Figure 20) and Jagannathan teaches the fin field-effect transistor further comprises a second gate structure disposed on the set of vertical fins (see Figure 1).
Regarding Claim 7, Tomisha further teaches the oxide semiconductor material comprises at least one of an (InZnO)-based, (InGaO)-based, (InSnO)-based, (InGaZnO)-based, (InGaZnSnO)-based, (GaZnSnO)-based, (GaZnO)-based, (InSnZnO)-based or (FeInZnO)-based oxide semiconductor material (¶0014).
Regarding Claim 8, Tomisha further teaches a part of a dynamic random access memory cell (¶0014).
Regarding Claim 9, Jagannathan teaches one or more semiconductor structures, wherein at least one of the semiconductor structures comprises: a field-effect transistor (see Figure 1, see bottom row of finFETs); and a fin field-effect transistor comprising a set of vertical fins (see Figure 1, see upper row of finFETs), wherein the nanosheet field-effect transistor and the fin field-effect transistor are in a stacked configuration (see Figure 1).
Jagannathan does not specifically teach the fin field effect transistors comprises an oxide semiconductor material. However, Tomishima teaches using oxide semiconductor fins in DRAMs (¶0014) it would have been obvious to a person having ordinary skill in the art at the time of effective filing to use oxide semiconductor material as taught by Tomishima as the fins of Jagannathan, since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960). MPEP § 2144.07.
Jagannathan as modified does not specifically teach the first row of transistors are nanosheet field-effect transistors comprising a nanosheet stack structure, however Jagannathan does teach other types of transistors are well-known to be used in place of finFET devices (column 4, lines 39-44). Bi teaches forming stacked CMOS transistors for out of nanosheet field effect transistors comprising a nanosheet stack structure (see Figure 20). It would have been obvious to a person having ordinary skill in the art at the time of effective filing to use the nanosheet structures of Bi in the device of Jagannathan, as Jagannathan indicates multiple types of transistors can be used in place of finFETs (column 4, lines 39-44) and it has been held that a conclusion of obviousness can be drawn from “combining prior art elements according to known methods to yield predictable results,” such as forming recesses in a interconnect area of a substrate, in KSR International Co. v. Teleflex Inc., 550 U.S. 398, 420, 82 USPQ2d 1385, 1397 (2007).
Regarding Claim 10, Jagannathan as modified further teaches the nanosheet field-effect transistor is in an orthogonal configuration relative to the fin field-effect transistor (see Figure 1, note certain bottom row transistors are orthogonal to certain upper row transistors).
Regarding Claim 11, Bi further teaches the nanosheet field-effect transistor further comprises a first source/drain region disposed on a first side of the nanosheet stack structure and a second source/drain region disposed on a second side of the nanosheet stack structure (see Figure 18, S/D regions 290 and associated text).
Regarding Claim 12, Bi further teaches the nanosheet field-effect transistor further comprises a first metal contact disposed on the first source/drain region and a second metal contact disposed on the second source/drain region (see Figure 20).
Regarding Claim 14, Bi further teaches the nanosheet field-effect transistor further comprises a first gate structure disposed on the nanosheet stack structure (See Figure 20) and Jagannathan teaches the fin field-effect transistor further comprises a second gate structure disposed on the set of vertical fins (see Figure 1).
Regarding Claim 15, Tomisha further teaches the oxide semiconductor material comprises at least one of an (InZnO)-based, (InGaO)-based, (InSnO)-based, (InGaZnO)-based, (InGaZnSnO)-based, (GaZnSnO)-based, (GaZnO)-based, (InSnZnO)-based or (FeInZnO)-based oxide semiconductor material (¶0014).
Regarding Claim 16, Tomisha further teaches a part of a dynamic random access memory cell (¶0014).
Allowable Subject Matter
Claims 17, 18, and 20 are allowed.
Claims 5 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: None of the prior art, alone or in combination teaches all limitations of the claims, specifically including but not limited to “the fin field-effect transistor further comprises a read write line connected to the first metal contact of the nanosheet field-effect transistor and a read bit line connected to the second metal contact of the nanosheet field-effect transistor” of Claims 5, 13, and 17.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bao et al. (US Patent Application Publication No. 2024/0006480)
Vellantis (US Patent Application Publication No. 2021/0125986)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK W TORNOW whose telephone number is (571)270-7534. The examiner can normally be reached M-Th 6:30-4:30 EST.
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MARK W. TORNOW
Primary Examiner
Art Unit 2891
/MARK W TORNOW/Primary Examiner, Art Unit 2891
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