DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1, 14, and 24 have been considered but are moot because the new ground of rejection does not rely on an identical interpretation of the prior art applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s assertions (Applicant’s remarks pages 10-13) that the prior art of record does not teach the new limitations of amended independent claims 1, 14, and 24 are acknowledged. However, the disclosure of US 20230197706 A1 (Huang) is found to be highly pertinent to the consideration of the claims when an upper part of its first substrate 101 is considered to be part of the claimed “first bonding film”, particularly in view of obvious modifications based on the disclosures of US 20200335473 A1 (Zhou et al) and US 20070164458 A1 (Ogino et al).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 14, 17, and 21-30 are rejected under 35 U.S.C. 103 as being unpatentable over US patent publications US 20230197706 A1 (Huang) in view of US 20200335473 A1 (Zhou et al hereinafter Zhou) and US 20070164458 A1 (Ogino et al hereinafter Ogino).
Regarding claim 1, Huang discloses a package structure (the package structure of FIGS. 11-12 ¶ [0017-0018]), comprising: a first bonding film (FIG. 12, first conductive features 103 and upper half of first substrate 101 form a bonding film ¶ [0033]) formed on a first substrate (FIG. 12, lower half of first substrate 101 ¶ [0033]); a first alignment mark (FIGS. 11-12, first alignment marks 105 in first and fourth sets 1S and 4S, as well as portions of first bottom liner 107 which directly contact sidewalls and bottom surfaces of marks 105, are formed in first conductive features 103 ¶ [0044, 0048]) formed in the first bonding film, wherein the first alignment mark comprises a plurality of first patterns spaced apart from each other (FIGS. 11-12, first alignment marks 105 and discrete adjoining subsections of liner 107 are arranged in multiple spaced apart patterns in first and fourth sets 1S and 4S), and one of the first patterns comprises: a dielectric layer (FIG. 12, portion of liner 107 level with and under the upper surface of conductive features 103) disposed in a trench (FIG. 12, a trench in conductive features 103 filled by liner 107 and alignment mark 105) of the first bonding film and covering a bottom surface and a sidewall of the trench (FIG. 12, liner 107 covers bottom surface and sidewall of trench formed in conductive features 103);
a second bonding film (FIG. 12, second conductive features 203 forms a bonding film ¶ [0057]) formed on a second substrate (FIG. 12, second substrate 201 ¶ [0057]) and bonded to the first bonding film (FIG. 12, the second bottom liner 207 bonds to the first bottom liner 107 though top liners 109 and 209 ¶ [0057]); and a second alignment mark (FIGS. 11-12, second alignment marks 205 are formed in the second bonding film ¶ [0057]) formed in the second bonding film, wherein the second alignment mark comprises a plurality of second patterns spaced apart from each other (FIGS. 11-12, there is a plurality of spaced-apart alignment marks 205), wherein in a top view (FIG. 11 provides a top view), the first alignment mark is spaced apart from the second alignment mark (FIG. 11, alignment marks 105 and 205 are spaced apart from each other).
Huang does not further disclose a metal layer disposed in the dielectric layer so that the dielectric layer is sandwiched between the metal layer and the first bonding film in a direction perpendicular to the bottom surface, or that a distance between adjacent first patterns is less than a distance between the first alignment mark and the second alignment mark, such a distance comparison not being of particular importance to the disclosure of their invention. Additionally, in Huang the alignment marks are formed of fluorescent material such as azobenzene (¶ [0049]).
However, Zhou discloses a bonded device (the package structure of FIG. 4 having wafers 10 and 20 ¶ [0030, 0058]) wherein a first alignment mark and a second alignment mark (FIGS. 3-4, alignment marks 160 ¶ [0049]) may be formed of a “point array pattern” (FIG. 3, point array 162 ¶ [0049]), and that their point-array patterns can avoid a defect in dishing which may otherwise be caused by the patterns having a large area (¶ [0050]). If such a point-array pattern is applied to the alignment marks 105/205 of Huang (FIG. 11), the distance between the points of the point-array patterns is significantly less than the distance between each instance of first alignment marks 105 and second alignment marks 205.
Huang and Zhou both pertain to the field of semiconductor devices which use alignment marks when bonding devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Huang in view of Zhou to form the alignment marks using Zhou’s point array pattern to avoid a defect in dishing as taught by Zhou (¶ [0050]). In so doing, a distance between adjacent first patterns (distance between the points of the point-array in the first alignment marks) is less than a distance between the first alignment mark and the second alignment mark.
Further, Zhou discloses that their alignment marks are formed of a metal layer (bonding pad 150 and point array 162 of Zhou are both metal such as copper, Zhou ¶ [0048-0049]). In addition, Ogino discloses embodiments of molds comprising alignment patterns wherein metal patterns (FIG. 10B, rear face metal patterns 1003 ¶ [0077]) and fluorescent patterns (FIG. 10C, rear face fluorescent patterns 1004 ¶ [0077]) are both taught as acceptable alternatives (¶ [0077]), the molds of Ogino noted to be applicable to the recognized problem of fine-tuned alignment for semiconductor devices (¶ [0007]).
Huang, Zhou, and Ogino pertain to the field of alignment marks applied to semiconductor devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Huang in view of Zhou and Ogino to use a metal material such as that taught by Zhou in place of the fluorescent material taught by Huang, since the materials were demonstrated as interchangeable by Ogino for the purposes of forming alignment marks, and such a substitution may be found appropriate in consideration of materials costs and changing market conditions. Having done so, the first bonding film comprises a metal layer (Huang FIG. 12, alignment mark 105 in view of Zhou and Ogino is formed of metal) disposed in the dielectric layer (Huang FIG. 12, mark 105 is disposed in liner 107) so that the dielectric layer is sandwiched between the metal layer and the first bonding film in a direction perpendicular to the bottom surface (Huang FIG. 12, the upper half of substrate 101, liner 107, and alignment mark 105 are stacked such that liner 107 is sandwiched between mark 105 and upper half of substrate 101 along a vertical direction which is perpendicular to the bottom surface).
Regarding claim 2, Huang in view of Zhou and Ogino discloses the limitations of claim 1 as detailed above, and they further disclose that each of the first patterns comprises: a dielectric layer provided within the first bonding film (Huang FIG. 12, first bottom liner 107 is a dielectric layer provided within the first bonding film ¶ [0045-0046]), and a metal layer provided within the first bonding film (Huang FIG. 12 in view of Zhou and Ogino, mark 105 is formed of metal as discussed regarding claim 1 above) so that the dielectric layer is disposed between the metal layer and the first bonding film (Huang FIG. 12, liner 107 is between mark 105 and conductive features 103/upper half of first substrate 101).
As currently considered, Huang in view of Zhou and Ogino does not disclose that a top surface of the metal layer is substantially level with a top surface of the first bonding film. However, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found such a configuration obvious to arrive at in view of Huang and Zhou for the following reasons: Huang discloses that a chemical mechanical polishing process is used to planarize the metal layer (FIGS. 5-7, the alignment mark material 511 -> 105 is exposed by a planarizing process ¶ [0050]), as well as that the liner 107 may be at least partially removed over conductive features 103 to expose the conductive features for electrical coupling (Huang ¶ [0047]), and Zhou discloses, analogously, that a planarizing process is used to prepare the device for bonding, wherein a top surface of the metal layer (FIG. 4, point array 162 is the metal alignment mark layer ¶ [0049]) is substantially level with a top surface of the first bonding film (FIG. 4, bonding pad 150, protective layer 149, and point array 162 are planarized with substantially level top surfaces ¶ [0050]). This feature would be obvious to incorporate into the device of Huang by having the chemical mechanical polishing process (Huang ¶ [0050]) proceed further than is illustrated in Huang FIG. 7 such that a top surface of alignment mark 105, liner layer 107, and conductive features 103 all have substantially level top surfaces (a comparable configuration being illustrated in Zhou FIG. 4). Doing so would also reduce the thickness dimension of the device, a known variable that is often optimized in the art, as well as allow the conductive features of Huang to couple to other elements (Huang ¶ [0002, 0047]).
Regarding claim 3, Huang in view of Zhou and Ogino discloses the limitations of claim 1 as detailed above, and they further disclose that the first patterns and the second patterns are symmetrically arranged around a central axis, and the central axis is perpendicular to a top surface of the first substrate (annotated Huang FIG. 11 below, the intersection point represents a central axis which extends “through” the top-view cross-section and has alignment marks 105 and 205 in the 1S and 4S quadrants arranged symmetrically about it).
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Regarding claim 4, Huang in view of Zhou and Ogino discloses the limitations of claim 3 as detailed above, and they further disclose that the central axis is spaced apart from the first alignment mark and the second alignment mark in the top view (annotated Huang FIG. 11 above, the intersection point having the claimed central axis does not overlap either of alignment marks 105 or 205).
Regarding claim 5, Huang in view of Zhou and Ogino discloses the limitations of claim 1 as detailed above, and they further disclose that in the top view, either of the first patterns or the second patterns has a shape of a circle, an ellipse, a rounded rectangle, or a polygon (Huang FIG. 11, the alignment marks 105 and 205 are rectangular, which is polygonal).
Regarding claim 14, Huang discloses a package structure (the package structure of FIGS. 11-12 ¶ [0017-0018]), comprising: a first bonding film (FIG. 12, first conductive features 103 and the upper half of first substrate 101 form a bonding film ¶ [0033]) on a first package component (FIG. 12, lower half of first substrate 101 is a first package component ¶ [0033]), wherein a plurality of first trenches are formed in the first bonding film (FIG. 12, trenches filled by first bottom liner 107 and first alignment marks 105 are formed in first conductive features 103), a first plurality (FIG. 11, the alignment marks 105 in the first set 1S ¶ [0063]) and a second plurality (FIG. 11, the alignment marks 105 in the fourth set 4S ¶ [0066]) of first patterns are formed by a first dielectric material (FIG. 12, first bottom liner 107 contacting sidewalls of alignment marks 105 ¶ [0044-0046]) and a first material (FIG. 12, first alignment marks 105 ¶ [0048], which fills the trenches with liner 107) filled in the first trenches, and a distance between two adjacent first patterns in the first plurality of the first patterns is less than a distance between one of the first plurality of the first patterns and one of the second plurality of the first patterns (FIG. 11, alignment marks 105 in first set 1S are closer to each other than either of alignment marks 105 in fourth set 4S are to either of alignment marks 105 in first set 1S); and
a second bonding film (FIG. 12, second conductive features 203 forms a bonding film ¶ [0057]) on a second package component (FIG. 12, second substrate 201 is a second package component ¶ [0057]), wherein a plurality of second trenches are formed in the second bonding film (FIG. 12, trenches filled by second bottom liner 207 and second alignment marks 205 are formed in second conductive features 203), and a plurality of second patterns (FIG. 11, the alignment marks 205 in the first set 1S ¶ [0063]) are formed by a second dielectric material (FIG. 12, second bottom liner 207 contacting sidewalls of alignment marks 205 ¶ [0057]) and a second material (FIG. 12, second alignment marks 205 ¶ [0048], which fills the trenches with liner 207) filled in the second trenches, wherein the second package component is bonded to the first package component via the first bonding film and the second bonding film (FIG. 12, first and second substrates 101 and 201 are bonded to each other through first and second conductive films 103 and 203).
Huang does not disclose that the first bonding film comprises a dielectric material different from the first dielectric material, and the first dielectric material, the first conductive material, and the first bonding film overlap in a normal direction of the first package component, and that the first and second materials are conductive materials. In Huang, the alignment marks are formed of fluorescent material such as azobenzene (¶ [0049]), the liner is suggested to be formed of SiO, SiN, or SiON (¶ [0046]), and specific dielectric layer materials present in the conductive features 103 and substrate 101 are not discussed in particular detail, though it is mentioned that substrate 101 may include a plurality of non-shown dielectric layers (¶ [0034]) and that conductive features 103 may be configured as testing circuits (¶ [0043]).
However, the alignment marks of Zhou are formed of a metal layer (bonding pad 150 and point array 162 of Zhou are both metal such as copper, Zhou ¶ [0048-0049]). In addition, Ogino discloses embodiments of molds comprising alignment patterns wherein metal patterns (FIG. 10B, rear face metal patterns 1003 ¶ [0077]) and fluorescent patterns (FIG. 10C, rear face fluorescent patterns 1004 ¶ [0077]) are both taught as acceptable alternatives (¶ [0077]), the molds of Ogino noted to be applicable to the recognized problem of fine-tuned alignment for semiconductor devices (¶ [0007]).
Huang, Zhou, and Ogino pertain to the field of alignment marks applied to semiconductor devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Huang in view of Zhou and Ogino to use a metal material such as that taught by Zhou in place of the fluorescent material taught by Huang, since the materials were demonstrated as interchangeable by Ogino for the purposes of forming alignment marks, and such a substitution may be found appropriate in consideration of materials costs and changing market conditions. Having done so, the first and second materials are conductive materials, and it further follows that the first dielectric material, the first conductive material, and the first bonding film overlap in a normal direction of the first package component (Huang FIG. 12, the upper half of substrate 101, liner 107, and alignment mark 105 are stacked such that they overlap along a vertical direction, which is a normal direction of the lower half of substrate 101).
Furthermore, the package structure of Zhou includes a first bonding film (Zhou FIG. 4, dielectrics 130, 132, and cover 140 form a first bonding film in wafer 20 ¶ [0044-0046]) which comprises a dielectric material (e.g. borosilicate glass formed in dielectric layer 130 ¶ [0045]). The dielectric material of Zhou’s first bonding film provides insulation for a variety of transistor devices 110 (¶ [0043]), which a person of ordinary skill in the art before the effective filing date of the claimed invention would have found beneficial in insulating the various conductive features of Huang (e.g. the testing circuits of Huang ¶ [0043]). Therefore, in view of the teachings of Huang, Zhou, and Ogino, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Huang such that the first bonding film comprises a dielectric material different from the first dielectric material, (e.g. the dielectric material of the first bonding film is borosilicate glass per Zhou ¶ [0045], and the dielectric liner layer 107 of Huang is silicon nitride per Huang ¶ [0046]), in order to provide insulation materials for the liner and bonding film that ensure device functionality when arranging the testing circuits of Huang, and such selection of materials may be found beneficial in view of materials costs and changing market conditions.
Regarding claim 17, Huang in view of Zhou and Ogino discloses the limitations of claim 14 as detailed above, and they further disclose that a depth of the first trenches is less than a thickness of the first bonding film (Huang FIG. 12, as discussed regarding claim 14, the first bonding film is considered to include the upper half of first substrate 101, and liner 107 which lines the trenches does not extend halfway through first substrate 101).
Regarding claim 21, Huang in view of Zhou and Ogino discloses the limitations of claim 14 as detailed above, and they further disclose that a depth of the first dielectric material is greater than a depth of the first conductive material (Huang FIG. 12, first bottom liner 107 extends deeper into wafer 100 than first alignment marks 105).
Regarding claim 22, Huang in view of Zhou and Ogino discloses the limitations of claim 14 as detailed above. As currently considered, Huang in view of Zhou and Ogino does not disclose that top surfaces of the first dielectric material, the first conductive material, and the first bonding film are substantially coplanar with each other.
However, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found such a configuration obvious to arrive at in view of Huang and Zhou for the following reasons: Huang discloses that a chemical mechanical polishing process is used to planarize the metal layer (FIGS. 5-7, the alignment mark material 511 -> 105 is exposed by a planarizing process ¶ [0050]), as well as that the liner 107 may be at least partially removed over conductive features 103 to expose the conductive features for electrical coupling (Huang ¶ [0047]), and Zhou discloses, analogously, that a planarizing process is used to prepare the device for bonding, wherein top surfaces of the first dielectric material (Zhou FIG. 4, protective layer 149 is formed of a dielectric material), the first conductive material (Zhou FIG. 4, point array 162 is the metal alignment mark layer ¶ [0049]), and the first bonding film (Zhou FIG. 4, bonding pad 150 is part of a bonding film ¶ [0050]) are substantially coplanar with each other (Zhou FIG. 4, each of protective layer 149, point array 162, and bonding pad 150 are planarized to be substantially coplanar with each other ¶ [0050]). This feature would be obvious to incorporate into the device of Huang by having the chemical mechanical polishing process (Huang ¶ [0050]) proceed further than is illustrated in Huang FIG. 7 such that a top surface of alignment mark 105, liner layer 107, and conductive features 103 all have substantially level top surfaces (a comparable configuration being illustrated in Zhou FIG. 4). Doing so would also reduce the thickness dimension of the device, a known variable that is often optimized in the art, as well as allow the conductive features of Huang to couple to other elements (Huang ¶ [0002, 0047]).
Regarding claim 23, Huang in view of Zhou and Ogino discloses the limitations of claim 14 as detailed above, and they further disclose that the second trenches are formed to have the same width (Huang FIGS. 11-12, the second trenches in wafer 200 are formed having the same widths among each other; see also MPEP 2125 I).
Regarding claim 24, Huang discloses a package structure (the package structure of FIGS. 11-12 ¶ [0017-0018]), comprising: a first bonding film (FIG. 12, first conductive features 103 and the upper half of first substrate 101 form a bonding film ¶ [0033]) on a first substrate (FIG. 12, lower half of first substrate 101 ¶ [0033]); a first alignment mark (FIGS. 11-12, first alignment marks 105 in first and fourth sets 1S and 4S, as well as portions of first bottom liner 107 which directly contact sidewalls and bottom surfaces of marks 105, are formed in first conductive features 103 ¶ [0044, 0048]) formed in the first bonding film, wherein the first alignment mark comprises a plurality of first patterns (FIGS. 11-12, first alignment marks 105 and discrete adjoining subsections of liner 107 are arranged in multiple spaced apart patterns in first and fourth sets 1S and 4S) spaced apart from each other, and one of the first patterns comprises: a dielectric layer (FIG. 12, portion of liner 107 level with and under the upper surface of conductive features 103) disposed in a trench (FIG. 12, a trench in conductive features 103 filled by liner 107 and alignment mark 105) of the first bonding film,
a second bonding film (FIG. 12, second conductive features 203 forms a bonding film ¶ [0057]) on a second substrate (FIG. 12, second substrate 201 which is positioned over first substrate 101 ¶ [0057]) over the first substrate; a second alignment mark formed in the second bonding film (FIGS. 11-12, second alignment marks 205 in first and fourth sets 1S and 4S are formed in second conductive features 203 ¶ [0057]), wherein the second alignment mark comprises a plurality of second patterns (FIGS. 11-12, second alignment marks 205 are arranged in multiple spaced apart patterns in first and fourth sets 1S and 4S) spaced apart from each other, wherein a first central axis of the first alignment mark is aligned with a second central axis of the second alignment mark (annotated Huang FIG. 11 below, which illustrates that the central axes of the first and second alignment marks are aligned at the intersection point; see also MPEP 2125 I), a distance between adjacent two of the first patterns (FIG. 11, the two first alignment marks 105 adjacent to each other in first set 1S) is less than a distance between one of the first patterns and one of the second patterns (FIG. 11, either of the first alignment marks 105 in first set 1S are closer to each other than they are to either of the second alignment marks 205 in fourth set 4S, in a direction perpendicular to the first central axis) in a direction perpendicular to the first central axis.
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Huang does not explicitly disclose that the first bonding film comprises a dielectric material different from the dielectric layer; and a metal layer disposed in the dielectric layer so that the dielectric layer, the metal layer, and the first bonding film overlap in a direction perpendicular to a normal direction of the first substrate. In Huang, the alignment marks are formed of fluorescent material such as azobenzene (¶ [0049]), the liner is suggested to be formed of SiO, SiN, or SiON (¶ [0046]), and specific dielectric layer materials present in the conductive features 103 and substrate 101 are not discussed in particular detail, though it is mentioned that substrate 101 may include a plurality of non-shown dielectric layers (¶ [0034]) and that conductive features 103 may be configured as testing circuits (¶ [0043]).
Further, Zhou discloses a bonded device (the package structure of FIG. 4 having wafers 10 and 20 ¶ [0030, 0058]), and the alignment marks of Zhou are formed of a metal layer (bonding pad 150 and point array 162 of Zhou are both metal such as copper, Zhou ¶ [0048-0049]). In addition, Ogino discloses embodiments of molds comprising alignment patterns wherein metal patterns (FIG. 10B, rear face metal patterns 1003 ¶ [0077]) and fluorescent patterns (FIG. 10C, rear face fluorescent patterns 1004 ¶ [0077]) are both taught as acceptable alternatives (¶ [0077]), the molds of Ogino noted to be applicable to the recognized problem of fine-tuned alignment for semiconductor devices (¶ [0007]).
Huang, Zhou, and Ogino pertain to the field of alignment marks applied to semiconductor devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Huang in view of Zhou and Ogino to use a metal material such as that taught by Zhou in place of the fluorescent material taught by Huang, since the materials were demonstrated as interchangeable by Ogino for the purposes of forming alignment marks, and such a substitution may be found appropriate in consideration of materials costs and changing market conditions. Having done so, the first bonding film comprises a metal layer (Huang FIG. 12, alignment mark 105 in view of Zhou and Ogino is formed of metal) disposed in the dielectric layer (Huang FIG. 12, mark 105 is disposed in liner 107) so that the dielectric layer, the metal layer, and the first bonding film overlap in a direction perpendicular to a normal direction of the first substrate (“a direction perpendicular to a normal direction of the first substrate” understood to represent a vertical direction, Huang FIG. 12, the upper half of substrate 101, liner 107, and alignment mark 105 are stacked such that they overlap along that vertical direction).
Furthermore, the package structure of Zhou includes a first bonding film (Zhou FIG. 4, dielectrics 130, 132, and cover 140 form a first bonding film in wafer 20 ¶ [0044-0046]) which comprises a dielectric material (e.g. borosilicate glass formed in dielectric layer 130 ¶ [0045]). The dielectric material of Zhou’s first bonding film provides insulation for a variety of transistor devices 110 (¶ [0043]), which a person of ordinary skill in the art before the effective filing date of the claimed invention would have found beneficial in insulating the various conductive features of Huang (e.g. the testing circuits of Huang ¶ [0043]). Therefore, in view of the teachings of Huang, Zhou, and Ogino, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Huang such that the first bonding film comprises a dielectric material different from the dielectric layer (e.g. the dielectric material of the first bonding film is borosilicate glass per Zhou ¶ [0045], and the dielectric liner layer 107 of Huang is silicon nitride per Huang ¶ [0046]), in order to provide insulation materials for the liner and bonding film that ensure device functionality when arranging the testing circuits of Huang, and such selection of materials may be found beneficial in view of materials costs and changing market conditions.
Regarding claim 25, Huang in view of Zhou and Ogino discloses the limitations of claim 24 as detailed above, and Huang further discloses that the first patterns are formed symmetrically about the first central axis (annotated Huang FIG. 11 above, first alignment marks 105 in first and fourth sets 1S and 4S are formed symmetrically about the first central axis; see also MPEP 2125 I).
Regarding claim 26, Huang in view of Zhou and Ogino discloses the limitations of claim 24 as detailed above, and while Huang does not explicitly disclose that a top surface of the first alignment mark is substantially coplanar with a top surface of the first bonding film, Zhou discloses a package structure (the package structure of FIG. 4 having wafers 10 and 20 ¶ [0030, 0058]), comprising: a top surface of a first alignment mark (Zhou FIG. 4, point array 162 is a first alignment mark ¶ [0049]) that is substantially coplanar with a top surface of a first bonding film (Zhou FIG. 4, bonding pad 150 and point array 162 are planarized with substantially level top surfaces ¶ [0050]).
Huang and Zhou both pertain to the field of semiconductor devices which use alignment marks when bonding devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found such a configuration obvious to arrive at in view of Huang and Zhou for the following reasons: Huang discloses that a chemical mechanical polishing process is used to planarize the metal layer (FIGS. 5-7, the alignment mark material 511 -> 105 is exposed by a planarizing process ¶ [0050]), as well as that the liner 107 may be at least partially removed over conductive features 103 to expose the conductive features for electrical coupling (Huang ¶ [0047]), and Zhou discloses that a top surface of the first alignment mark is substantially coplanar with a top surface of the first bonding film (as described above). This feature would be obvious to incorporate into the device of Huang by having the chemical mechanical polishing process (Huang ¶ [0050]) proceed further than is illustrated in Huang FIG. 7 such that a top surface of alignment mark 105, liner layer 107, and conductive features 103 all have substantially level top surfaces (a comparable configuration being illustrated in Zhou FIG. 4). Doing so would reduce the thickness dimension of the device, a known variable that is often optimized in the art, as well as allow the conductive features of Huang to couple to other elements (Huang ¶ [0002, 0047]).
Regarding claim 27, Huang in view of Zhou and Ogino discloses the limitations of claim 24 as detailed above, and Huang further discloses that the first alignment mark is mismatched with the second alignment mark in a direction parallel to the first central axis (Huang FIG. 11, the first alignment marks 105 and the second alignment marks 205 do not overlap each other along the direction that the central axis is located in, which corresponds to the “Z” direction of FIG. 12 ¶ [0029, 0039]).
Regarding claim 28, Huang in view of Zhou and Ogino discloses the limitations of claim 24 as detailed above and further discloses that the first alignment mark comprises a first dielectric material (Huang FIG. 12, portions of first bottom liner 107 which directly contact sidewalls and bottom surfaces of marks 105 ¶ [0044]) and a first conductive material (FIGS. 11-12, first alignment marks 105 in first and fourth sets 1S and 4S are formed on liner 107 ¶ [0048], and Huang in view of Zhou and Ogino uses a metal material as described regarding claim 24 above) on the first dielectric material, and a top surface of the first dielectric material is substantially coplanar with a top surface of the first material (FIG. 12, the top surfaces of first bottom liner 107 and first alignment marks 105 are substantially coplanar with each other ¶ [0050]).
Regarding claim 29, Huang in view of Zhou and Ogino discloses the limitations of claim 28 as detailed above and further discloses that the first dielectric material covers a bottom surface and a sidewall of the first conductive material (Huang FIG. 12, first bottom liner 107 covers a bottom surface and a sidewall of first alignment marks 105).
Regarding claim 30, Huang in view of Zhou and Ogino discloses the limitations of claim 24 as detailed above, and Huang further discloses that the first patterns are formed to have the same width (Huang FIGS. 11-12, the first alignment patterns 105 in wafer 100 are formed having the same widths among each other; see also MPEP 2125 I).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Zhou and Ogino as applied to claim 1 above, and further in view of US patent publication US 20230230931 A1 (Arulalan et al hereinafter Arulalan).
Huang in view of Zhou and Ogino discloses the limitations of claim 1 as detailed above, but they do not explicitly disclose that in the top view, each of the first patterns and second patterns has an area of about 0.1 µm^2 to about 30µm^2 an area for the patterns not being specifically quantified as that was not a point of particular importance to the disclosure of their invention. Zhou does state that their point-array patterns can avoid a defect in dishing which may otherwise be caused by the patterns having a large area (¶ [0050]), the area of the patterns therefore being a result-effective variable.
Arulalan further discloses a semiconductor device comprising alignment marks (e.g. the device of FIG. 2B ¶ [0020]) and a mask for forming the alignment marks (the hardmask layer of FIG. 1 ¶ [0018]) wherein the dimensions of the alignment mark openings and masking areas may accommodate the same orders of magnitude as those of the claimed range of areas (the widths and pitches of the openings both may range at less than 1 µm or several µm, ¶ [0038-0039]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the areas of the first patterns and second patterns in the device of Huang in view of Zhou and Ogino as it has been taught to be a result-effective variable (Zhou ¶ [0050]). Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a configuration wherein in the top view, each of the first patterns and second patterns has an area of about 0.1 µm^2 to about 30µm^2, in order to achieve a desirable area for the alignment marks which avoids the dishing defect but also allows for precise aligning, such areas for alignment marks being known and achievable in the art as demonstrated by Arulalan (¶ [0038-0039]). See also MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the claimed range of areas is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Zhou and Ogino as applied to claim 14 above, and further in view of Arulalan.
Regarding claim 15, Huang in view of Zhou and Ogino discloses the limitations of claim 14 as detailed above, but they do not further disclose that the distance between two adjacent first patterns in the first plurality of the first patterns is about 0.1 µm to about 2 µm, a quantification of the amount of spacing between the first patterns not being a parameter of particular importance to the disclosure of their invention. Zhou does state that their point-array patterns can avoid a defect in dishing which may otherwise be caused by the patterns having a large area (¶ [0050]), the area of the patterns therefore being a result-effective variable.
Arulalan further discloses a semiconductor device comprising alignment marks (e.g. the device of FIG. 2B ¶ [0020]) and a mask for forming the alignment marks (the hardmask layer of FIG. 1 ¶ [0018]) wherein the dimensions of the alignment mark openings and masking areas may accommodate the same orders of magnitude as those of the claimed range of areas (the widths and pitches of the openings both may range at less than 1 µm or several µm, ¶ [0038-0039]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the distances between two adjacent first patterns in the first plurality of the first patterns in the device of Huang as the area of alignment marks has been taught to be a result-effective variable (Zhou ¶ [0050]). Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a configuration wherein the distance between two adjacent first patterns in the first plurality of the first patterns is about 0.1 µm to about 2 µm, in order to achieve a desirable area for the alignment marks which avoids the dishing defect but also allows for precise aligning, such spacings for alignment marks being known and achievable in the art as demonstrated by Arulalan (¶ [0038-0039]). See also MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the claimed range of distances is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Regarding claim 16, Huang in view of Zhou and Ogino discloses the limitations of claim 14 as detailed above, but they do not further disclose that an area of each of the first trenches is not greater than 30µm^2 on a plane parallel to a top surface of the first package component, a quantification of the areas of the trenches on a plane parallel to a top surface of the first package component not being a parameter of particular importance to the disclosure of their invention. Zhou does state that their point-array patterns can avoid a defect in dishing which may otherwise be caused by the patterns having a large area (¶ [0050]), the area of the patterns therefore being a result-effective variable.
Arulalan further discloses a semiconductor device comprising alignment marks (e.g. the device of FIG. 2B ¶ [0020]) and a mask for forming the alignment marks (the hardmask layer of FIG. 1 ¶ [0018]) wherein the dimensions of the alignment mark openings and masking areas may accommodate the same orders of magnitude as those of the claimed range of areas (the widths and pitches of the openings both may range at less than 1 µm or several µm, ¶ [0038-0039]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the area of each of the first trenches as the area of alignment marks has been taught to be a result-effective variable (Zhou ¶ [0050]). Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a configuration wherein an area of each of the first trenches is not greater than 30µm^2 on a plane parallel to a top surface of the first package component, in order to achieve a desirable area for the alignment marks which avoids the dishing defect but also allows for precise aligning, such spacings for alignment marks being known and achievable in the art as demonstrated by Arulalan (¶ [0038-0039]). See also MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the claimed range of areas is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US patent publication US 20230122531 A1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.R.C./Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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