DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Amendment filed 2/10/2026.
Claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 6/5/2024 and 10/22/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Species I in the reply filed on 2/10/2026 is acknowledged.
Claims 6-7 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Note, claim 7 is withdrawn for being dependent on withdrawn claim 6. Election was made without traverse in the reply filed on 2/1/2026.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claimed subject matter of claim 19 must be shown or the feature(s) canceled from the claim(s). For example, claim 19 recites the limitation “wherein the metal via extends laterally beyond respective edges of the through-via, and the metal via physically contacts the dielectric isolation layer”, which does not appear to be shown in the Drawings of the current application. As shown in Figures 5-7 and 9-14 of the Drawings it appears that the metal via 40 does not extend beyond the respective edges of though-via 16 and does not physically contact the dielectric isolation layer 38. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 2021/0225809 A1, hereinafter “Yu”).
Regarding independent claim 17, Yu discloses a method comprising:
forming a package comprising:
forming a first redistribution structure 210 (“interconnect device”- ¶0020) (see Fig. 2B); and
bonding a device die 100 (“peripheral device”- ¶0016) over the first redistribution structure 210 (see Fig. 3A), wherein the device die 100 comprises:
a semiconductor substrate 102 (“semiconductor substrate”- ¶0016);
an integrated circuit 104 (“devices”- ¶0017) at a front surface of the semiconductor substrate 102;
a dielectric isolation layer 110 (specifically the “dielectric layers of interconnect structure 110”- ¶0017) contacting a back surface of the semiconductor substrate 102;
a through-via 112 (“through-vias”- ¶0018) penetrating through the semiconductor substrate 102 and the dielectric isolation layer 110; and
a metal via 108 (“pads…metal”- ¶0019) contacting the through-via 112, since 108 indirectly contacts 112; and
forming a second redistribution structure 316 (“metallization pattern”- ¶0029) over the device die, 100 wherein the second redistribution structure 316 is electrically connected to the first redistribution structure 210 through the through-via 112 (¶0029) (see Fig. 3D).
Regarding claim 19, Yu discloses wherein the metal via 108 extends laterally beyond respective edges of the through-via 112, and the metal via 108 physically contacts the dielectric isolation layer 110 (see Fig. 3D).
Regarding claim 20, Yu discloses wherein the dielectric isolation layer 110 comprises an inorganic dielectric material (i.e., silicon oxide) (¶0017).
Allowable Subject Matter
Claims 1-5 and 8-16 are allowed.
Regarding independent claim 1, Yu discloses a method comprising:
bonding a composite die 100 (“peripheral device”- ¶0016) on a redistribution structure 210 (“interconnect device”- ¶0020) (see Fig. 3A), wherein the composite die 100 comprises:
a device die (i.e., “integrated circuit die”- ¶0016) comprising:
a semiconductor substrate 102 (“semiconductor substrate”- ¶0016); and
a through-semiconductor via 112 (“through-vias”- ¶0018) penetrating through the semiconductor substrate 102;
a metal via 108 (“pads…metal”- ¶0019) at a surface of the device die; and
encapsulating the composite die 100 in an encapsulant 310 (“dielectric material”- ¶0027) (see Fig. 3B);
performing a planarization process on the composite die 100 and the encapsulant 310 (¶0028) (see Fig. 3C); and
forming a conductive feature 316 (“metallization pattern”- ¶0029) electrically coupling to the metal via 108 (see Fig. 3D).
Yu does not expressly disclose a sacrificial carrier attached to the device die and wherein the sacrificial carrier is removed to reveal the metal via.
Thus, regarding independent claim 1, the claim is allowed, because the prior art of record including Yu, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “a sacrificial carrier attached to the device die” and “performing a planarization process on the composite die and the encapsulant, wherein the sacrificial carrier is removed to reveal the metal via”.
Claims 2-5 and 8-11 are allowed as being dependent on allowed claim 1.
Regarding independent claim 12, Tsou et al. (US 2021/0375768 A1, hereinafter “Tsou”) discloses a method comprising:
forming a device wafer 300 (“wafer”- ¶0039) comprising:
performing a backside grinding process on a backside of a semiconductor substrate 410 (“silicon substrate”- ¶0029), so that a through-via 414 (“via structures”- ¶0029) is revealed from the backside of the semiconductor substrate 410 (¶0037) (see Figs. 1C-1D);
recessing the semiconductor substrate 410 from the backside, wherein a portion of the through-via 414 protrudes out of the semiconductor substrate 410 (¶0038) (see Figs. 1D-1E);
forming a dielectric isolation layer 431 (“insulating layer”- ¶0039) on a back surface of the semiconductor substrate 410, wherein the through-via 414 is revealed through the dielectric isolation layer 431 (see Fig. 1F);
forming a metal via 438 (“metal pads”- ¶0041) contacting the through-via 414 (see Fig. 1F); and
forming a dielectric layer 432 (“dielectric material”- ¶0040), wherein the metal via 438 is in the dielectric layer 432 (see Fig. 1F).
Tsou does not expressly disclose attaching a sacrificial carrier to the device wafer to form a composite wafer and sawing the composite wafer into a plurality of composite dies, wherein the sacrificial carrier is also sawed as sacrificial dies.
Thus, regarding independent claim 12, the claim is allowed, because the prior art of record including Tsou, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “attaching a sacrificial carrier to the device wafer to form a composite wafer” and “sawing the composite wafer into a plurality of composite dies, wherein the sacrificial carrier is also sawed as sacrificial dies”.
Claims 13-16 are allowed as being dependent on allowed claim 12.
Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 18, the prior art of record including Yu and/or Tsou, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “[the method]… comprising: encapsulating the device die in an encapsulant, wherein when the device die is encapsulated, the device die is attached to a sacrificial carrier; and polishing the encapsulant, wherein the sacrificial carrier is removed during the polishing”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Chen et al. (US 2021/0134704 A1), which discloses a method of forming a semiconductor package comprising forming through vias in a device die.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm.
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/JAY C CHANG/Primary Examiner, Art Unit 2817