DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 6-8 are withdrawn. Claims 1-5 and 9-20 are present for examination.
Information Disclosure Statement
The information disclosure statements (IDS) filed on September 08, 2023, November 07, 2025, and February 12, 2026 are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Method of Solder Reflow Fusing for Manufacturing Electronic Packages and Electronic Assemblies.
Election/Restrictions
Claim 6 (from which claims 7 and 8 depend) are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species (i.e. Species II), there being no allowable generic or linking claim. Election was made without traverse in the reply filed on February 12, 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 11, 15, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “substantially” in claims 1, 11, 15, and 20 is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
Regarding claims 1 and 15, it is unclear what defines “… the first mold structure extends over at least part of the first side of the substrate to substantially encapsulate the group of through-mold connections …”
Regarding claim 11, it is unclear what defines “… the group of through-mold connections being substantially flush with an outer surface of the first mold substrate …”
Regarding claim 20, it is unclear what defines “… an exposed face of each through-mold connections is substantially flush with an outer surface of the first mold structure …”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 9-12, 14, 16-17, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwon (US 2019/0355667 A1).
Claim 1, Kwon discloses a method for manufacturing an electronic package (semiconductor package 30 is an electronic package, hereinafter, electronic package 30, [0067], Fig. 3), the method comprising:
providing a substrate (lower substrate 100 is a substrate, hereinafter, substrate 100, [0040], Figs. 1A and 1B) having a first side (upper surface 100u of substrate 100 within a first region R1, hereinafter, first side 100u of substrate 100, [0046], Figs. 1A and 1B) and a second side (upper surface of insulating layer 610 is opposite to upper surface 100u of substrate 100, hereinafter, second side 610u, [0046], Figs. 1A and 1B);
arranging a group of through-mold connections (connection structure 400’ is a group of through-mold connections, hereinafter, group of through-mold connections 400’, [0062], Figs. 1A/1B, 2A/2B, and 3) that are electrically conductive on the first side 100u of the substrate 100 (group of through-mold connections 400’ are electrically conductive on the first side 100u of the substrate 100, [0046], Figs. 1A and 1B), the group of through-mold connections 400’ configured to be coupled to a circuit board (the group of through-mold connections 400’ is configured coupled to a lower substrate 100, wherein the lower substrate 100 may be a circuit board, hereinafter, circuit board 100 or substrate 100, [0068], Fig. 3) by a corresponding group of intermediate solder portions (lower solder connection portion 451 and upper solder connection portion 452 are corresponding group of intermediate solder portions, hereinafter, corresponding group of intermediate solder portions 451/452, [0064], Figs. 1A/1B, 2A/2B, and 3), the through-mold connections 400’ having a melting point in excess of a melting point of the intermediate solder portions 451/452 (through-mold connections 400’ have a higher melting point than the melting point of the intermediate solder portions 451/452, [0064], Figs. 1A/1B, 2A/2B, and 3);
mounting a first electronic module (semiconductor chips 210 is a first electronic module, hereinafter, first electronic module 210, [0040, Figs. 1A/2A and 3) to the first side 100u of the substrate 100 (first electronic module 210 is mounted to the first side 100u of the substrate 100, [0040, Figs. 1A/2A and 3);
applying a first mold structure (lower molding film 500 is a first mold structure, hereinafter, first mold structure 500, [0059], Fig. 3) to the first side of the substrate 100u such that the first mold structure 500 extends over at least part of the first side 100u of the substrate 100 to substantially encapsulate the group of through-mold connections 400’ (first mold structure 500 extends over at least part of the first side of the substrate 100u to substantially encapsulate the group of through-mold connections 400’, [0059], Fig. 3); and
removing a portion of the first mold structure 500 to expose the group of through-mold connections 400 (to expose the group of through-mold connections 400 a portion of the first mold structure 500 was removed, [0059], Fig. 3).
Claim 2, Kwon discloses the method (electronic package 30, [0067], Fig. 3) of claim 1, in which an outer surface of the first mold structure 500 is free of any moat or channel circumscribing and adjacent to each of the through-mold connections 400 during the method (an outer surface of the first mold structure 500 is free of any moat or channel circumscribing and adjacent to each of the through-mold connections 400 during the method, Fig. 3).
Claim 9, Kwon discloses the method (electronic package 30, [0067], Fig. 3) of claim 1 in which the step of applying a first mold structure 500 to the first side 100u of the substrate 100 comprises encapsulating at least part of the first electronic module 210 in the first mold structure 500 (first electronic module 210 is encapsulated within the first mold structure 500, [0059], Fig. 3).
Claim 10, Kwon discloses the method (electronic package 30, [0067], Fig. 3) of claim 1 further comprising:
mounting a second electronic component (third semiconductor chip 720 is a second electronic component, hereinafter, second electronic component 720, [0068], Fig. 3) to the second side 610u of the substrate 100 (second electronic component 720 is mounted to the second side 610u of the substrate 100, [0068], Fig. 3), and
applying a second mold structure (upper molding film 730 is a second mold structure, hereinafter, second mold structure 730, [0068], Fig. 3) to the second side 610u of the substrate such that the second mold structure 730 extends over at least part of the second side 610u of the substrate 100 (second mold structure 730 extends over at least part of the second side 610u of the substrate 100, [0068], Fig. 3).
Claim 11, Kwon discloses the method (electronic package 30, [0067], Fig. 3) of claim 1 in which the step of removing a portion of the first mold structure 500 to expose the group of through-mold connections 400’ is performed so as to provide an exposed face of each of the group of through-mold connections 400’ being substantially flush with an outer surface of the first mold structure 500 (an exposed face of each of the group of through-mold connections 400’ is provided as being substantially flush with an outer surface of the first mold structure 500, [0059], Figs. 1A/1B, 2A/2B, and 3).
Claim 12, Kwon discloses the method (electronic package 30, [0067], Fig. 3) of claim 1 further comprising:
providing the corresponding group of intermediate solder portions 451/452; and
fusing each intermediate solder portion 451/452 directly to an end face of a corresponding one of the group of through-mold connections 400’ (each intermediate solder portion 451/452 is directly fused to an end face of a corresponding one of the group of through-mold connections 400’, [0047], Figs. 2B and 3).
Claim 14, Kwon discloses the method (electronic package 30, [0067], Fig. 3) of claim 12 in which the step of fusing each intermediate solder portion 451/452 directly to an end face of a corresponding one of the group of through-mold connections 400’ is performed such that each intermediate solder portion 451/452 protrudes above an outer surface of the first mold structure 500 (each intermediate solder portion 451/452 protrudes above an outer surface of the first mold structure 500 in order to electrically connect to the lower pad 621 within the above lying interposer substrate 600, [0048], Figs. 2A and 3).
Claim 16, Kwon discloses a method of manufacturing an electronic assembly (semiconductor package 30 is an electronic package, hereinafter, electronic package 30, [0067], Fig. 3), the method comprising:
encapsulating an electronic module (semiconductor chips 210 is an electronic module, hereinafter, electronic module 210, [0040, Figs. 1A/2A and 3) and electrically conductive through-mold connections (connection structure 400’ is a group of electrically conductive through-mold connections, hereinafter, electrically conductive through-mold connections 400’, [0046] and [0062], Figs. 1A/1B, 2A/2B, and 3) with a mold structure (lower molding film 500 is a mold structure, hereinafter, mold structure 500 encapsulating an electronic module 210 and electrically conductive through-mold connections 400’, [0059], Fig. 3), the electronic module 210 and the electrically conductive through-mold connections 400’ being positioned on a first side of a substrate (upper surface 100u of substrate 100, [0046], Figs. 1A and 1B);
removing a portion of the mold structure 500 to expose the electrically conductive through-mold connections 400’ (to expose the group of through-mold connections 400’ a portion of the first mold structure 500 was removed, [0059], Fig. 3); and
electrically connecting the electrically conductive through-mold connections 400 to a circuit board (the group of through-mold connections 400 is configured coupled to a lower substrate 100, wherein the lower substrate 100 may be a circuit board, hereinafter, circuit board 100 or substrate 100, [0068], Fig. 3) using solder connections (lower solder connection portion 451, upper solder connection portion 452 and conductive terminal 750 electrically connects the electrically conductive through-mold connections 400 to a circuit board 100 and is formed of a solder material, [0064] and [0069], Fig. 3), the electrically conductive through-mold connections 400 having a melting point that is higher than a melting point the solder connections 451/452/750 (through-mold connections 400 have a higher melting point than the melting point of the intermediate solder portions 451/452, [0064], Figs. 1A/1B, 2A/2B, and 3).
Claim 17, Kwon discloses the method (electronic package 30, [0067], Fig. 3) of claim 16 wherein an outer surface of the first mold structure 500 is free of any moat or channel circumscribing and adjacent to each of the through-mold connections 400 after performing the method (an outer surface of the first mold structure 500 is free of any moat or channel circumscribing and adjacent to each of the through-mold connections 400 after performing the method, Fig. 3).
Claim 19, Kwon discloses the method (electronic package 30, [0067], Fig. 3) of claim 16 wherein the electrically connecting includes reflowing the solder connections 451/452/750 without melting the electrically conductive through-mold connections 400 (solder connection 750 is formed by a reflow process, leaving the electrically conductive through-mold connections 400 with a higher melting point un-melted, [0069], Fig. 3).
Claim 20, Kwon discloses the method (electronic package 30, [0067], Fig. 3) of claim 16 wherein an exposed face of each through-mold connections 400 is substantially flush with an outer surface of the first mold structure 500 after the removing (an exposed face of each through-mold connections 400 is substantially flush with an outer surface of the first mold structure 500 after the removing, [0048], Fig. 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-5, 13, 15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Ishii (US 2023/0223317 A1).
Claim 3, Kwon discloses the method (electronic package 30, [0067], Fig. 3) of claim 1.
Kwon does not explicitly disclose wherein the melting point of the through-mold connections exceed the melting point of the intermediate solder portions by at least 10 degrees Celsius.
However, Ishii discloses wherein the melting point of the through-mold connections (Ishii, the high-melting-point solder-bonding is the material used to form the through-mold connections, [0056], Fig. 1; Kwon, Fig. 3) exceed the melting point of the intermediate solder portions (Ishii, the low-melting-point solder-bonding is the material used to form the intermediate solder portions, [0056], Fig. 1; Kwon, Fig. 3) by at least 10 degrees Celsius (Ishii, the melting point of the high-melting-point solder-bonding material is at least 10 degrees Celsius (i.e. 30 degrees Celsius) higher than the low-melting-point solder-bonding material, [0056], Fig. 1; Kwon, Fig. 3). The combination to utilize an alloy of tin and antimony would specifically manipulate the melting point of the solder material as compared to the materials used to form the through-mold connections to ensure melting of only the lower melting point material during subsequent reflow processing (Ishii, [0050]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an alloy of tin and antimony would specifically manipulate the melting point of the solder material as compared to the materials used to form the through-mold connections to ensure melting of only the lower melting point material during subsequent reflow processing (Ishii, [0050]).
Claim 4, Kwon discloses the method (electronic package 30, [0067], Fig. 3) of claim 1.
Kwon does not explicitly disclose wherein the through-mold connections are formed of an alloy including tin and antimony.
However, Ishii discloses the through-mold connections formed of an alloy including tin and antimony (Ishii, high-melting-point solder-bonding material includes tin which contains antimony, [0056], Fig. 1; Kwon, through-mold connections 400, [0064], Fig. 3). The combination to utilize an alloy of tin and antimony would specifically manipulate the melting point of the solder material as compared to the materials used to form the through-mold connections to ensure melting of only the lower melting point material during subsequent reflow processing (Ishii, [0050]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an alloy of tin and antimony would specifically manipulate the melting point of the solder material as compared to the materials used to form the through-mold connections to ensure melting of only the lower melting point material during subsequent reflow processing (Ishii, [0050]).
Claim 5, Kwon/Ishii discloses the method (Kwon, electronic package 30, [0067], Fig. 3; Ishii, resin-sealed semiconductor device 100, [0026], Fig. 1) of claim 4.
Kwon/Ishii discloses wherein the alloy has a solidus temperature of at least 240 degrees Celsius (Ishii, alloy of the high-melting-point solder-bonding material has a solidus temperature of 240 degrees Celsius, [0050], Fig. 1; Kwon, Fig. 3).
Claim 13, Kwon discloses the method (electronic package 30, [0067], Fig. 3) of claim 12.
Kwon discloses wherein the intermediate solder portions 451/452 are formed of an alloy comprising tin and silver (intermediate solder portions 451/452 are formed of an alloy comprising tin and silver, [0047], Figs. 2B and 3).
Kwon does not explicitly disclose wherein the intermediate solder portions are formed of an alloy comprising tin, silver, and copper.
However, Ishii discloses wherein the intermediate solder portions (Ishii, module bonding material 10 is a low-melting-point solder-bonding material and is equivalent to the intermediate solder portions, hereinafter, intermediate solder portions 10, [0056], Fig. 1; Kwon, Figs. 1A/1B, 2A/2B, and 3) are formed of an alloy comprising tin, silver and copper (Ishii, intermediate solder portions 10 are formed of an alloy comprising tin, silver and copper, [0056], Fig. 1; Kwon, intermediate solder portions 451/452 are formed of an alloy comprising tin and silver, [0047], Figs. 2B and 3). The combination to utilize an alloy containing tin, silver, and copper allows for the specific control of the solidus and liquidus temperatures of the intermediate solder portions as compared to the solidus and liquidus temperatures of the through-mold connections that are formed of an alloy including different materials to ensure melting of only the lower melting point material during subsequent reflow processing (Ishii, [0050]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an alloy containing tin, silver, and copper allows for the specific control of the solidus and liquidus temperatures of the intermediate solder portions as compared to the solidus and liquidus temperatures of the through-mold connections that are formed of an alloy including different materials to ensure melting of only the lower melting point material during subsequent reflow processing (Ishii, [0050]).
Claim 15, Kwon discloses a method for manufacturing an electronic package (semiconductor package 30 is an electronic package, hereinafter, electronic package 30, [0067], Fig. 3), the method comprising:
providing a substrate (lower substrate 100 is a substrate, hereinafter, substrate 100, [0040], Figs. 1A and 1B) having a first side (upper surface 100u of substrate 100, [0046], Figs. 1A and 1B) and a second side (second side of substrate 100 is the bottom surface, opposite to the upper surface 100u of substrate 100, [0046], Figs. 1A and 1B);
arranging a group of through-mold connections (connection structure 400’ is a group of through-mold connections, hereinafter, group of through-mold connections 400’, [0062], Figs. 1A/1B, 2A/2B, and 3) that are electrically conductive on the first side 100u of the substrate 100 (group of through-mold connections 400’ are electrically conductive on the first side 100u of the substrate 100, [0046], Figs. 1A and 1B), the arranging including directly fusing each of the group of through-mold connections 400’ to a corresponding electrically conductive node (substrate pad 110 is a corresponding electrically conductive node, hereinafter, corresponding electrically conductive node 110, [0040], Figs. 1A/1B, 2A/2B, and 3) provided on or embedded in the substrate 100 (corresponding electrically conductive node 110 is embedded in the substrate 100, [0040], Figs. 2B and 3);
mounting a first electronic module (semiconductor chips 210 is a first electronic module, hereinafter, first electronic module 210, [0040, Figs. 1A/2A and 3) to the first side 100u of the substrate 100 (first electronic module 210 is mounted to the first side 100u of the substrate 100, [0040, Figs. 1A/2A and 3);
applying a first mold structure (lower molding film 500 is a first mold structure, hereinafter, first mold structure 500, [0059], Fig. 3) to the first side 100u of the substrate 100 such that the first mold structure 500 extends over at least part of the first side 100u of the substrate 100 to substantially encapsulate the group of through-mold connections 400’ (first mold structure 500 extends over at least part of the first side of the substrate 100u to substantially encapsulate the group of through-mold connections 400’, [0059], Fig. 3); and
removing a portion of the first mold structure 500 to expose the group of through-mold connections 400’ (to expose the group of through-mold connections 400 a portion of the first mold structure 500 was removed, [0059], Fig. 3), the group of through-mold connections 400’ are configured to be coupled to a circuit board (the group of through-mold connections 400’ is configured coupled to a lower substrate 100, wherein the lower substrate 100 may be a circuit board, hereinafter, circuit board 100, [0068], Fig. 3) by a corresponding group of intermediate solder portions (lower solder connection portion 451 and upper solder connection portion 452 are corresponding group of intermediate solder portions, hereinafter, corresponding group of intermediate solder portions 451/452, [0064], Figs. 1A/1B, 2A/2B, and 3), the through-mold connections 400’ formed of an alloy including tin (through-mold connections 400’ is formed of an alloy including tin, [0047], Fig. 3).
Kwon does not explicitly disclose the through-mold connections formed of an alloy including tin and antimony, the alloy having a solidus temperature greater than a liquidus temperature of the intermediate solder portions.
However, Ishii discloses the through-mold connections formed of an alloy including tin and antimony (Ishii, high-melting-point solder-bonding material includes tin which contains antimony, [0056], Fig. 1; Kwon, through-mold connections 400’, [0064], Fig. 3). The alloy having a solidus temperature greater than a liquidus temperature of the intermediate solder portions (Ishii, the high-melting-point solder-bonding is an alloy including tin and antimony and the material alloy having a solidus temperature greater than a liquidus temperature of the low-melting-point solder-bonding material which are equivalent to the intermediate solder portions, [0055, Fig. 1; Kwon, [0064], Figs. 1A/1B, 2A/2B, and 3). The combination to utilize an alloy of tin and antimony would specifically manipulate the melting point of the solder material as compared to the materials used to form the through-mold connections to ensure melting of only the lower melting point material during subsequent reflow processing (Ishii, [0050]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an alloy of tin and antimony would specifically manipulate the melting point of the solder material as compared to the materials used to form the through-mold connections to ensure melting of only the lower melting point material during subsequent reflow processing (Ishii, [0050]).
Claim 18, Kwon discloses the method (electronic package 30, [0067], Fig. 3) of claim 16.
Kwon does not explicitly disclose wherein the through-mold connections are formed of an alloy including tin and antimony.
However, Ishii discloses the through-mold connections formed of an alloy including tin and antimony (Ishii, high-melting-point solder-bonding material includes tin which contains antimony, [0056], Fig. 1; Kwon, through-mold connections 400, [0064], Fig. 3). The combination to utilize an alloy of tin and antimony would specifically manipulate the melting point of the solder material as compared to the materials used to form the through-mold connections to ensure melting of only the lower melting point material during subsequent reflow processing (Ishii, [0050]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an alloy of tin and antimony would specifically manipulate the melting point of the solder material as compared to the materials used to form the through-mold connections to ensure melting of only the lower melting point material during subsequent reflow processing (Ishii, [0050]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yoo (US 2020/0118992 A1) discloses a semiconductor package further including first solder balls 140 as intermediate solder connections that are protruding above the first molding layer 116, [0024], Fig. 2.
Chen (US 2018/0096949 A1) discloses a semiconductor package further including solder ball 106 in combination with additional conductive material 118 function as intermediate solder connections, hereinafter, intermediate solder connections 106/118 that are protruding above the overmold 105, [0159], Figs. 13B and 18C.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812