DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-3, 7-8, 12, and 15-16 are amended. Claims 6-8 are withdrawn. Claims 9, 11, 14, and 20 are cancelled. Claims 1-5, 10, 12-13, 15-19 and 21 are present for examination.
Information Disclosure Statement
The information disclosure statements (IDS) filed on June 11, 2026 is being considered by the examiner.
Response to Arguments
Applicant’s arguments, see pages 7-8, filed June 11, 2026, with respect to the title objection have been fully considered and are persuasive. The title objection of March 11, 2026 has been withdrawn.
Applicant’s arguments, see page 8, filed June 11, 2026, with respect to the 35 U.S.C. 112 rejections have been fully considered and are persuasive. The 35 U.S.C. 112 rejections of March 11, 2026 have been withdrawn.
Applicant’s arguments, see pages 9-13, filed June 11, 2026, with respect to the rejection(s) of claim(s) 1-2, 9-12, 14, 16-17, and 19-20 under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Ishii (US 2023/0223317 A1).
Applicant’s arguments, see pages 9-13, filed June 11, 2026, with respect to the rejection(s) of claim(s) 3-5, 13, 15, and 18 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Ishii (US 2023/0223317 A1).
In the interest of compact prosecution, the Examiner suggests the Applicant more clearly define the (i) steps involved in the reflow soldering operation and/or the (ii) timescales and temperatures involved in each step of the reflow soldering operation (e.g. (i) wherein the reflow soldering operation comprises a preheating phase, soaking phase, reflow phase, and cooling phase; (ii) wherein the preheating phase preheats the temperature from ambient temperature to a soak temperature, the soaking phase holds a temperature steady or allows the temperature to deviate slightly, the reflow phase increases the temperature above the liquidus temperature of the solder material of the intermediate solder portions and the cooling phase reduces the temperature to ambient temperature – Instant Application, [0120], Fig. 8). The Examiner is available at the number below for an interview to discuss ideas at the Applicant’s convenience.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 10, 12-13, 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon (US 2019/0355667 A1) in view of Ishii (US 2023/0223317 A1).
Claim 1, Kwon discloses a method for manufacturing an electronic package (semiconductor package 30 is an electronic package, hereinafter, electronic package 30, [0067], Fig. 3), the method comprising:
providing a substrate (lower substrate 100 is a substrate, hereinafter, substrate 100, [0040], Figs. 1A and 1B) having a first side (upper surface 100u of substrate 100 within a first region R1, hereinafter, first side 100u of substrate 100, [0046], Figs. 1A and 1B) and a second side (upper surface of insulating layer 610 is opposite to upper surface 100u of substrate 100, hereinafter, second side 610u, [0046], Figs. 1A and 1B);
arranging a group of through-mold connections (connection structure 400’ is a group of through-mold connections, hereinafter, group of through-mold connections 400’, [0062], Figs. 1A/1B, 2A/2B, and 3) that are electrically conductive on the first side 100u of the substrate 100 (group of through-mold connections 400’ are electrically conductive on the first side 100u of the substrate 100, [0046], Figs. 1A and 1B), the group of through-mold connections 400’ configured to be coupled to a circuit board (the group of through-mold connections 400’ is configured coupled to a lower substrate 100, wherein the lower substrate 100 may be a circuit board, hereinafter, circuit board 100 or substrate 100, [0068], Fig. 3) by a corresponding group of intermediate solder portions (lower solder connection portion 451 and upper solder connection portion 452 are corresponding group of intermediate solder portions, hereinafter, corresponding group of intermediate solder portions 451/452, [0064], Figs. 1A/1B, 2A/2B, and 3), the through-mold connections 400’ having a melting point in excess of a melting point of the intermediate solder portions 451/452 (through-mold connections 400’ have a higher melting point than the melting point of the intermediate solder portions 451/452, [0064], Figs. 1A/1B, 2A/2B, and 3);
mounting a first electronic module (semiconductor chips 210 is a first electronic module, hereinafter, first electronic module 210, [0040, Figs. 1A/2A and 3) to the first side 100u of the substrate 100 (first electronic module 210 is mounted to the first side 100u of the substrate 100, [0040, Figs. 1A/2A and 3);
applying a first mold structure (lower molding film 500 is a first mold structure, hereinafter, first mold structure 500, [0059], Fig. 3) to the first side of the substrate 100u such that the first mold structure 500 extends over at least part of the first side 100u of the substrate 100 to encapsulate the group of through-mold connections 400’ (first mold structure 500 extends over at least part of the first side of the substrate 100u to encapsulate the group of through-mold connections 400’, [0059], Fig. 3); and
removing a portion of the first mold structure 500 to expose the group of through-mold connections 400 (to expose the group of through-mold connections 400 a portion of the first mold structure 500 was removed, [0059], Fig. 3).
Kwon does not explicitly disclose applying a first mold structure to the first side of the substrate such that the first mold structure extends over at least part of the first side of the substrate to encapsulate the group of through-mold connections and at least part of the first electronic module;
removing a portion of the first mold structure to expose the group of through-mold connections, so as to provide an exposed face of each of the through-mold connections that is flush with an outer surface of the first mold structure; and
coupling the intermediate solder portions to the exposed faces of the through-mold connections, the intermediate solder portions protruding from the outer surface of the first mold structure away from the through-mold connections.
However, Ishii discloses applying a first mold structure (Ishii, moulding resin 9 is a first mold structure, hereinafter, first mold structure 9, [0026], Fig. 4; Kwon, lower molding film 500 is a first mold structure, hereinafter, first mold structure 500, [0059], Fig. 3) to the first side of the substrate (Ishii, semiconductor element 1/2 both contain active semiconductor regions that are disposed on a substrate, hereinafter, semiconductor element substrate 1S/2S, wherein both semiconductor elements 1/2¸ [0027], Fig. 4; Kwon, Fig. 3) such that the first mold structure extends over at least part of the first side of the substrate to encapsulate the group of through-mold connections (Ishii, first mold structure 9 extends over at least part of the first side of the substrate 1S/2S to encapsulate the on-the-chip bonding materials 41/42, heat spreader 3, resin insulating layer 7, and copper plate 8 are a group of through-mold connections, hereinafter, group of through-mold connections 7/8, [0026], Fig. 4; Kwon, first mold structure 500 extends over at least part of the first side of the substrate 100u to substantially encapsulate the group of through-mold connections 400’, [0059], Fig. 3) and at least part of the first electronic module (Ishii, first mold structure 9 extends over at least part of the first electronic module 101, [0026], Fig. 4; Kwon, Fig. 3);
removing a portion of the first mold structure to expose the group of through-mold connections, so as to provide an exposed face of each of the through-mold connections that is flush with an outer surface of the first mold structure (Ishii, a portion of the first mold structure 9 exposes the group of through-mold connections 7/8 so as to provide an exposed face of each of the through-mold connections 7/8 that is flush with an outer surface of the first mold structure 9, [0028], Fig. 4; Kwon, to expose the group of through-mold connections 400 a portion of the first mold structure 500 was removed, [0059], Fig. 3); and
coupling the intermediate solder portions to the exposed faces of the through-mold connections, the intermediate solder portions protruding from the outer surface of the first mold structure away from the through-mold connections (Ishii, coupling the module bonding material 10 which is an intermediate solder portion, hereinafter, intermediate solder portion 10 to the exposed faces of the through-mold connections 7/8, the intermediate solder portions 10 protruding from the outer surface of the first mold structure 9 away from the through-mold connections 7/8, [0028], Fig. 4 ; Kwon, through-mold connections 400’ and intermediate solder portions 451/452, [0062] and [0064], Figs. 1A/1B, 2A/2B, and 3). The combination to utilize a flush surface between the through-mold connections and first mold structure ensures that coupling the intermediate solder portions protrude from the outer surface of the first mold structure away from the through-mold connections ensures thermal resistance between bonded layers can be suppressed from increasing; therefore, a module having a high heat-radiation performance can be obtained (Ishii, [0053]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a flush surface between the through-mold connections and first mold structure to ensure that coupling the intermediate solder portions protrude from the outer surface of the first mold structure away from the through-mold connections ensures thermal resistance between bonded layers can be suppressed from increasing; therefore, a module having a high heat-radiation performance can be obtained (Ishii, [0053]).
Claim 2, Kwon/Ishii discloses the method (Kwon, electronic package 30, [0067], Fig. 3; Ishii, Fig. 4) of claim 1.
Kwon/Ishii discloses in which an outer surface of the first mold structure is free of any moat or channel circumscribing and adjacent to each of the through-mold connections during the method (Kwon, an outer surface of the first mold structure 500 is free of any moat or channel circumscribing and adjacent to each of the through-mold connections 400 during the method, Fig. 3; Ishii, Fig. 4).
Claim 3, Kwon discloses the method (electronic package 30, [0067], Fig. 3) of claim 1.
Kwon does not explicitly disclose wherein the melting point of the through-mold connections exceed the melting point of the intermediate solder portions by at least 10 degrees Celsius.
However, Ishii discloses wherein the melting point of the through-mold connections (Ishii, the high-melting-point solder-bonding is the material used to form the through-mold connections, [0056], Fig. 1; Kwon, Fig. 3) exceed the melting point of the intermediate solder portions (Ishii, the low-melting-point solder-bonding is the material used to form the intermediate solder portions, [0056], Fig. 1; Kwon, Fig. 3) by at least 10 degrees Celsius (Ishii, the melting point of the high-melting-point solder-bonding material is at least 10 degrees Celsius (i.e. 30 degrees Celsius) higher than the low-melting-point solder-bonding material, [0056], Fig. 1; Kwon, Fig. 3). The combination to utilize an alloy of tin and antimony would specifically manipulate the melting point of the solder material as compared to the materials used to form the through-mold connections to ensure melting of only the lower melting point material during subsequent reflow processing (Ishii, [0050]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an alloy of tin and antimony would specifically manipulate the melting point of the solder material as compared to the materials used to form the through-mold connections to ensure melting of only the lower melting point material during subsequent reflow processing (Ishii, [0050]).
Claim 4, Kwon discloses the method (electronic package 30, [0067], Fig. 3) of claim 1.
Kwon does not explicitly disclose wherein the through-mold connections are formed of an alloy including tin and antimony.
However, Ishii discloses the through-mold connections formed of an alloy including tin and antimony (Ishii, high-melting-point solder-bonding material includes tin which contains antimony, [0056], Fig. 1; Kwon, through-mold connections 400, [0064], Fig. 3). The combination to utilize an alloy of tin and antimony would specifically manipulate the melting point of the solder material as compared to the materials used to form the through-mold connections to ensure melting of only the lower melting point material during subsequent reflow processing (Ishii, [0050]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an alloy of tin and antimony would specifically manipulate the melting point of the solder material as compared to the materials used to form the through-mold connections to ensure melting of only the lower melting point material during subsequent reflow processing (Ishii, [0050]).
Claim 5, Kwon/Ishii discloses the method (Kwon, electronic package 30, [0067], Fig. 3; Ishii, resin-sealed semiconductor device 100, [0026], Fig. 1) of claim 4.
Kwon/Ishii discloses wherein the alloy has a solidus temperature of at least 240 degrees Celsius (Ishii, alloy of the high-melting-point solder-bonding material has a solidus temperature of 240 degrees Celsius, [0050], Fig. 1; Kwon, Fig. 3).
Claim 10, Kwon/Ishii discloses the method (Kwon, electronic package 30, [0067], Fig. 3; Ishii, Fig. 4) of claim 1.
Kwon/Ishii discloses further comprising:
mounting a second electronic component (Kwon, third semiconductor chip 720 is a second electronic component, hereinafter, second electronic component 720, [0068], Fig. 3; Ishii, Fig. 4) to the second side of the substrate (Kwon, second electronic component 720 is mounted to the second side 610u of the substrate 100, [0068], Fig. 3; Ishii, Fig. 4), and
applying a second mold structure (Kwon, upper molding film 730 is a second mold structure, hereinafter, second mold structure 730, [0068], Fig. 3; Ishii, Fig. 4) to the second side of the substrate such that the second mold structure extends over at least part of the second side of the substrate (Kwon, second mold structure 730 extends over at least part of the second side 610u of the substrate 100, [0068], Fig. 3; Ishii, Fig. 4).
Claim 12, Kwon/Ishii discloses the method (Kwon, electronic package 30, [0067], Fig. 3; Ishii, Fig. 4) of claim 1.
Kwon/Ishii discloses further comprising:
providing the corresponding group of intermediate solder portions (Kwon, providing the corresponding group of intermediate solder portions 451/452, [0067], Fig. 3; Ishii, Fig. 4); and
fusing each intermediate solder portion directly to an end face of a corresponding one of the group of through-mold connections (Kwon, each intermediate solder portion 451/452 is directly fused to an end face of a corresponding one of the group of through-mold connections 400’, [0047], Figs. 2B and 3; Ishii, Fig. 4).
Claim 13, Kwon discloses the method (electronic package 30, [0067], Fig. 3) of claim 12.
Kwon discloses wherein the intermediate solder portions 451/452 are formed of an alloy comprising tin and silver (intermediate solder portions 451/452 are formed of an alloy comprising tin and silver, [0047], Figs. 2B and 3).
Kwon does not explicitly disclose wherein the intermediate solder portions are formed of an alloy comprising tin, silver, and copper.
However, Ishii discloses wherein the intermediate solder portions (Ishii, module bonding material 10 is a low-melting-point solder-bonding material and is equivalent to the intermediate solder portions, hereinafter, intermediate solder portions 10, [0056], Fig. 1; Kwon, Figs. 1A/1B, 2A/2B, and 3) are formed of an alloy comprising tin, silver and copper (Ishii, intermediate solder portions 10 are formed of an alloy comprising tin, silver and copper, [0056], Fig. 1; Kwon, intermediate solder portions 451/452 are formed of an alloy comprising tin and silver, [0047], Figs. 2B and 3). The combination to utilize an alloy containing tin, silver, and copper allows for the specific control of the solidus and liquidus temperatures of the intermediate solder portions as compared to the solidus and liquidus temperatures of the through-mold connections that are formed of an alloy including different materials to ensure melting of only the lower melting point material during subsequent reflow processing (Ishii, [0050]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an alloy containing tin, silver, and copper allows for the specific control of the solidus and liquidus temperatures of the intermediate solder portions as compared to the solidus and liquidus temperatures of the through-mold connections that are formed of an alloy including different materials to ensure melting of only the lower melting point material during subsequent reflow processing (Ishii, [0050]).
Claim 15, Kwon discloses a method for manufacturing an electronic package (semiconductor package 30 is an electronic package, hereinafter, electronic package 30, [0067], Fig. 3), the method comprising:
providing a substrate (lower substrate 100 is a substrate, hereinafter, substrate 100, [0040], Figs. 1A and 1B) having a first side (upper surface 100u of substrate 100, [0046], Figs. 1A and 1B) and a second side (second side of substrate 100 is the bottom surface, opposite to the upper surface 100u of substrate 100, [0046], Figs. 1A and 1B);
arranging a group of through-mold connections (connection structure 400’ is a group of through-mold connections, hereinafter, group of through-mold connections 400’, [0062], Figs. 1A/1B, 2A/2B, and 3) that are electrically conductive on the first side 100u of the substrate 100 (group of through-mold connections 400’ are electrically conductive on the first side 100u of the substrate 100, [0046], Figs. 1A and 1B), the arranging including directly fusing each of the group of through-mold connections 400’ to a corresponding electrically conductive node (substrate pad 110 is a corresponding electrically conductive node, hereinafter, corresponding electrically conductive node 110, [0040], Figs. 1A/1B, 2A/2B, and 3) provided on or embedded in the substrate 100 (corresponding electrically conductive node 110 is embedded in the substrate 100, [0040], Figs. 2B and 3);
mounting a first electronic module (semiconductor chips 210 is a first electronic module, hereinafter, first electronic module 210, [0040, Figs. 1A/2A and 3) to the first side 100u of the substrate 100 (first electronic module 210 is mounted to the first side 100u of the substrate 100, [0040, Figs. 1A/2A and 3);
applying a first mold structure (lower molding film 500 is a first mold structure, hereinafter, first mold structure 500, [0059], Fig. 3) to the first side 100u of the substrate 100 such that the first mold structure 500 extends over at least part of the first side 100u of the substrate 100 to 400’ (first mold structure 500 extends over at least part of the first side of the substrate 100u to substantially encapsulate the group of through-mold connections 400’, [0059], Fig. 3); and
removing a portion of the first mold structure 500 to expose the group of through-mold connections 400’ (to expose the group of through-mold connections 400 a portion of the first mold structure 500 was removed, [0059], Fig. 3), the group of through-mold connections 400’ are configured to be coupled to a circuit board (the group of through-mold connections 400’ is configured coupled to a lower substrate 100, wherein the lower substrate 100 may be a circuit board, hereinafter, circuit board 100, [0068], Fig. 3) by a corresponding group of intermediate solder portions (lower solder connection portion 451 and upper solder connection portion 452 are corresponding group of intermediate solder portions, hereinafter, corresponding group of intermediate solder portions 451/452, [0064], Figs. 1A/1B, 2A/2B, and 3), the through-mold connections 400’ formed of an alloy including tin (through-mold connections 400’ is formed of an alloy including tin, [0047], Fig. 3).
Kwon does not explicitly disclose applying a first mold structure to the first side of the substrate such that the first mold structure extends over at least part of the first side of the substrate to encapsulate the group of through-mold connections and at least part of the first electronic module;
removing a portion of the first mold structure to expose the group of through-mold connections, such that an exposed face of each of the through-mold connections that is flush with an outer surface of the first mold structure.
However, Ishii discloses applying a first mold structure (Ishii, moulding resin 9 is a first mold structure, hereinafter, first mold structure 9, [0026], Fig. 4; Kwon, lower molding film 500 is a first mold structure, hereinafter, first mold structure 500, [0059], Fig. 3) to the first side of the substrate (Ishii, semiconductor element 1/2 both contain active semiconductor regions that are disposed on a substrate, hereinafter, semiconductor element substrate 1S/2S, wherein both semiconductor elements 1/2¸ [0027], Fig. 4; Kwon, Fig. 3) such that the first mold structure extends over at least part of the first side of the substrate to encapsulate the group of through-mold connections (Ishii, first mold structure 9 extends over at least part of the first side of the substrate 1S/2S to encapsulate the on-the-chip bonding materials 41/42, heat spreader 3, resin insulating layer 7, and copper plate 8 are a group of through-mold connections, hereinafter, group of through-mold connections 7/8, [0026], Fig. 4; Kwon, first mold structure 500 extends over at least part of the first side of the substrate 100u to substantially encapsulate the group of through-mold connections 400’, [0059], Fig. 3) and at least part of the first electronic module (Ishii, first mold structure 9 extends over at least part of the first electronic module 101, [0026], Fig. 4; Kwon, Fig. 3);
removing a portion of the first mold structure to expose the group of through-mold connections, such that an exposed face of each of the through-mold connections that is flush with an outer surface of the first mold structure (Ishii, a portion of the first mold structure 9 exposes the group of through-mold connections 7/8 so as to provide an exposed face of each of the through-mold connections 7/8 that is flush with an outer surface of the first mold structure 9, [0028], Fig. 4; Kwon, to expose the group of through-mold connections 400 a portion of the first mold structure 500 was removed, [0059], Fig. 3). The combination to utilize a flush surface between the through-mold connections and first mold structure ensures thermal resistance between bonded layers can be suppressed from increasing; therefore, a module having a high heat-radiation performance can be obtained (Ishii, [0053]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a flush surface between the through-mold connections and first mold structure to ensure thermal resistance between bonded layers can be suppressed from increasing; therefore, a module having a high heat-radiation performance can be obtained (Ishii, [0053]).
Kwon does not explicitly disclose the through-mold connections formed of an alloy including tin and antimony, the alloy having a solidus temperature greater than a liquidus temperature of the intermediate solder portions.
However, Ishii discloses the through-mold connections formed of an alloy including tin and antimony (Ishii, high-melting-point solder-bonding material includes tin which contains antimony, [0056], Fig. 1; Kwon, through-mold connections 400’, [0064], Fig. 3). The alloy having a solidus temperature greater than a liquidus temperature of the intermediate solder portions (Ishii, the high-melting-point solder-bonding is an alloy including tin and antimony and the material alloy having a solidus temperature greater than a liquidus temperature of the low-melting-point solder-bonding material which are equivalent to the intermediate solder portions, [0055, Fig. 1; Kwon, [0064], Figs. 1A/1B, 2A/2B, and 3). The combination to utilize an alloy of tin and antimony would specifically manipulate the melting point of the solder material as compared to the materials used to form the through-mold connections to ensure melting of only the lower melting point material during subsequent reflow processing (Ishii, [0050]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an alloy of tin and antimony would specifically manipulate the melting point of the solder material as compared to the materials used to form the through-mold connections to ensure melting of only the lower melting point material during subsequent reflow processing (Ishii, [0050]).
Claim 16, Kwon discloses a method of manufacturing an electronic assembly (semiconductor package 30 is an electronic package, hereinafter, electronic package 30, [0067], Fig. 3), the method comprising:
encapsulating an electronic module (semiconductor chips 210 is an electronic module, hereinafter, electronic module 210, [0040, Figs. 1A/2A and 3) and electrically conductive through-mold connections (connection structure 400’ is a group of electrically conductive through-mold connections, hereinafter, electrically conductive through-mold connections 400’, [0046] and [0062], Figs. 1A/1B, 2A/2B, and 3) with a mold structure (lower molding film 500 is a mold structure, hereinafter, mold structure 500 encapsulating an electronic module 210 and electrically conductive through-mold connections 400’, [0059], Fig. 3), the electronic module 210 and the electrically conductive through-mold connections 400’ being positioned on a first side of a substrate (upper surface 100u of substrate 100, [0046], Figs. 1A and 1B);
removing a portion of the mold structure 500 to expose the electrically conductive through-mold connections 400’ (to expose the group of through-mold connections 400’ a portion of the first mold structure 500 was removed, [0059], Fig. 3); and
electrically connecting the electrically conductive through-mold connections 400 to a circuit board (the group of through-mold connections 400 is configured coupled to a lower substrate 100, wherein the lower substrate 100 may be a circuit board, hereinafter, circuit board 100 or substrate 100, [0068], Fig. 3) using solder connections (lower solder connection portion 451, upper solder connection portion 452 and conductive terminal 750 electrically connects the electrically conductive through-mold connections 400 to a circuit board 100 and is formed of a solder material, [0064] and [0069], Fig. 3), the electrically conductive through-mold connections 400 having a melting point that is higher than a melting point the solder connections 451/452/750 (through-mold connections 400 have a higher melting point than the melting point of the intermediate solder portions 451/452, [0064], Figs. 1A/1B, 2A/2B, and 3).
Kwon does not explicitly disclose removing a portion of the mold structure to expose the electrically conductive through-mold connections such that an exposed face of each of the through-mold connections is flush with an outer surface of the first mold structure.
However, Ishii discloses removing a portion of the mold structure to expose the electrically conductive through-mold connections (Ishii, a portion of the first mold structure 9 exposes the group of through-mold connections 7/8 so as to provide an exposed face of each of the through-mold connections 7/8 that is flush with an outer surface of the first mold structure 9, [0028], Fig. 4; Kwon, to expose the group of through-mold connections 400 a portion of the first mold structure 500 was removed, [0059], Fig. 3) such that an exposed face of each of the through-mold connections is flush with an outer surface of the first mold structure (Ishii, exposed face of each through-mold connection 7/8 is flush with an outer surface of the first mold structure 9, [0028, Fig. 4; Kwon, through-mold connections 400’ and intermediate solder portions 451/452, [0062] and [0064], Figs. 1A/1B, 2A/2B, and 3). The combination to utilize an exposed face of the through-mold connections are flush with an outer surface of the first mold structure ensures thermal resistance between bonded layers can be suppressed from increasing; therefore, a module having a high heat-radiation performance can be obtained (Ishii, [0053]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an exposed face of the through-mold connections are flush with an outer surface of the first mold structure to ensure thermal resistance between bonded layers can be suppressed from increasing; therefore, a module having a high heat-radiation performance can be obtained (Ishii, [0053]).
Claim 17, Kwon/Ishii discloses the method (Kwon, electronic package 30, [0067], Fig. 3; Ishii, Fig. 4) of claim 16.
Kwon/Ishii discloses wherein an outer surface of the first mold structure is free of any moat or channel circumscribing and adjacent to each of the through-mold connections after performing the method (Kwon, an outer surface of the first mold structure 500 is free of any moat or channel circumscribing and adjacent to each of the through-mold connections 400 after performing the method, Fig. 3; Ishii, Fig. 4).
Claim 18, Kwon discloses the method (electronic package 30, [0067], Fig. 3) of claim 16.
Kwon does not explicitly disclose wherein the through-mold connections are formed of an alloy including tin and antimony.
However, Ishii discloses the through-mold connections formed of an alloy including tin and antimony (Ishii, high-melting-point solder-bonding material includes tin which contains antimony, [0056], Fig. 1; Kwon, through-mold connections 400, [0064], Fig. 3). The combination to utilize an alloy of tin and antimony would specifically manipulate the melting point of the solder material as compared to the materials used to form the through-mold connections to ensure melting of only the lower melting point material during subsequent reflow processing (Ishii, [0050]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an alloy of tin and antimony would specifically manipulate the melting point of the solder material as compared to the materials used to form the through-mold connections to ensure melting of only the lower melting point material during subsequent reflow processing (Ishii, [0050]).
Claim 19, Kwon/Ishii discloses the method (Kwon, electronic package 30, [0067], Fig. 3; Ishii, Fig. 4) of claim 16.
Kwon/Ishii discloses wherein the electrically connecting includes reflowing the solder connections without melting the electrically conductive through-mold connections (Kwon, solder connection 750 is formed by a reflow process, leaving the electrically conductive through-mold connections 400 with a higher melting point un-melted, [0069], Fig. 3; Ishii, Fig. 4).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Ishii, and further in view of Kim (US 2018/0061816 A1).
Claim 21, Kwon discloses the method (Kwon, electronic package 30, [0067], Fig. 3; Ishii, resin-sealed semiconductor device 100, [0032], Fig. 4) of claim 1.
Kwon/Ishii does not explicitly disclose wherein the first electronic module is a flip chip, and the removing the portion of the first mold structure exposes a surface of the flip chip such that the surface of the flip chip is flush with the outer surface of the first mold structure.
However, Kim discloses wherein the first electronic module is a flip chip (Kim, first electronic module 103 is a flip chip, [0022], Fig. 2; Kwon, electronic package 30, [0067], Fig. 3; Ishii, resin-sealed semiconductor device 100, [0032], Fig. 4), and the removing the portion of the first mold structure exposes a surface of the flip chip such that the surface of the flip chip is flush with the outer surface of the first mold structure (Kim, removing the portion of the first mold structure 105 exposes a surface of the flip chip 103 such that the surface of the flip chip 103 is flush with the outer surface of the first mold structure 105, [0022], Fig. 2; Kwon, electronic package 30, [0067], Fig. 3; Ishii, resin-sealed semiconductor device 100, [0032], Fig. 4). The combination to utilize a flip chip for the first electronic module allows for the flip chip to be flush with the outer surface of the first mold structure to achieve a high density package on package chip stack (Kim, [0004]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a flip chip for the first electronic module to allow for the flip chip to be flush with the outer surface of the first mold structure to achieve a high density package on package chip stack (Kim, [0004]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yoo (US 2020/0118992 A1) discloses a semiconductor package further including first solder balls 140 as intermediate solder connections that are protruding above the first molding layer 116, [0024], Fig. 2.
Chen (US 2018/0096949 A1) discloses a semiconductor package further including solder ball 106 in combination with additional conductive material 118 function as intermediate solder connections, hereinafter, intermediate solder connections 106/118 that are protruding above the overmold 105, [0159], Figs. 13B and 18C.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEVY J BOEGEL whose telephone number is (703)756-1299. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights