DETAILED ACTION
This Office Action is in response to the Applicant Election filed on 02/24/2026.
Currently, claims 1-18 and 21-22 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 02/24/2026 is acknowledged. Claims 1-18 and 21-22 are examined in this Office action.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/09/2024, 04/01/2025, and 02/11/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitations “the first and third via structures” and “the fourth via structure”. There is insufficient antecedent basis for the third and fourth via structures in this claim. Therefore, the claim has an indefinite scope. For the purpose of examination, these limitation will be read as: “the first via structure and a third via structure” and “a fourth via structure”.
Claim 10 is also rejected under 112(b) as it depends on base claim 9.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 21, and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHEN et al. (US Pub. No. 2019/0378809).
Regarding independent claim 1, Chen teaches a method for fabricating semiconductor packages (Figs. 1-11), comprising:
forming a redistribution structure (Fig. 11, 70, ¶ [0032]) comprising a plurality of conductive layers (Fig. 11, RDL1 + RDL2 + RDL3 + 52A + Via-0, ¶¶ [0030]-[0031]) and a plurality of via structures (Fig. 11, Via-1 + Via-2 + Via-3 + Via-4, ¶ [0030], ¶¶ [0039]-[0042]), adjacent ones of the plurality of conductive layers being connected through at least a corresponding one of the plurality of via structures (Fig. 11, ¶ [0030]);
wherein forming the redistribution structure further comprises laterally rotating (see Figs. 11 & 12B, leftmost Via-3 is not laterally aligned with leftmost Via-2 and the leftmost Via-3 is instead laterally rotated around the relative position of the leftmost Via-2) a first via structure (Fig. 11, Leftmost Via-3 of via group VG-3, ¶ [0036]) among the plurality of via structures around a second via structure (Fig. 11, Leftmost via of Via-2 group VG-2, ¶ [0036]) among the plurality of via structures, the first via structure being above the second via structure (Fig. 11).
Regarding independent claim 21, Cheng teaches a method for fabricating semiconductor packages (Figs. 1-12B), comprising:
identifying, for a plurality of first vias (Fig. 11, VG-3, ¶ [0036]) on a first layer (Fig. 11, RDL2, ¶ [0036]) of a semiconductor device, first locations (Fig. 11, locations corresponding to vias Via-3 of VG-3, ¶ [0036]) according to a first predefined pattern (Fig. 12A, pattern of VG-3, ¶ [0039]);
identifying, for a plurality of second vias (Fig. 11, VG-1, ¶ [0036]) on a second layer (Fig. 11, RDL-1, ¶ [0036]) of the semiconductor device, second locations (Fig. 11, locations corresponding to vias Via-1 of VG-1, ¶ [0036]) according to a second predefined pattern (Fig. 12C, pattern of VG-1, ¶ [0041]);
identifying a third location (Fig. 11, location corresponding to top leftmost Via-2 of via group VG-2, ¶ [0036]) for a third via (Fig. 11, bottom leftmost Via-2) on a third layer (Fig. 11, RDL-2, ¶ [0036]) of the semiconductor device, the third layer disposed vertically between the first layer and the second layer (Fig. 11); and
laterally rotating (Figs. 11 & 12B, bottom leftmost Via-2 is laterally rotated relative to the positions of vias Via-3) the third location about one of the first locations to identify a fourth location (Figs. 11 & 12B, location corresponding to bottom leftmost Via-2 of via group VG-2) for the third via, wherein the fourth location is based on a lateral distance from one or more of the first locations and one or more of the second locations (¶¶ [0039]-[0042] teaches that the locations of Chen’s Vias and Via groups have a lateral distance from each other so that they are vertically misaligned).
Regarding claim 22, Chen teaches the method of claim 21, and Chen teaches that the first predefined pattern (Fig. 12A, pattern of VG-3, ¶ [0039]) differs (Figs. 11-12C) from the second predefined pattern (Fig. 12C, pattern of VG-1, ¶ [0041]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 3, and 5-9 are rejected under 35 U.S.C. 103 as being obvious over CHEN et al. (US Pub. No. 2019/0378809) in view of JENG et al. (US Pub. No. 2022/0028825) and further in view of TANG et al. (US Pat. No. 12,095,463).
Regarding claim 2, Chen teaches the method of claim 1, and Chen teaches
laterally rotating the first via structure (Fig. 11, Leftmost via of Via-3 group VG-3, ¶ [0036]) away from a third via structure (Figs. 11 & 12B, bottom rightmost Via-3 of via group VG-3) among the plurality of via structures (Fig. 12B, the leftmost Via-3 is laterally rotated away from the bottom rightmost Via-3 at an angle from the view of Fig. 12B), the first and third via structures being laterally aligned with each other (Fig. 11, leftmost Via-3 and rightmost Via-3 are laterally aligned with each other in the view of Fig. 11);
providing a semiconductor chip (Fig. 6, 26A + 26B, ¶ [0024]) comprising a substrate (Fig. 1, 28A + 28B, ¶ [0024]) and a plurality of first connector structures (Fig. 6, 30B, ¶ [0024]);
bonding the plurality of first connector structures to the redistribution structure (Fig. 6, ¶ [0028]).
However, Chen does not explicitly teach bonding the redistribution structure to a carrier substrate through a plurality of second connector (the Examiner notes that Chen does teach bonding their interconnection structure to a tape 55 through electrical connectors 52 in order to secure the device for further processing, see Fig. 5 ¶ [0033]).
However, Jeng is a pertinent art that teaches that a carrier substrate can be used instead of a tape to affix a device during processing (see Fig. 17, 310, ¶ [0065]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s device to be affixed to a carrier substrate instead of a tape during processing according to the teaching of Jeng (Fig. 17) in order to simplify manufacturing (Jeng ¶ [0066] teaches that a carrier substrate can easily be removed using heat or exposure to UV light)
However, as is not pertinent to the particulars of their invention, Chen in view of Jeng does not explicitly teach a plurality of metallization layers and a plurality of first connector structures disposed on a topmost one of the plurality of metallization layers.
However, Chen does teach integrated circuit devices included in 26A and 26B (¶ [0024]). It is known in the art that integrated circuit devices typically include multiple metallization layers (as evidence, see Tang Col. 7 lines 40-45). Therefore, it would be obvious that Chen’s integrated circuit devices includes a plurality of metallization layers in order to transmit electrical signals.
Further, Chen ¶ [0024] teaches that Chen’s connectors 30A, which are on top of Chen’s package 26A, are connected to their integrated circuit devices. Therefore, It would be obvious that Chen’s connectors 30A would be electrically connected to a topmost one of Chen’s metallization within their integrated circuit device.
Regarding claim 3, Chen in view of Tang teaches the method of claim 2, and Chen teaches that forming the redistribution structure (Fig. 11, 70, ¶ [0032]) further comprises laterally rotating (see Fig. 11, leftmost Via-3 is not laterally aligned with Via-4 and the leftmost Via-3 is instead laterally rotated around the relative position of Via-4) first via structure (Fig. 11, Leftmost Via-3 of via group VG-3, ¶ [0036]) away from a fourth one (Fig. 11, Via-4, ¶ [0036]) of the plurality of via structures, the first and third via structures (Figs. 11 & 12B, bottom rightmost Via-3 of via group VG-3) vertically disposed (Fig. 11, leftmost and rightmost Via-3 is on a vertical level disposed between Via-4 and Via-2) between the second via structure (Fig. 11, Leftmost via of Via-2 group VG-2, ¶ [0036]) and the fourth via structure.
Regarding claim 5, Chen in view of Jeng in view of Tang teaches the method of claim 3, and Chen teaches that subsequent to forming the redistribution structure, the first via structure (Fig. 11, Leftmost Via-3 of via group VG-3, ¶ [0036]) is laterally spaced from any of the second (Fig. 11, Leftmost via of Via-2 group VG-2, ¶ [0036]), third structure (Figs. 11 & 12B, bottom rightmost Via-3 of via group VG-3), or fourth via (Fig. 11, Via-4, ¶ [0036]) structure with a spacing equal to or greater than a preconfigured threshold (Figs. 11 & 12B, leftmost Via-3 is spaced apart from the leftmost Via-2, the bottom rightmost Via-3, and Via-4 by at least the lateral distance between leftmost Via-3 and the leftmost Via-2).
Regarding claim 6, Chen in view of Jeng in view of Tang teaches the method of claim 2, and Chen teaches that the first (Fig. 11, Leftmost Via-3 of via group VG-3, ¶ [0036]) and third via structures (Figs. 11 & 12B, bottom rightmost Via-3 of via group VG-3) each connect a portion of a first conductive layer (Fig. 11, RDL2, ¶¶ [0030]-[0031]) among the plurality of conductive layers (Fig. 11, RDL1 + RDL2 + RDL3 + 52A + Via-0, ¶¶ [0030]-[0031]) to a portion of a second conductive layer (Fig. 11, RDL3, ¶¶ [0030]-[0031]) among the plurality of conductive layers, the second via structure (Fig. 11, Leftmost via of Via-2 group VG-2, ¶ [0036]) connects the portion of the first conductive layer to a portion of a third conductive layer (Fig. 11, RDL1, ¶¶ [0030]-[0031]) among the plurality of conductive layers, and the fourth via structure (Fig. 11, Via-4, ¶ [0036]) connects the portion of the second conductive layer to a portion of a fourth conductive layer (Fig. 11, 52A, ¶¶ [0030]-[0031]) among the plurality of conductive layers.
Regarding claim 7, Chen in view of Jeng in view of Tang teaches the method of claim 6, and Chen teaches that the redistribution structure (Fig. 11, 70, ¶ [0032]) further comprises a fifth conductive layer (Fig. 11, Via-0, ¶¶ [0030]-[0031]) among the plurality of conductive layers, in which the fifth conductive layer, the third conductive layer (Fig. 11, RDL1, ¶¶ [0030]-[0031]), the first conductive layer (Fig. 11, RDL2, ¶¶ [0030]-[0031]), the second conductive layer (Fig. 11, RDL3, ¶¶ [0030]-[0031]), and the fourth conductive layer (Fig. 11, 52A, ¶¶ [0030]-[0031]) are vertically arranged (Figs. 6 & 11, Chen’s layers are vertically arranged in the claimed order between vertical levels of 30B and 52) in such an order from the first connector structures (Fig. 6, 30B, ¶ [0024]) to the second connector structures (Fig. 6, 52, ¶ [0033]).
Regarding claim 8, Chen in view of Jeng in view of Tang teaches the method of claim 6, and Chen teaches a first spacing between adjacent ones of the first connector structures (Fig. 6, 30B, ¶ [0024]) is not proportional (There is no mention in Chen’s disclosure of the spacings between 30B and 52 being proportional) to a second spacing between adjacent ones of the second connector structures (Fig. 6, 52, ¶ [0033]).
Regarding claim 9, Chen in view of Jeng in view of Tang teaches that forming the redistribution structure (Fig. 11, 70, ¶ [0032]) further comprises laterally rotating (see Figs. 11 & 12B, topmost Via-3 is not laterally aligned with topmost Via-2 and the topmost Via-3 is instead laterally rotated around the relative position of the topmost Via-2) a fifth via structure (Figs. 11 & 12B, topmost Via-3 of via group VG-3, ¶ [0036]) among the plurality of via structures around a sixth via structure (Figs. 11 & 12B, topmost Via-2 of via group VG-2, ¶ [0036]) among the plurality of via structures, the fifth via structure being laterally aligned with the first via structure (Fig. 11, Leftmost Via-3 of via group VG-3, ¶ [0036]) and a third via structure (Figs. 11 & 12B, bottom rightmost Via-3 of via group VG-3), the sixth via structure being aligned with a fourth via structure (Fig. 11, rightmost Via-2 of Via group VG-2, ¶ [0036]).
Allowable subject matter
Claims 4 and 10 are objected to as being dependent upon a rejected base claim (claims 3 and 9), but would be allowable, pending 112(b) rejections above, if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: The closest prior art known to the Examiner is listed on the PTO 892 forms of record.
With respect to dependent claim 4, the cited prior art does not anticipate or make obvious, inter alia, the step of: “the first via structure, the second via structure, and the fourth via structure belong to a first net, while the third via structure belongs to a second, different net”.
With respect to dependent claim 10, the cited prior art does not anticipate or make obvious, inter alia, the step of: “the first to fourth via structure are configured to carry a first supply voltage, while the fifth to sixth via structures are configured to carry a second, different supply voltage”.
Claims 11-18 are allowed.
The following is an examiner’s statement of reasons for allowance: The closest prior art known to the Examiner is listed on the PTO 892 forms of record.
Regarding independent claim 11, none of the prior art of record teaches or suggests, alone or in combination, adjusting a location of a sixth via structure connecting a fourth conductive layer and a fifth conductive layer of the redistribution structure based on at least one of: (i) a location of a seventh via structure; or (ii) the location of the fourth or fifth via structure, wherein the fourth via structure and the sixth via structure extend downwardly and upwardly from the fourth conductive layer, respectively, the sixth via structure and the fifth via structure extend downwardly and upwardly from the fifth conductive layer, respectively, and the sixth and seventh via structures are laterally aligned with each other.
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub No. 2019/0373727 by Hayashi et al discloses a semiconductor device.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub No. 20150364444 by Scanlan et al discloses a semiconductor device.
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/R.P.S./
Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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