Prosecution Insights
Last updated: April 19, 2026
Application No. 18/329,387

METHODS FOR MOUNTING AN ELECTRONIC PACKAGE TO A CIRCUIT BOARD

Final Rejection §102§103
Filed
Jun 05, 2023
Examiner
BULLARD-CONNOR, GENEVIEVE GRACE
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Skyworks Solutions Inc.
OA Round
2 (Final)
43%
Grant Probability
Moderate
3-4
OA Rounds
3y 5m
To Grant
53%
With Interview

Examiner Intelligence

Grants 43% of resolved cases
43%
Career Allow Rate
3 granted / 7 resolved
-25.1% vs TC avg
Moderate +10% lift
Without
With
+10.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
61 currently pending
Career history
68
Total Applications
across all art units

Statute-Specific Performance

§103
48.2%
+8.2% vs TC avg
§102
32.7%
-7.3% vs TC avg
§112
19.1%
-20.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 7 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-5, 8-9, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwon (US 2019/0355667). Regarding claim 1, Kwon discloses a method for mounting an electronic package (11) to a circuit board (600, Figure 2A, considered a circuit board because 600 comprises a plurality of insulating layers and conductive traces therein, see para. [0046], which is the structure of a circuit board), the method comprising: providing an electronic package (11), the electronic package (11) including a substrate (100) having a first side (upper side) and a second side (lower side), a first electronic module (210) mounted to the first side (upper side) of the substrate (100, see Figure 2A), a first mold structure (base layer 409) extending over at least part of the first side (upper side) of the substrate (100, see Figure 2A), and a group of through-mold connections (400’, see Figure 2B) that are electrically conductive (“conductive structure” 400’, para. [0063] discloses 400’ being formed of copper) and provided on the first side (upper side) of the substrate (100, see Figure 2A), the group of through-mold connections (400’) being flush with an outer surface of the first mold structure (409, see Figure 2B, which shows the lower and upper surfaces of the through-mold connections 400’ being flush or coplanar with the lower and upper surfaces of the first mold structure, respectively) and exposed through the first mold structure (409, see upper and lower surfaces of the through-mold connections 400’ that are not in direct physical contact with the mold structure 409, thus are exposed through the mold structure 409, see Figure 2B); providing a circuit board (600, see Figure 2A, para. [0068]); and mounting the electronic package (11) to the circuit board (600) by use of a group of intermediate solder portions (452, connected to upper surfaces of each through-mold connections 400’, because the through-mold connections 400’ are connected to the circuit board through the group of intermediate solder portions 452, the intermediate solder portions are considered as being used to mount to package 11 to the circuit board 600) such that each intermediate solder portion (452) of the group of intermediate solder portions (452) couples a corresponding through-mold connection (400’) of the group of through-mold connections (400’) to the circuit board (600, see Figure 2A), the intermediate solder portions (452) protruding from the outer surface of the first mold structure (409, Figure 2B shows the solder portions 452 extending from the outer upper surface of the first mold structure) the through-mold connections (400’) having a melting point in excess of a melting point of the intermediate solder portions (452, para. [0064] discloses that the through-mold connections 400’ have a higher melting point than that of the intermediate solder portions 452). Regarding claim 2, Kwon discloses in which the mounting the electronic package (11) to the circuit board (600) comprises fusing each intermediate solder portion (452) directly to an end face of a corresponding one of the group of through-mold connections (400’, para. [0093] discloses a soldering method of melting, i.e. reflowing, the intermediate solder portions 452 on the through-mold connections 400’, which would comprise fusing the intermediate solder portions 452 to the though-mold connections 400’). Regarding claim 3, Kwon discloses in which the mounting the electronic package (11) to the circuit board (600) comprises performing a reflow operation (melting intermediate solder portions 452, see para. [0093]) that reflows each intermediate solder portion (452) directly to an end face of a corresponding one of the through-mold connections (400’, see para. [0093]). Regarding claim 4, Kwon discloses in which performing the reflow operation (melting, para. [0093]) includes applying heat sufficient to liquify the intermediate solder portions (452, see para. [0093] which discloses that intermediate solder portions 452 are heated to their melting point) in preference to the through-mold connections (400’, para. [0064] discloses that the melting point of through-mold connections 400’ is greater than that of the intermediate solder portions 452, and since the temperature applied is the melting point of the intermediate solder portions 452, the intermediate solder portions 452 are liquified in preference to the through-mold connections 400’). Regarding claim 5, Kwon discloses that performing the reflow operation (melting, para. [0093]) includes controlling the application of heat so as to avoid liquification of the through-mold connections (400’) during the reflow operation (para. [0093] discloses that the temperature applied is the melting temperature of the intermediate solder portions 452, which is lower than that of the through-mold connections, thus liquification of the through-mold connections 400’ is avoided, and the through-mold connections are disclosed as keeping their shape during the heat treatment, i.e. reflow/melting, process). Regarding claim 8, Kwon discloses performing the reflow operation (melting, para. [0093]) comprises controlling the application of heat such that the through-mold connection (400’) remains wholly or partially in a solid phase throughout the reflow operation (para. [0093] discloses that the through-mold connections 400’ keep their shape during the heat treatment, i.e. reflow/melting, process and that the heat treatment process is performed at the melting point of the intermediate solder portions 452 which is less than that of the through-mold connections 400’). Regarding claim 9, Kwon discloses an outer surface of the first mold structure (409) is free of any moat or channel circumscribing and adjacent to each of the through-mold connections (400’, see Figure 2A which shows flat surfaces of the molding structure 409 around the through-mold connections 400’). Regarding claim 12, Kwon discloses the through-mold connections (400’) are formed of a metallic material (see metallic materials for through-mold connections 400’ listed in para. [0063], which is copper). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 10-11 and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon as applied to claim 1 above, and further in view of Ishii (US 2023/0223317). Regarding claim 10, Kwon does not disclose the through-mold connections (400’) are formed of an alloy (see para. [0063], which discloses the through-mold connections are formed of copper) the alloy having a solidus temperature greater than a liquidus temperature of the intermediate solder portions. Ishii discloses, however, through-mold connections (41/42, extending through mold 9) wherein the through-mold connections are formed of an alloy (tin and antimony, see para. [0056]), the alloy having a solidus temperature greater than a liquidus temperature of the intermediate solder portions (solder bonding layer 10, para. [0056]). It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Ishii above into the teachings of Kwon for the purpose of utilizing a material with a higher melting point for the through-mold connections than that of other solder bonding materials in order to avoid remelting of said material during subsequent heating/bonding processes during manufacture (Ishii, para. [0056]). Regarding claim 11, Kwon does not disclose that the melting point of the through-mold connections exceeds the melting point of the intermediate solder portions by at least 10 degrees Celsius. Ishii discloses through-mold connections (41/42, see Figure 4, extending through mold 9) where the melting point of the through-mold connections exceeds the melting point of the intermediate solder portions (module bonding material 10) by at least 10 degrees Celsius (see para. [0056], a temperature difference of 30 degrees Celsius is disclosed). It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Ishii into the teachings of Kwon to include a melting point difference between the through-mold connections and the intermediate solder portions of at least 10 degrees Celsius for the purpose of utilizing a material with a high melting point, for the through-mold connections, in order to avoid remelting of said material during subsequent heating/bonding processes during manufacture (Ishii, para. [0056]). Regarding claim 13, Kwon discloses that the through-mold connections (400’) are formed of copper (see para. [0063]), which is not necessarily considered a solder material in the art. Ishii discloses, however, through-mold connections (41/42, Figure 4) formed of a solder material (see para. [0056], which discloses a tin and antimony solder composition). It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Ishii into the teachings of Kwon to include a solder material for the through-mold connections for the purpose of utilizing a solder material with a high melting point (Ishii, para. [0056]). Additionally, the selection of a known material based on its suitability for its intended purpose is prima facie obvious, see MPEP 2144.07 and Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). Regarding claim 14, Ishii discloses that the solder material (para. [0056]) is free of lead (the solder material is a tin and antimony composition, thus does not contain any lead). Regarding claim 15, Ishii discloses an alloy used for through-mold connections (41/42, see Figure 4 which shows the connections 41/42 extend through the mold material 9 to connect different elements of the device) including tin and antimony (see para. [0056]). It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Ishii into the teachings of Kwon to include a tin and antimony alloy material for the through-mold connections for the purpose of utilizing a material with a high melting point in order to avoid remelting of said material during subsequent heating/bonding processes during manufacture (Ishii, para. [0056]). Additionally, the selection of a known material based on its suitability for its intended purpose is prima facie obvious, see MPEP 2144.07 and Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). Regarding claim 16, Ishii discloses an alloy for through-mold connections (41/42, see para. [0056]) that has a solidus temperature of at least 240 degrees Celsius (para. [0056] discloses that the liquidus temperature of the tin/antimony alloy of the through-mold connections 41/42 is about 240 degrees Celsius, thus the solidus temperature is at least 240 degrees Celsius). It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Ishii into the teachings of Kwon to include a tin and antimony alloy material for the through-mold connections having a solidus temperature of at least 240 degrees Celsius for the purpose of utilizing a material with a high melting point in order to avoid remelting of said material during subsequent heating/bonding processes during manufacture (Ishii, para. [0056]). Additionally, the selection of a known material based on its suitability for its intended purpose is prima facie obvious, see MPEP 2144.07 and Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon (US 2019/0355667) and Ishii (US 2023/0223317). Regarding claim 19, Kwon discloses a method for mounting an electronic package (11) to a circuit board (600, Figure 2A, considered a circuit board because 600 comprises a plurality of insulating layers and conductive traces therein, see para. [0046], which is the structure of a circuit board), the method comprising: providing an electronic package (11), the electronic package (11) including a substrate (100) having a first side (upper side) and a second side (lower side), a first electronic module (210) mounted to the first side (upper side) of the substrate (100, see Figure 2A), a first mold structure (base layer 409) extending over at least part of the first side (upper side) of the substrate (100, see Figure 2A), and a group of through-mold connections (400’) that are electrically conductive (“conductive structure” 400’, para. [0063] discloses a copper material used) and provided on the first side (upper side) of the substrate (100, see Figure 2A), the group of through-mold connections (400’) being flush with an outer surface of the first mold structure (409, see Figure 2B, which shows the lower and upper surfaces of the through-mold connections 400’ being flush or coplanar with the lower and upper surfaces of the first mold structure, respectively) and exposed through the first mold structure (409, see upper and lower surfaces of the through-mold connections 400’ that are not in direct physical contact with the mold structure 409, thus are exposed through the mold structure 409, see Figure 2B); providing a circuit board (600, see Figure 2A, para. [0068]) configured to receive the electronic package (11, see Figure 2A, the circuit board 600 is bonded to, or receives, the electronic package 11); and mounting the electronic package (11) the circuit board (600) by use of a group of intermediate solder portions (452, connected to upper surfaces of each through-mold connections 400’, because the through-mold connections 400’ are connected to the circuit board through the group of intermediate solder portions 452, the intermediate solder portions are considered as being used to mount to package 11 to the circuit board 600) such that each intermediate solder portion (452) of the group of intermediate solder portions (452) couples a corresponding through-mold connection (400’) of the group of through-mold connections (400’, see Figure 2A) to the circuit board (600, see Figure 2A), the intermediate solder portions (452) protruding from the outer surface of the first mold structure (409, Figure 2B shows the solder portions 452 extending from the outer upper surface of the first mold structure). Kwon does not disclose the through-mold connections (400’) are formed of an alloy (see para. [0063], which discloses the through-mold connections are formed of copper) including tin and antimony, the alloy having a solidus temperature greater than a liquidus temperature of the intermediate solder portions. Ishii discloses, however, through-mold connections (41/42, extending through mold 9) formed of an alloy including tin and antimony (tin and antimony, see para. [0056]), the alloy having a solidus temperature greater than a liquidus temperature of the intermediate solder portions (solder bonding layer 10, para. [0056]). It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Ishii above into the teachings of Kwon for the purpose of utilizing a material with a higher melting point for the through-mold connections than that of other solder bonding materials in order to avoid remelting of said material during subsequent heating/bonding processes during manufacture (Ishii, para. [0056]). Additionally, the selection of a known material based on its suitability for its intended purpose is prima facie obvious, see MPEP 2144.07 and Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). Regarding claim 20, Kwon discloses a method for mounting an electronic package (11) to a circuit board (600, Figure 2A, considered a circuit board because 600 comprises a plurality of insulating layers and conductive traces therein, see para. [0046], which is the structure of a circuit board), the method comprising: providing an electronic package (11), the electronic package (11) including a substrate (100) having a first side (upper side) and a second side (lower side), a first electronic module (210) mounted to the first side (upper side) of the substrate (100, see Figure 2A), a first mold structure (409) extending over at least part of the first side (upper side) of the substrate (100, see Figure 2A), and a group of through-mold connections (400’) that are electrically conductive (“conductive structure” 400’, para. [0063] discloses 400’ may be formed of copper) and provided on the first side (upper side) of the substrate (100, see Figure 2A), the group of through-mold connections (400’) being flush with an outer surface of the first mold structure (409, see Figure 2B, which shows the lower and upper surfaces of the through-mold connections 400’ being flush or coplanar with the lower and upper surfaces of the first mold structure, respectively) and exposed through the first mold structure (409, see upper and lower surfaces of the through-mold connections 400’ that are not in direct physical contact with the mold structure 409, thus are exposed through the mold structure 409, see Figure 2B); providing a circuit board (600, see Figure 2A, para. [0068]); and mounting the electronic package (11) to the circuit board (600) by use of a group of intermediate solder portions (452, connected to upper surfaces of each through-mold connections 400’, because the through-mold connections 400’ are connected to the circuit board through the group of intermediate solder portions 452, the intermediate solder portions are considered as being used to mount to package 11 to the circuit board 600) such that each intermediate solder portion (452) of the group of intermediate solder portions (452) couples a corresponding through-mold connection (400’) of the group of through-mold connections (400’) to the circuit board (600, see Figure 2A), the intermediate solder portions (452) protruding from the outer surface of the first mold structure (409, Figure 2B shows the solder portions 452 extending from the outer upper surface of the first mold structure 409). Kwon does not disclose that the through-mold connections are formed of an alloy including tin and antimony, the alloy having a solidus temperature of at least 240 degrees Celsius. Ishii discloses through-mold connections (41/42, see Figure 4 which shows the connections 41/42 extend through the mold material 9 to connect different elements of the device) formed of an alloy including tin and antimony (see para. [0056]), the alloy having a solidus temperature of at least 240 degrees Celsius (para. [0056] discloses that the liquidus temperature of the tin/antimony alloy of the through-mold connections 41/42 is about 240 degrees Celsius, thus the solidus temperature is at least 240 degrees Celsius). It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Ishii into the teachings of Kwon to include a tin and antimony alloy material for the through-mold connections having a solidus temperature of at least 240 degrees Celsius for the purpose of utilizing a material with a high melting point in order to avoid remelting of said material during subsequent heating/bonding processes during manufacture (Ishii, para. [0056]). Additionally, the selection of a known material based on its suitability for its intended purpose is prima facie obvious, see MPEP 2144.07 and Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). Response to Arguments Applicant’s arguments with respect to claims 1, 19, and 20 have been considered but are moot because the new ground of rejection does not rely on any interpretation of the reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant’s amendments to claim 19 overcomes the objection to claim 19. The objection to claim 19 is withdrawn. Applicant’s amendments to claims 1, 5, 12, and 19-10 overcome the 112(b) rejections of claims 1, 5, 12, and 19-20. The 112(b) rejections are withdrawn. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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Prosecution Timeline

Jun 05, 2023
Application Filed
Dec 09, 2025
Non-Final Rejection — §102, §103
Mar 04, 2026
Response Filed
Mar 20, 2026
Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12525517
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
2y 5m to grant Granted Jan 13, 2026
Study what changed to get past this examiner. Based on 1 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
43%
Grant Probability
53%
With Interview (+10.0%)
3y 5m
Median Time to Grant
Moderate
PTA Risk
Based on 7 resolved cases by this examiner. Grant probability derived from career allow rate.

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