Prosecution Insights
Last updated: July 17, 2026
Application No. 18/329,589

INTEGRATED CIRCUIT AND LOW DROP-OUT LINEAR REGULATOR CIRCUIT

Final Rejection §103
Filed
Jun 06, 2023
Priority
Dec 26, 2022 — TW 111150011
Examiner
NADAV, ORI
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Realtek Semiconductor Corporation
OA Round
2 (Final)
60%
Grant Probability
Moderate
3-4
OA Rounds
8m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allowance Rate
422 granted / 701 resolved
-7.8% vs TC avg
Strong +21% interview lift
Without
With
+21.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 9m
Avg Prosecution
48 currently pending
Career history
769
Total Applications
across all art units

Statute-Specific Performance

§103
89.4%
+49.4% vs TC avg
§102
3.9%
-36.1% vs TC avg
§112
5.2%
-34.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 701 resolved cases

Office Action

§103
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA DETAILED ACTION Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-6 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (12,073,165). Regarding claim 1, Chung et al. teach in figure 7 and related text an integrated circuit, comprising: a plurality of first conductive segments 132 and a plurality of second conductive segments 140 that are separated from each other in a first direction; a plurality of third conductive segments 134 and a plurality of fourth conductive segments 136 that are separated from each other along the first direction, wherein the plurality of first conductive segments 132 and the plurality of third conductive segments 134 are interposed between a plurality of first gates 106 and separated from the plurality of first gates 106 in a plan view, and the plurality of second conductive segments 140 and the plurality of fourth conductive segments 136 are arranged between a plurality of second gates (another 106); a first conductive line (the conductive line connected to source contact via 112) which can transmit a drain/source signal and coupled to the plurality of first conductive segments 132 and the plurality of second conductive segments 140; and a second conductive line (the conductive line connected to source contact via 110) which can transmit a source/drain signal and coupled to the plurality of third conductive segments 134 and the plurality of fourth conductive segments 136, wherein the plurality of third conductive segments 134 and the plurality of fourth conductive segments 136 are mirrored symmetrically with respect to the second conductive line 140 in a plan view. Chung et al. do not explicitly state that the first and second conductive lines are configured to transmit a drain/source signal. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to configure the first and second conductive lines to transmit a drain/source signal, in Chung et al.’s device, in order to be able to operate the device. Regarding claim 2, Chung et al. teach in figure 7 and related text that the plurality of first conductive segments 132 and the plurality of second conductive segments 140 are mirrored symmetrically with respect to the second conductive line. Regarding claim 3, Chung et al. teach in figure 7 and related text that a first active area 104 coupled to the plurality of first conductive segments 132 and the plurality of third conductive segments 134, and having a first width along the first direction, wherein the plurality of first conductive segments 132 to the plurality of fourth conductive segments 136 extend in the first direction, and the second conductive line extends in a second direction different from the first direction, and has a second width along the first direction. Chung et al. does not teach that the second conductive line in which the second width is greater than the first width. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the second width greater than the first width, in Chung et al.’s device, in order to optimize the device characteristics and improve the conductivity of the device. It is to be presumed also that skilled workers would as a matter of course, if they do not immediately obtain desired results, make certain experiments and adaptations, within the skill of the competent worker. The failures of experimenters who have no interest in succeeding should not be accorded great weight. In re Michalek, 162 F.2d 229, 232 (CCPA 1947); In re Reid, 179 F.2d 998, 1002 (CCPA 1950). See In re Boesch, 617 F.2d 272, 276 (CCPA 1980) (“[Djiscovery of an optimum value of a result effective variable in a known process is ordinarily within the skill of the art.”); In re Aller, 220 F.2d 454, 456 (CCPA 1955) (“where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.”). Regarding claim 4, Chung et al. teach in figure 7 and related text that the first conductive line has a third width different from the second width along the first direction, since the first conductive line is formed in a via hole which has a third width different from the second width. Regarding claim 5, Chung et al. do not teach that the third width is less than the first width and the second width. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the third width is less than the first width and the second width, in Chung et al.’s device, in order to optimize the device characteristics and improve the conductivity of the device. Regarding claim 6, Chung et al. teach in figure 7 and related text that a second active area (another 104) coupled to the plurality of second conductive segments and the plurality of fourth conductive segments, wherein the second conductive line is arranged between the first active area and the second active area. Regarding claim 17, Chung et al. teach in figure 7 and related text a circuit, comprising: a first conductive line (the conductive line connected to source contact via 112) and a second conductive line (the conductive line connected to source contact via 110); and a circuit, comprising: a plurality of first conductive segments 132 and a plurality of second conductive segments 138, wherein the plurality of first conductive segments and the plurality of second conductive segments are mirrored with respect to a first direction and correspond to a middle conductive line 140 of a source/drain of the circuit; and a plurality of first active regions 104 arranged in a first active area and a plurality of second active regions (another 104) arranged in a second active area, wherein the first active area and the second active area are arranged between the first conductive line and the second conductive line, and the plurality of first active regions 104 and the plurality of second active regions (another 104) are coupled to the second conductive line by the plurality of first conductive segments and the plurality of second conductive segments, separately, and a plurality of gates 106, wherein the plurality of first conductive segments and the plurality of second conductive segments are interposed between a plurality of first gates and separated from the plurality of first gates in a plan view. Chung et al. do not teach using the circuit in an output stage circuit of a low drop-out linear regulator circuit, and wherein the middle conductive line corresponds to a source/drain of the output stage circuit. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use Chung et al.’s circuit in an output stage circuit of a low drop-out linear regulator circuit, and wherein the middle conductive line corresponds to a source/drain of the output stage circuit, in order to expand the device capabilities. Regarding claim 18, Chung et al. teach in figure 7 and related text the output stage circuit further comprises: a plurality of third conductive segments 134 and a plurality of fourth conductive segments 136 that are mirrored with respect to the first direction and corresponding to a middle conductive line 140 of a drain/source terminal of the output stage circuit (see above analysis); and a plurality of third active regions arranged in the first active area 104 and a plurality of fourth active regions arranged in the second active area (another 104), wherein the plurality of third active regions and the plurality of fourth active regions are coupled to the second conductive line through the plurality of fourth conductive segments and the plurality of third conductive segments, separately. Response to Arguments 1. Applicants argue that Chung does not show that the conductive lines 132 and 134 are separated from the gate structures 106 in the plan view, because “in a plan view the conductive lines 132 and 134 overlap with the gate structures 106”. 1. Conductive lines 132 and 134 are not connected to, and thus separated, from the gate structures 106. Although the conductive lines 132 and 134 overlap with the gate structures 106 in a plan view, the conductive lines 132 and 134 are sill separated from the gate structures 106. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). O.N. /ORI NADAV/ 5/17/2026 PRIMARY EXAMINER TECHNOLOGY CENTER 2800
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Prosecution Timeline

Jun 06, 2023
Application Filed
Feb 11, 2026
Non-Final Rejection mailed — §103
May 05, 2026
Response Filed
May 20, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
60%
Grant Probability
81%
With Interview (+21.1%)
3y 9m (~8m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 701 resolved cases by this examiner. Grant probability derived from career allowance rate.

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