DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Amendment filed July 15, 2026 is acknowledged. Claims 1, 5, 8, 13 and 15 have been amended. Claims 1-20 are pending.
Action on merits of claims 1-20 follows.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-9, 11, 13-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over KANG et al. (US. Pub. No. 2022/0130970) of record, in view of HUANG et al. (US. Pub. No. 2023/0033289).
With respect to claim 1, KANG teaches a semiconductor device substantially as claimed including:
a gate structure (GS) disposed on a substrate (100); and
a contact plug including:
a first conductive pattern (180-207LP) contacting an upper surface of the gate structure (GS); and
a second conductive pattern (207UP) contacting an upper surface of the first conductive pattern,
wherein an upper surface of a central portion (207LP_US) of the first conductive pattern is higher than an upper surface of an edge portion (207a_US) of the first conductive pattern,
wherein a lower surface of a central portion (207LP_US) of the second conductive pattern (207UP) is higher than a lower surface of an edge portion (207a_US) of the second conductive pattern corresponding to the upper surface (207LP--_US-207a_US) of the first conductive pattern, and
wherein a portion of the first conductive pattern (180-207LP) is in direct contact with the gate structure (GS). (See FIG. 6).
Thus, KANG is shown to teach all the features of the claim with the exception of explicitly disclosing the portion of a sidewall of the first conductive pattern is in direct contact with the gate structure (GS).
However, HUANG teaches a semiconductor device including:
a gate structure (94) disposed on a substrate (50); and
a contact plug including:
a first conductive pattern (110) contacting an upper surface of the gate structure (94) (GS),
wherein a portion of a sidewall of the first conductive pattern (110) is in direct contact with the gate structure (94). (See FIGs. 17B, 18B, 21B).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form a portion of a sidewall of the first conductive pattern of KANG being in direct contact with the gate structure as taught by HUANG to increase the contact surface, thus, more secure contact.
With respect to claim 8, KANG teaches a semiconductor device substantially as claimed including:
a gate structure (GS) disposed on a substrate (100); and
a contact plug including:
a first conductive pattern (180-207LP) contacting an upper surface of the gate structure (GS); and
a second conductive pattern (207UP) contacting an upper surface (-US) of the first conductive pattern,
wherein an upper surface (207a_US) of an edge portion (207a) of the first conductive pattern is higher than an upper surface of a central portion (207LP_US) of the first conductive pattern,
wherein a lower surface of a central portion (207LP_US) of the second conductive pattern (207UP) is lower than a lower surface of an edge portion (207a_US) of the second conductive pattern (207UP) corresponding to the upper surface (_US) of the first conductive pattern,
wherein a width of the edge portion (207a) of the first conductive pattern, measured in a horizontal direction substantially parallel to an upper surface of the substrate (100), is smaller than a thickness (H21) of the central portion of the first conductive pattern, in a vertical direction substantially perpendicular to the upper surface, and
wherein a portion of the first conductive pattern (180-207LP) is in direct contact with the gate structure (GS). (See FIG. 7).
Thus, KANG is shown to teach all the features of the claim with the exception of explicitly disclosing the portion of a sidewall of the first conductive pattern is in direct contact with the gate structure (GS).
However, HUANG teaches a semiconductor device including:
a gate structure (94) disposed on a substrate (50); and
a contact plug including:
a first conductive pattern (110) contacting an upper surface of the gate structure (94) (GS),
wherein a portion of a sidewall of the first conductive pattern (110) is in direct contact with the gate structure (94). (See FIGs. 17B,18B, 21B).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form a portion of a sidewall of the first conductive pattern of KANG being in direct contact with the gate structure as taught by HUANG to increase the contact surface, thus, more secure contact.
With respect to claim 15, KANG teaches a semiconductor device substantially as claimed including:
an active pattern (105) disposed on a substrate (100), the active pattern extending in a first direction (X) that is substantially parallel to an upper surface of the substrate (100), a gate structure (GS) disposed on the active pattern, the gate structure extending in a second direction (Y) that is substantially parallel to the upper surface of the substrate and crosses the first direction (X);
a source/drain layer (150) disposed on the active pattern adjacent to the gate structure (GS) in the first direction (X);
a plurality of channels (UP1) spaced apart from each other in a third direction (Z) that is substantially perpendicular to the upper surface of the substrate;
an insulating interlayer (190-191) disposed on the gate structure (GS); and
a contact plug extending through the insulating interlayer (190-191) and contacting an upper surface of the gate structure (GS), the contact plug including:
a first conductive pattern (180-207LP) including a first metal; and
a second conductive pattern (207UP) contacting an upper surface (_US) of the first conductive pattern and including a second metal,
wherein an upper surface (_US) of a central portion of the first conductive pattern (207LP) is higher than an upper surface (_US) of an edge portion (270a) of the first conductive pattern,
wherein a lower surface (_US) of a central portion of the second conductive pattern (207UP) is higher than a lower surface (207a_US) of an edge portion of the second conductive pattern (207UP) corresponding to the upper surface (_US) of the first conductive pattern, and
wherein a portion of the first conductive pattern is in direct contact with the gate structure (GS). (See FIGs. 6, 23).
Thus, KANG is shown to teach all the features of the claim with the exception of explicitly disclosing the portion of a sidewall of the first conductive pattern is in direct contact with the gate structure (GS).
However, HUANG teaches a semiconductor device including:
a gate structure (94) disposed on a substrate (50); and
a contact plug including:
a first conductive pattern (110) contacting an upper surface of the gate structure (94) (GS),
wherein a portion of a sidewall of the first conductive pattern (110) is in direct contact with the gate structure (94). (See FIGs. 17B,18B, 21B).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form a portion of a sidewall of the first conductive pattern of KANG being in direct contact with the gate structure as taught by HUANG to increase the contact surface, thus, more secure contact.
With respect to claim 2, a width of the edge portion (207a) of the first conductive pattern of KANG, in a horizontal direction substantially parallel to an upper surface of the substrate (100), is smaller than a thickness (H21) of the central portion of the first conductive pattern (207LP), in a vertical direction substantially perpendicular to the upper surface of the substrate.
With respect to claims 3 and 11, the first and second conductive patterns of KANG include a same metal.
With respect to claims 5 and 13, semiconductor device of KANG further comprising an insulating interlayer (191) disposed on the gate structure (GS), the insulating interlayer (191) covering a sidewall of the contact plug (207),
wherein a portion of the insulating interlayer (191) adjacent to the contact plug (207) further includes the same metal of the first and second conductive patterns.
In the Remarks filed November 17, 2025, citing ¶ [0092], Applicant confirmed that deposited metal may diffuse into the insulating layer.
With respect to claims 6 and 20, the gate structure (GS) of KANG or HUANG includes:
a gate electrode (120); and
a gate insulation pattern (130) disposed on a lower surface and a sidewall of the gate electrode (120),
wherein the first conductive pattern directly contacts the gate electrode (120).
With respect to claim 7, the semiconductor device of KANG or HUANG further comprising a plurality of channels (UP1) spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, each of the channels extending through the gate structure.
With respect to claim 9, the width of the edge portion (207a) of the first conductive pattern of KANG is substantially constant along the vertical direction.
With respect to claims 14 and 16, the second conductive pattern (UP) of KANG directly contacts the insulating interlayer.
With respect to claim 17, a portion of the insulating interlayer of KANG adjacent to the contact plug further includes the first metal.
With respect to claim 19, a width of the edge portion of the first conductive pattern of KANG in a horizontal direction (X) substantially parallel to the upper surface of the substrate, is smaller than a thickness (H21) of the central portion of the first conductive pattern in the third direction.
Claims 4, 12 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over KANG ‘970 and HUANG ‘696 as applied to claims 3, 11 and 16 above, and further in view of CHAN et al. (US. Patent No. 7955972) of record.
KANG, in view of HUANG, teaches the semiconductor device as described in claims 3, 11 and 16 including: second conductive pattern of tungsten selectively deposited.
Thus, KANG and HUANG are shown to teach all the features of the claim with the exception of explicitly disclosing the second pattern further including fluorine, chlorine, boron and/or silicon.
However, CHAN teaches a semiconductor device including a conductive pattern of tungsten, selectively deposited from WF6 in a reduction reaction with silane or borane to form a low resistance tungsten. (See [0025]-[0026]).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the tungsten second conductive pattern of KANG and HUANG utilizing the reduction reaction as taught by CHAN to provide for low resistance contact.
The conductive pattern includes fluorine, chlorine, boron and/or silicon is an inherent result of the selective deposit of conductive metal utilizing reduction reaction of silane or borane.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over KANG ‘970 and HUANG ‘696, as applied to claim 8 above, and further in view of HSU (US. Pub. No. 2022/0139777) of record.
KANG, in view of HUANG, teaches the semiconductor device as described in claim 8 above including: the width of the edge portion of the first conductive pattern, measured in a horizontal direction substantially parallel to an upper surface of the substrate, is smaller than the thickness of the substrate of the central portion of the first conductive pattern, in a vertical direction substantially perpendicular to the upper surface.
Thus, KANG and HUANG are shown to teach all the features of the claim with the exception of explicitly disclosing the width of the edge portion of the first conductive pattern decreases in the vertical direction from a portion of the edge portion of the first conductive pattern.
However, HSU teaches a semiconductor device including:
a width of an edge portion of first conductive pattern (301) decreases in the vertical direction from a portion of the edge portion of the first conductive pattern (301) at a height of the upper surface of the central portion of the first conductive pattern to an uppermost portion of the edge portion of the first conductive pattern (301). (See Figs. 5, 26).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the first conductive pattern of KANG having the width of the edge portion of a first conductive pattern decreases in the vertical direction from a portion of the edge portion of the first conductive pattern as taught by HSU for the same intended purpose of recessing the central portion of the first conductive pattern.
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 10:00-4:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue A Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANH D MAI/Primary Examiner, Art Unit 2893
Prosecution Insights