DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 03, 2026 has been entered.
Status of the Claims
Amendment filed February 03, 2026 is acknowledged. Claims 1, 8 and 15 have been amended. Claims 1-20 are pending.
Action on merits of claims 1-20 follows.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 7-9, 11, 13-17 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KANG et al. (US. Pub. No. 2022/0130970) of record.
With respect to claim 1, KANG teaches a semiconductor device as claimed including:
a gate structure (GS) disposed on a substrate (100); and
a contact plug including:
a first conductive pattern (207LP-207a) contacting an upper surface of the first gate structure (GS); and
a second conductive pattern (207UP) contacting an upper surface of the first conductive pattern (207LP-207a),
wherein an upper surface of a central portion (207LP-_US) of the first conductive pattern is higher than an upper surface of an edge portion (207a_US) of the first conductive pattern (207LP-207a), and
wherein a lower surface of a central portion of the second conductive pattern (207UP) is higher than a lower surface of an edge portion of the second conductive pattern corresponding to the upper surface (207LP--_US-207a_US) of the first conductive pattern (207LP-207a). (See FIG. 6).
With respect to claim 2, a width of the edge portion (207a) of the first conductive pattern (207LP), in a horizontal direction substantially parallel to an upper surface of the substrate (100), is smaller than a thickness (H21) of the central portion of the first conductive pattern (207LP), in a vertical direction substantially perpendicular to the upper surface of the substrate.
With respect to claim 3, the first (LP) and second (UP) conductive patterns include a same metal.
With respect to claim 5, semiconductor device of KANG further comprising an insulating interlayer (191) disposed on the gate structure (GS), the insulating interlayer (191) covering a sidewall of the contact plug (207), wherein a portion of the insulating interlayer (191) adjacent to the contact plug (207) further includes the metal of the first (LP) and second (UP) conductive patterns.
In the Remarks filed November 17, 2025, citing ¶ [0092], Applicant confirmed that deposited metal may diffuse into the insulating layer.
With respect to claim 7, the semiconductor device of KANG further comprising a plurality of channels (UP1) spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, each of the channels extending through the gate structure.
With respect to claim 8, KANG teaches a semiconductor device as claimed including:
a gate structure (GS) disposed on a substrate (100); and
a contact plug including:
a first conductive pattern (207LP-207a) contacting an upper surface of the first gate structure (GS); and
a second conductive pattern (207UP) contacting an upper surface (-US) of the first conductive pattern,
wherein an upper surface (207a_US) of an edge portion (207a) of the first conductive pattern is higher than an upper surface of a central portion (207LP_US) of the first conductive pattern,
wherein a lower surface of a central portion of the second conductive pattern (207UP) is lower than a lower surface (US) of an edge portion of the second conductive pattern (207UP) corresponding to the upper surface (US) of the first conductive pattern,
wherein a width of the edge portion (207a) of the first conductive pattern, measured in a horizontal direction substantially parallel to an upper surface of the substrate (100), is smaller than a thickness (H21) of the central portion of the first conductive pattern (207LP), in a vertical direction substantially perpendicular to the upper surface. (See FIG. 7).
With respect to claim 9, the width of the edge portion (207a) of the first conductive pattern (207LP) is substantially constant along the vertical direction.
With respect to claim 11, the first (LP) and second (UP) conductive patterns of KANG include a same metal.
With respect to claim 13, the semiconductor device of KANG further comprises an insulating interlayer (191) disposed on the gate structure (GS), the insulating interlayer covering a sidewall of the contact plug (207), wherein a portion of the insulating interlayer (191) adjacent to the contact plug (207) further includes the metal of the first (LP) and second (UP) conductive patterns.
With respect to claim 14, the second conductive pattern (UP) directly contacts the insulating interlayer (191).
With respect to claim 15, KANG teaches a semiconductor device substantially as claimed including:
an active pattern (105) disposed on a substrate (100), the active pattern extending in a first direction that is substantially parallel to an upper surface of the substrate (100), a gate structure (GS) disposed on the active pattern, the gate structure extending in a second direction that is substantially parallel to the upper surface of the substrate and crosses the first direction;
a source/drain layer (150) disposed on the active pattern adjacent to the gate structure (GS) in the first direction;
a plurality of channels (UP1) spaced apart from each other in a third direction that is substantially perpendicular to the upper surface of the substrate;
an insulating interlayer (191) disposed on the gate structure (GS); and
a contact plug (270) extending through the insulating interlayer (191) and contacting an upper surface of the gate structure (GS), the contact plug including:
a first conductive pattern (LP) including a first metal; and
a second conductive pattern (UP) contacting an upper surface of the first conductive pattern (LP) and including a second metal,
wherein an upper surface (US) of a central portion of the first conductive pattern (LP) is higher than an upper surface of an edge portion (270a) of the first conductive pattern (LP), and
wherein a lower surface of a central portion of the second conductive pattern (UP) is higher than a lower surface of an edge portion of the second conductive pattern (UP) corresponding to the upper surface of the first conductive pattern (LP). (See FIG. 6).
With respect to claim 16, the second conductive pattern (UP) of KANG directly contacts the insulating interlayer (191).
With respect to claim 17, a portion of the insulating interlayer (191) adjacent to the contact plug (270) further includes the first metal.
With respect to claim 19, a width of the edge portion of the first conductive pattern (LP), in a horizontal direction substantially parallel to the upper surface of the substrate, is smaller than a thickness (H21) of the central portion of the first conductive pattern (LP) in the third direction.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 12 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over KANG ‘970 as applied to claims 3, 11 and 16 above, and further in view of CHAN et al. (US. Patent No. 7955972) of record.
KANG teaches the semiconductor device as described in claims 3, 11 and 16 including: second conductive pattern of tungsten selectively deposited.
Thus, KANG is shown to teach all the features of the claim with the exception of explicitly disclosing the second pattern further including fluorine, chlorine, boron and/or silicon.
However, CHAN teaches a semiconductor device including a conductive pattern of tungsten, selectively deposited from WF6 in a reduction reaction with silane or borane to form a low resistance tungsten. (See [0025]-[0026]).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the tungsten second conductive pattern of KANG utilizing the reduction reaction as taught by CHAN to provide for low resistance contact.
The conductive pattern includes fluorine, chlorine, boron and/or silicon is an inherent result of the selective deposit of conductive metal utilizing reduction reaction of silane or borane.
Claims 6 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over KANG ‘970 as applied to claims 1 and 15 above, and further in view of WANG et al. (US. Pub. No. 2021/0257254) of record.
With respect to claims 6 and 20, KANG teaches the semiconductor device as described in claims 1 and 15 including: the gate structure (GS) includes: a gate electrode (120); and a gate insulation pattern (130) disposed on a lower surface and a sidewall of the gate electrode (120), wherein the first conductive pattern contacting the upper surface of the gate structure.
Thus, KANG is shown to teach all the features of the claim with the exception of explicitly disclosing the first conductive pattern directly contacting the gate electrode.
However, WANG teaches a semiconductor device including: a first conductive pattern (56B) contacting an upper surface of a gate structure (26), wherein the gate structure (26) including a gate electrode (28); and a gate insulation pattern (24) disposed on a lower surface and a sidewall of the gate electrode (28), wherein the first conductive pattern (56B) directly contacting the gate electrode (28). (See FIG. 10B).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor device of KANG having the first conductive pattern (56B) directly contacting the gate electrode as taught by WANG for the same intended purpose of providing electrical contact to the gate structure.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over KANG ‘970 as applied to claim 8 above, and further in view of HSU (US. Pub. No. 2022/0139777) of record.
KANG teaches the semiconductor device as described in claim 8 above including: the width of the edge portion of the first conductive pattern, measured in a horizontal direction substantially parallel to an upper surface of the substrate, is smaller than the thickness of the substrate of the central portion of the first conductive pattern, in a vertical direction substantially perpendicular to the upper surface.
Thus, KANG is shown to teach all the features of the claim with the exception of explicitly disclosing the width of the edge portion of the first conductive pattern decreases in the vertical direction from a portion of the edge portion of the first conductive pattern.
However, HSU teaches a semiconductor device including:
a width of an edge portion of first conductive pattern (301) decreases in the vertical direction from a portion of the edge portion of the first conductive pattern (301) at a height of the upper surface of the central portion of the first conductive pattern to an uppermost portion of the edge portion of the first conductive pattern (301). (See Figs. 5, 26).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the first conductive pattern of KANG having the width of the edge portion of a first conductive pattern decreases in the vertical direction from a portion of the edge portion of the first conductive pattern as taught by HSU for the same intended purpose of recessing the central portion of the first conductive pattern.
Response to Arguments
Applicant's arguments filed February 03, 202 have been fully considered but they are not persuasive.
Claim Rejected Under 35 USC § 102
With respect to claims 1 and 15, Applicant argues:
as previously noted in the response to the Office Action dated August 19, 2025, which was filed on November 17, 2025, the first conductive pattern 207LP of Kang has an upper surface which is flat. Fig. 6 of Kang, reproduced below for reference, clearly indicates that the central portion and the edge portion of the upper surface of the first conductive pattern 207LP are in the same level.
However, Kang, FIG. 6 below, shows that the surface of the first conductive pattern (207a-207LP) clearly not flat. The surface of the edge portion (207a_US) is clearly lower than that of the central portion (207LP_US).
Not that the “barrier film” is clearly a portion of the first conductive pattern.
Therefore, the limitations of claims 1 and 15 are met.
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Similarly, KANG, FIG. 7 below, shows that the surface of the first conductive pattern (207a-207LP) clearly not flat. The surface of edge portion (207a_US) is clearly higher than that of the central portion (207LP_US).
Therefore, the limitations of claim 8 are met.
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Claim Rejected Under 35 USC § 103
Applicant asserts that dependent claims 4, 12 and 18; 6 and 20; and 10 are patentable by virtual of their dependency.
Since claims 1, 8 and 15 are unpatentable for being anticipated by KANG, the rejection claims 4, 12 and 18; 6 and 20; and 10 for being unpatentable over KANG and CHAN, WANG and HSU, respectively, are maintained.
Conclusion
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/ANH D MAI/Primary Examiner, Art Unit 2893