DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 8-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/21/2025
Applicant’s election without traverse of Invention I, Device Embodiment 1, Device Modification A1 in the reply filed on 10/21/2025 is acknowledged.
Claim 6 reads on unelected Device Embodiment 1, Device Modification A2. Specifically, Claim 6 states “wherein the gate electrode includes, in a cross-section, a first portion whose width in the first direction increases from an upper portion of the gate electrode toward a lower portion closer to the substrate, and a second portion whose width in the first direction decreases below the first portion”. This modification is drawn to the non-elected species Device Modification A2 which is defined as “the lower portion of the gate structure is recessed leading to a smaller width of the gate structure at the bottom of the structure than the width of the upper portion of the gate structure” in the restriction requirement mailed on 08/21/2025. Therefore claim6 is withdrawn from further consideration, as being drawn to a nonelected species.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
PNG
media_image1.png
659
590
media_image1.png
Greyscale
Claim 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2019/0157444 A1, hereinafter Yang ‘444) in view of Lin et al. (US 2022/0130977 A1, hereinafter Lin ‘977), in view of the following arguments.
With respect to Claim 1 Yang ‘444 discloses a semiconductor device (Fig 1-5 and 26-38), comprising:
an active area (105, Fig 2, Para [0017]) that protrudes in a direction perpendicular (3rd direction as shown in Fig 2) to an upper surface (top of 100) of a substrate (100, Fig 2, Para [0017]) and that extends in a first direction (1st direction (horizontal) as shown in Fig 2) parallel to the upper surface (top of 100) of the substrate (100);
an element isolating area (130, Fig 2, Para [0017]) formed on the substrate (100) and around the active area (105);
a channel formed (124, Fig 2, Para [0023]) on an upper surface (top of 105) of the active area (105) and that extends in the first direction (1st direction as shown in Fig 1); a gate structure (310, Figs 1 and 2, Para [0028]) that surrounds at least two surfaces (sides and top as shown in Fig 2) of the channel (124) and that extends in a second direction (2nd direction as shown in Fig 2) perpendicular to the first direction (1st direction)(perpendicularity of 1st and 2nd directions disclosed in Fig 2);
a spacer (185, Fig 5, Para [0017]) formed on both sidewalls sides (sides of gate structure 310 as shown in Figs 1 and 5) of the gate structure (310) in the first direction (1st direction as shown in Fig 1); and
a source/drain layer (240, Fig 3, Para [0025]) in contact with both sidewalls (sides of gate structure 310 as shown in Figs 1 and 5) in the first direction (1st direction as shown in Fig 1) of the channel (124) and insulated from the gate structure (310) by the spacer (185)(disclosed in Fig 3),
But Lin ‘977 fails to explicitly disclose wherein the gate structure includes, in a cross-section, a first portion whose width in the first direction increases from an upper portion of the gate structure toward a lower portion closer to the substrate, and a second portion whose a width in the first direction remains the same or decreases below the first portion.
Nevertheless, in a related endeavor (Fig 1-12 of Lin ‘977), Line ‘977 teaches wherein the gate structure (1210, Fig 12 of Lin ‘977, Para [0054]) includes, in a cross-section (Fig 12 of Lin ‘977), a first portion (first portion above layer 320 as shown in annotated Fig 12 of Lin ‘977, hereinafter FP) whose width in the first direction (first direction shown in annotated Fig 12 of Lin ‘977) increases from an upper portion (upper portion shown in annotated Fig 12 of Lin ‘977) of the gate structure (1210) toward a lower portion (lower portion shown in annotated Fig 12 of Lin ‘977) closer to the substrate (202, Fig 4 of Lin ‘977 and annotated Fig 12 of Lin ‘977, Para [0018]), and a second portion (second portion from layer 320 as shown in annotated Fig 12 of Lin ‘977, hereinafter SP) whose a width in the first direction (first direction shown in annotated Fig 12 of Lin ‘977) remains the same or decreases below the first portion (FP)(width of second portion remains the same as shown in annotated Fig 12 of Lin ‘977).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lin ’977’s teaching of wherein the gate structure includes, in a cross-section, a first portion whose width in the first direction increases from an upper portion of the gate structure toward a lower portion closer to the substrate, and a second portion whose a width in the first direction remains the same or decreases below the first portion into Yang ‘444’s device. Yang ‘444 teaches a gate structure with slanted sidewalls. Lin ‘977 also teaches a gate structure with slanted (tapered) sidewalls. And Lin ‘977 teaches in Para [0014] that the tapered gates “address the line collapse and line twist defect issues by controlling the dummy gate profile ”. Therefore the ordinary artisan would have been motivated to modify Yang ‘444 in the manner set forth above, at least, because this using the shape taught by Lin ‘977 would improve the device yield of the manufacturing process.
As incorporated, the tapered gate structure of Lin ‘977 (shown in annotated Fig 12 of Lin ‘977) would be used in the shape of gate structure (310) of Yang ‘444.
With respect to Claim 2 Yang ‘444 as modified by Lin ‘977 discloses all limitations of the semiconductor device of claim 1, and Yang ‘444 further discloses wherein
the gate structure (310) surrounds one channel (124) and an upper surface (top of channel) and a sidewall (side of channel) of the channel (124) in the second direction (second direction shown in Fig 2)(Fig 2 and Para [0026] discloses gate electrode 300 of gate structure 310 (ref Para [0028]) over channel 124).
With respect to Claim 3 Yang ‘444 as modified by Lin ‘977 discloses all limitations of the semiconductor device of claim 1, and Yang ‘444 further discloses wherein
the gate structure (310) surrounds a plurality of channels (plurality of 124 as shown in Fig 2) and upper and lower surfaces and sidewalls (top, bottom and sides of channel) of at least some of the plurality of channels (plurality of 124 as shown in Fig 2) in the second direction (second direction as shown in Fig 2) (Fig 2 and Para [0026] discloses gate electrode 300 of gate structure 310 (ref Para [0028]) surrounds plurality of channels 124).
With respect to Claim 4 Yang ‘444 as modified by Lin ‘977 discloses all limitations of the semiconductor device of claim 1, and Yang ‘444 further discloses wherein
the gate structure (310) includes a gate insulating pattern (280, Fig 1, Para [0028]) and a gate electrode (300, Fig 1, Para [0028]).
PNG
media_image2.png
674
670
media_image2.png
Greyscale
With respect to Claim 5 Yang ‘444 as modified by Lin ‘977 discloses all limitations of the semiconductor device of claim 4, and Lin ‘977 further discloses wherein the gate electrode (1214, Fig 12 of Lin ‘977, Para [0054]) includes, in a cross-section (Fig 12 of Lin ‘977),
a first portion (first portion of gate electrode, as shown in annotated Fig 12_1 of Lin ‘977, hereinafter FPE) whose width (width of FPE as shown in annotated Fig 12_1 of Lin ‘977) in the first direction (first direction shown in annotated Fig 12_1 of Lin ‘977) increases from an upper portion (upper portion of 1214 shown in annotated Fig 12_1 of Lin ‘977) of the gate electrode (1214) toward a lower portion (upper portion of 1214 shown in annotated Fig 12_1 of Lin ‘977) closer to the substrate (202, Fig 4 of Lin ‘977 and annotated Fig 12_1 of Lin ‘977, Para [0018]), and
a second portion (second portion of gate electrode, as shown in annotated Fig 12_1 of Lin ‘977, hereinafter SPE) whose width (width of SPE as shown in annotated Fig 12_1 of Lin ‘977) in the first direction (first direction shown in annotated Fig 12_1 of Lin ‘977) remains the same below the first portion (FPE) (width of second portion of electrode 1214 remains the same as shown in annotated Fig 12_1 of Lin ‘977).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lin ’977’s further teaching of wherein the gate electrode includes, in a cross-section, a first portion whose width in the first direction increases from an upper portion of the gate electrode toward a lower portion closer to the substrate, and a second portion whose width in the first direction remains the same below the first portion into Yang ‘444’s device. Yang ‘444 teaches a gate structure with slanted sidewalls. Lin ‘977 also teaches a gate structure with slanted (tapered) sidewalls. And Lin ‘977 teaches in Para [0014] that the tapered gates “address the line collapse and line twist defect issues by controlling the dummy gate profile ”. Therefore the ordinary artisan would have been motivated to modify Yang ‘444 in the manner set forth above, at least, because this using the shape taught by Lin ‘977 would improve the device yield of the manufacturing process.
As incorporated, the gate electrode (1214) shape structure of Lin ‘977 (shown in annotated Fig 12_ of Lin ‘977) would be used as the gate electrode (300) of Yang ‘444 as modified by Lin ‘977.
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Allowable subject matter has been indicated because the closest prior art references of record, Yang et al. (US 2019/0157444 A1) and Lin et al. (US 2022/0130977 A1), either alone or in combination, fails to teach or fairly suggest the feature, “wherein the gate electrode includes, in a cross-section, a first portion whose width in the first direction increases from an upper portion of the gate electrode toward a lower portion closer to the substrate, and a second portion whose width in the first direction decreases and then increases below the first portion”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898