DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu(USPGPUB DOCUMENT: 2022/0084934, hereinafter Wu) in view of Zhang (USPGPUB DOCUMENT: 2022/0216134, hereinafter Zhang) and Boeck (USPGPUB DOCUMENT: 2010/0187657, hereinafter Boeck).
Re claim 10 Wu discloses in Fig 3 a method of fabricating a semiconductor device, the method comprising: providing a substrate; forming a first patterned conductive layer(top10/bottom10) on the substrate, the first patterned conductive layer(top10/bottom10) including a first capacitor plate[0039]; forming a first dielectric layer(top20/bottom20/40) over the first patterned conductive layer(top10/bottom10); forming a second patterned conductive layer(top10/bottom10) over the first dielectric layer(top20/bottom20/40), the second patterned conductive layer(top10/bottom10) including a second capacitor plate[0039]; and etching portions[0090] of the first dielectric layer(top20/bottom20/40) through the openings in the patterned photoresist layer to form air gaps(30) at the edges of the second capacitor plate[0039].
Wu does not discloses forming a patterned photoresist layer over the substrate, the patterned photoresist layer including openings at one or more edges of the second capacitor plate[0039]; such that, upon etching the portions of the first dielectric layer, at least a portion of a lower surface of the second capacitor plate is exposed through at least one of the air gaps.
Zhang discloses forming a patterned photoresist layer(201/202) over the substrate(1), the patterned photoresist layer including openings (undercut) at one or more edges
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Zhang to the teachings of Wu in order to increase the yield of electronic device products [0004, Zhang]. In doing so, the patterned photoresist layer including openings (undercut of Zhang) at one or more edges of the second capacitor plate[0039 of Wu];
Wu and Zhang does not discloses such that, upon etching the portions of the first dielectric layer, at least a portion of a lower surface of the second capacitor plate is exposed through at least one of the air gaps.
Boeck discloses such that, upon etching the portions of the first dielectric layer(414/416/418)[0031], at least a portion of a lower surface of the second capacitor plate(114/124) is exposed through at least one of the air gaps(112).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Boeck to the teachings of Wu in order to have one or more isolation cavities comprise cavities filled with a gas having a low dielectric constant (e.g., air) [0011, Boeck].
Re claim 11 Wu and Zhang and Boeck disclose the method of claim 10, wherein etching the portions of the first dielectric layer(top20/bottom20/40) through the openings in the patterned photoresist layer to form air gaps(30) at the edges of the second capacitor plate[0039] comprises: etching the portions of the first dielectric layer(top20/bottom20/40) through the openings in the patterned photoresist layer to form air gaps(30) at the edges of the second capacitor plate[0039].
Re claim 12 Wu and Zhang and Boeck disclose the method of claim 10, wherein the first patterned conductive layer(top10/bottom10) further includes a first conductive structure, and the second patterned conductive layer(top10/bottom10) further includes a second conductive structure and a conductive via that electrically couples the first conductive structure to the second conductive structure.
Re claim 13 Wu and Zhang and Boeck disclose the method of claim 12, further comprising: performing a patterned etch of the first dielectric layer(top20/bottom20/40) to form an opening in the first dielectric layer(top20/bottom20/40), wherein the conductive via is subsequently formed in the opening in the first dielectric layer(top20/bottom20/40).
Re claim 14 Wu and Zhang and Boeck disclose the method of claim 10, further comprising: after forming the air gaps(30) at the edges of the second capacitor plate[0039], etching exposed portions of the second capacitor plate[0039].
Re claim 15 Wu and Zhang and Boeck disclose the method of claim 14, wherein etching the exposed portions of the second capacitor plate[0039] causes edges and corners of the second capacitor plate[0039] to be rounded.
Re claim 16 Wu and Zhang and Boeck disclose the method of claim 14, further comprising: after forming the air gaps(30) at the edges of the second capacitor plate[0039], forming oxide on the exposed portions of the second capacitor plate[0039].
Re claim 17 Wu and Zhang and Boeck disclose the method of claim 14, wherein the air gaps(30) are non-overlapping with respect to one another and are disposed at corners of a lower surface of the second capacitor plate[0039].
Re claim 18 Wu and Zhang and Boeck disclose the method of claim 14, wherein the air gaps(30) are overlapping with respect to one another and are disposed at corners and edges of a lower surface of the second capacitor plate[0039].
Re claim 19 Wu and Zhang and Boeck disclose the method of claim 10, further comprising: before forming the first dielectric layer(top20/bottom20/40), forming a passivation layer over the substrate and the first patterned conductive layer(top10/bottom10).
Re claim 20 Wu and Zhang and Boeck disclose the method of claim 10, further comprising: removing the patterned photoresist layer; forming a second dielectric layer(top20/bottom20/40) over the substrate; and forming at least one opening in the second dielectric layer(top20/bottom20/40) to expose an upper surface of the second capacitor plate[0039].
Response to Arguments
Applicant’s arguments with respect to claim(s) 10-20 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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