DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 6/1/2026 have been fully considered but they are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Umeki (US PGPub 2024/0282846) in view of Shiraishi (US PGPub 2014/0003109).
Re claim 1: Umeki teaches (e.g. fig. 25) a semiconductor device comprising: a semiconductor substrate (substrate 31; e.g. paragraph 112) including a drift layer (n- drift layer 30; e.g. paragraph 111) of a first conductive type (n-type) between a first principal surface (upper surface 31; hereinafter “1PS”) and a second principal surface (lower surface of 31; hereinafter “2PS”) opposed to each other; an IGBT region (IGBT region 8; e.g. paragraph 80) and a diode region (diode region 9; e.g. paragraph 80) provided on the semiconductor substrate (31); and an emitter electrode (13) provided on the first principal surface (1PS) of the semiconductor substrate (31), wherein the IGBT region (8) includes a carrier accumulation layer (47) of the first conductive type (n-type) provided on the first principal surface (1PS) side of the drift layer (30); a base layer (p-type body 45; e.g. paragraph 131) of a second conductive type (p-type) provided on the first principal surface (1PS) side of the drift layer (30), an emitter layer (n-type emitter 46; e.g. paragraph 132) of the first conductive type (n-type) and a contact layer (p-type contact layer 49; e.g. paragraph 139) of the second conductive type (p-type) provided on the first principal surface (1PS) side of the base layer (45), a plurality of active trenches (trench 73; e.g. paragraph 142) penetrating through the base layer (47) and the emitter layer (46) from the first principal surface (1PS), a gate electrode (41) provided inside the active trenches (73) via a gate insulating film (40), and a collector layer (P+ collector 34; e.g. paragraph 113) of the second conductive type (p-type) provided on the second principal surface (2PS) side of the drift layer (30), wherein the diode region (9) includes an anode layer (anode region 62; e.g. paragraph 316) of the second conductive type (p-type) provided on the first principal surface (1PS) side of the drift layer (30), a plurality of diode trenches (trench for cell separating structure 63; e.g. paragraph 347) provided from the first principal surface (1PS) to the anode layer (62), a diode electrode (66) provided inside the diode trenches (63) via a diode insulating film (65), and a cathode layer (N+ cathode 61; e.g. paragraph 261) of the first conductive type (n-type) provided on the second principal surface (2PS) side of the drift layer (30), wherein a depth of the anode layer (62) is deeper than a depth of the diode trenches (63), and diode trenches (63) contact semiconductor material (p-type region of 62) of the second conductivity type (p-type) at the first principal surface (1PS).
Umeki is silent as to explicitly teaching an implanted electrode provided inside the active trenches via the gate insulating film and positioned on the second principal surface side of the gate electrode.
Shiraishi teaches (e.g. fig. 7) the IGBT region (IGBT region shown in fig. 7; e.g. paragraph 53) includes an implanted electrode (embedded electrode 118 connected to the emitter electrode 114; e.g. paragraph 47) provided inside the active trenches (gate trench 117; e.g. paragraph 37) via the gate insulating film (109) and positioned on the second principal surface side (bottom side of gate 110) of the gate electrode (110).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the embedded electrode as taught by Shiraishi in the device of Umeki in order to have the predictable result of improving device performance by improving on-resistance and improving controllability of the dv/dt while maintaining the breakdown voltage (see paragraph 42 of Shiraishi).
Re claim 16: Umeki teaches the semiconductor device according to claim 1, wherein the diode trenches (63) contact the anode layer (62) at the first principal surface (1PS).
Re claim 17: Umeki teaches the semiconductor device according to claim 1, wherein a depth of an entirety of the anode layer (62) between two of the diode trenches (63) is deeper than the depth of the diode trenches (63).
Re claim 18: Umeki teaches the semiconductor device according to claim 1, wherein a depth of an entirety of the anode layer (62) is deeper than the depth of the diode trenches (63).
Claim(s) 2 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Umeki in view of Shiraishi as applied to claim 1 above, and further in view of Soneda et al. (US PGPub 2021/0091216; hereinafter “Soneda”).
Re claim 2: Umeki in view of Shiraishi teaches the semiconductor device according to claim 1, wherein the implanted electrode (118 of Shiraishi) is insulated from the gate electrode (110 of Shiraishi) and is electrically connected to the emitter electrode (118 of Shiraishi is connected to the emitter 114; e.g. paragraph 47),
Umeki in view of Shiraishi is silent as to explicitly teaching the diode electrode is electrically connected to the emitter electrode.
Soneda teaches (e.g. fig. 1) the diode electrode (diode trench electrode 13c; e.g. paragraph 36) is electrically connected to the emitter electrode (13c electrically connected to emitter electrode 9).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the connection method for the diode trench electrode as taught by Soneda in the device of Umeki in view of Shiraishi in order to have the predictable result of using a connection method which improves device performance by accumulating carriers and improves switching speed.
Re claim 15: Umeki in view of Shiraishi and Soneda teaches the semiconductor device according to claim 1, wherein the semiconductor substrate (1 of Soneda) is formed of a wide-bandgap semiconductor (Silicon Carbide used to improve breakdown voltage and current capacity; e.g. paragraph 69 of Soneda).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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