DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of device embodiment 1 as shown in fig. 1,2 (claims 1, 2, 15 readable thereon, claims 3-14 withdrawn) in the reply filed on 12/15/2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saikaku et al. (US PGPub 2012/0025874; hereinafter “Saikaku”) in view of Shiraishi (US PGPub 2014/0003109).
Re claim 1: Saikaku teaches (e.g. fig. 41) a semiconductor device comprising: a semiconductor substrate (substrate of device 100; hereinafter “S”) including a drift layer (n- drift layer 102; e.g. paragraph 263) of a first conductive type (n-type) between a first principal surface (upper surface of device 100; hereinafter “1PS”) and a second principal surface (lower surface of device 100; hereinafter “2PS”) opposed to each other; an IGBT region (IGBT region above collector 141; hereinafter “IR”) and a diode region (diode region above anode 142; hereinafter “DR”) provided on the semiconductor substrate (S); and an emitter electrode (109) provided on the first principal surface (1PS) of the semiconductor substrate (S), a base layer (p-type body 103; e.g. paragraph 264) of a second conductive type (p-type) provided on the first principal surface (1PS) side of the drift layer (102), an emitter layer (n-type emitter 104; e.g. paragraph 263) of the first conductive type (n-type) and a contact layer (p-type contact layer 105; e.g. paragraph 234) of the second conductive type (p-type) provided on the first principal surface (1PS) side of the base layer (103), a plurality of active trenches (trench for gate 108a; hereinafter “AT”) penetrating through the base layer (103) and the emitter layer (104) from the first principal surface (1PS), a gate electrode (108a) provided inside the active trenches (AT) via a gate insulating film (107), and a collector layer (P+ collector 141; e.g. paragraph 263) of the second conductive type (p-type) provided on the second principal surface (2PS) side of the drift layer (102), wherein the diode region (DR) includes an anode layer (103a) of the second conductive type (p-type) provided on the first principal surface (1PS) side of the drift layer (102), a plurality of diode trenches (trench for diode gate 108b; hereinafter “DT”) provided from the first principal surface (1PS) to the anode layer (103a), a diode electrode (108b) provided inside the diode trenches (DT) via a diode insulating film (107 in DT), and a cathode layer (N+ cathode 142; e.g. paragraph 263) of the first conductive type (n-type) provided on the second principal surface (2PS) side of the drift layer (102), wherein a depth of the anode layer (103a) is deeper than a depth of the diode trenches (DT).
Saikaku is silent as to explicitly teaching wherein the IGBT region includes a carrier accumulation layer of the first conductive type provided on the first principal surface side of the drift layer; an implanted electrode provided inside the active trenches via the gate insulating film and positioned on the second principal surface side of the gate electrode.
Shiraishi teaches (e.g. fig. 7) the IGBT region (IGBT region shown in fig. 7; e.g. paragraph 53) includes a carrier accumulation layer (n-type layer 123; e.g. paragraph 53) of the first conductive type (n-type) provided on the first principal surface (upper side of drift region 104) side of the drift layer (drift layer 104; e.g. paragraph 53); an implanted electrode (embedded electrode 118 connected to the emitter electrode 114; e.g. paragraph 47) provided inside the active trenches (gate trench 117; e.g. paragraph 37) via the gate insulating film (109) and positioned on the second principal surface side (bottom side of gate 110) of the gate electrode (110).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the carrier accumulation layer and embedded electrode as taught by Shiraishi in the device of Saikaku in order to have the predictable result of improving device performance by improving on-resistance.
Claim(s) 2 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saikaku in view of Shiraishi as applied to claim 1 above, and further in view of Soneda et al. (US PGPub 2021/0091216; hereinafter “Soneda”).
Re claim 2: Saikaku in view of Shiraishi teaches the semiconductor device according to claim 1, wherein the implanted electrode (118 of Shiraishi) is insulated from the gate electrode (110 of Shiraishi) and is electrically connected to the emitter electrode (118 of Shiraishi is connected to the emitter 114; e.g. paragraph 47),
Saikaku in view of Shiraishi is silent as to explicitly teaching the diode electrode is electrically connected to the emitter electrode.
Soneda teaches (e.g. fig. 1) the diode electrode (diode trench electrode 13c; e.g. paragraph 36) is electrically connected to the emitter electrode (13c electrically connected to emitter electrode 9).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the connection method for the diode trench electrode as taught by Soneda in the device of Saikaku in view of Shiraishi in order to have the predictable result of using a connection method which improves device performance by accumulating carriers and improves switching speed.
Re claim 15: Saikaku in view of Shiraishi and Soneda teaches the semiconductor device according to claim 1, wherein the semiconductor substrate (1 of Soneda) is formed of a wide-bandgap semiconductor (Silicon Carbide used to improve breakdown voltage and current capacity; e.g. paragraph 69 of Soneda).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898