DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in China on 02/15/2022. It is noted, however, that applicant has not filed a certified copy of the 202210138486.X application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-5 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Furuya et al (JP2020147497A), an English computer translation (CT) is provided, in view of Nakamura et al (“Ultrahigh-quality silicon carbide single crystals.”) and Harada et al (US 2013/0071643).
Furuya et al teaches a monocrystalline SiC substrate (CT [0062], [0112]-[0114]), comprising a first surface and a second surface, wherein: the first surface comprises pinning regions and a device region; each of the pinning regions 22 is configured to provide a potential well which is capable to attract dislocations from a region surrounding said pinning region (Fig 6-9 and 14, CT [0016], [0069]-[0078] teaches spiral dislocation initiation point 22 can suppress the generation of heteromorphs and defects associated with the outflow of crystal dislocations; and spiral dislocations decrease in density because dislocations with opposite signs attract and bond with each other, causing them to disappear); the device region is configured to provide a part of the monocrystalline SiC substrate for manufacturing a semiconductor device; the device region 323 is surrounded by the pinning regions; and a density of dislocations in a central portion of the device region is smaller than a density of dislocations in an edge of the device region due to the pinning regions (Fig 6-9 and 14, CT [0019]-[0040], [0109] teaches a semiconductor device has an active region driven as a device and an outer peripheral region surrounding the active region, and a spiral dislocation density in the outer peripheral region is larger than that in the active region; introducing helical dislocations along the dicing line during chip formation to improve the actual quality of the semiconductor device obtained after dicing). Furuya et al teaches a plurality of first helical dislocation generation lines, and the plurality of first helical dislocation generation lines may be arranged periodically at predetermined intervals and a plurality of the second helical dislocation generation lines may be arranged periodically at predetermined intervals, and the second helical dislocation generation line extending in a second direction intersecting the first direction, and the facet growth region may have a second helical dislocation cluster extending from the second helical dislocation generation region in the SiC growth direction. (CT [0022]-[0033]).
In regards to “each of the pinning regions is configured to provide a potential well which is capable to attract dislocations from a region surrounding said pinning region under a thermal driving force,” Furuya et al teaches as growth progresses spiral dislocations decrease in density because dislocations with opposite signs attract and bond with each other, causing them to disappear (CT [0016]); and SiC growth occurs at a growth temperature; therefore, attraction from a thermal driving force would be expected.
Furuya et al teaches the SiC seed is cut out from another SiC single crystal that has already been produced; it is preferable that the SiC single crystal from which these SiC seeds are cut is of high quality; and high-quality SiC single crystals with extremely few defects can be obtained by methods such as the RAF method (CT [0005], [0112]-[0113]). Furuya et al does not explicitly teach a density of dislocations in the device region is less than 3000/cm2, a density of threading screw dislocations in the device region is less than 500/cm2, a density of threading edge dislocations in the device region is less than 1500/cm2, a density of basal plane dislocations in the device region is less than 1000/cm2.
In a method of making SiC crystal using RAF, Nakamura et al teaches a repeated a-face (RAF) growth process, wherein the EPDs decrease exponentially with increase in the repeat count of a-face growth and the dislocations in the SiC crystal are effectively eliminated by the RAF growth; and the averaged EPD of the RAF growth crystal was about 250 cm-2, which is low by three orders of magnitude than that of conventional grade SiC substrate (pg 1009-1011; Fig 3). Nakamura et al teaches EPDs have been considered to be the density of dislocations exposed at the substrate surface (pg 1012). RAF is a sublimation growth method.
In a method of measuring dislocation density of SiC substrates, Harada et al (US 2013/0071643) teaches micropipe density, threading screw dislocation density, threading edge dislocation density, and basal plane dislocation density can be measured by performing molten KOH etching or gas etching on silicon carbide substrate, and then observing etch pits formed in the surface of silicon carbide substrate ([0048], [0139]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify Furuya et al by using the SiC single crystal formed by sublimation (RAF) taught by Nakamura et al having a dislocation density of less than 3000/ cm2, i.e. 250/ cm2, to produce devices having fewer defects and higher quality, wherein the dislocation density measured by etch pit density would include threading screw dislocation density, threading edge dislocation density, and basal plane dislocation density, as taught by Harada et al; therefore, would overlap the claimed threading dislocation is less than 500/cm2, a threading edge dislocations is less than 1500/cm2, and a density of basal plane dislocations is less than 1000/cm2.
Referring to claim 2, the combination of Furuya et al, Nakamura et al and Harada et al teaches the pinning regions 22 are equally separated on the first surface, and the pinning regions which surround the device region are equally separated along a peripheral of the device region (Furuya See Fig 7(b), Fig 10 and Fig 14 which shows the pinning regions; CT [0079], [0091] which teaches shape of the region enclosed by the spiral dislocations is a square).
Referring to claim 3, the combination of Furuya et al, Nakamura et al and Harada et al all of the limitations of claim 3, as discussed above, except each of the pinning regions is a square of which a side length ranges from 40 mm to 100 mm; and the device region is a rectangular, and four of the pinning regions are disposed at four vertices, respectively of the device region.
Furuya et al teaches the shape of the region enclosed by a spiral dislocation generation line 21 is a square, and may be a rectangle or other shape (CT [0091]). Furuya et al also teaches the helical dislocation initiation point (pinning region) is artificially created by machining, it will be about 100 μm (CT [0084]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the combination of Furuya et al, Nakamura et al and Harada et al to have each of the pinning regions is a square of which a side length ranges from 40 mm to 100 mm which overlaps the size expected for the helical dislocation initiation point (pinning region) taught by Furuya et al, overlapping ranges are prima facie obvious; and the device region is a rectangular, and four of the pinning regions are disposed at four vertices, respectively of the device region because Furuya et al suggests other shapes such as rectangles, and changes in shape are prima facie obvious (MPEP 2144.04), to produce a device region having reduced defects having a desired shape.
Referring to claim 4, the combination of Furuya et al, Nakamura et al and Harada et al teaches the shape of the region enclosed by a spiral dislocation generation line 21 is a square (Furuya CT [0091]), which clearly suggests a device region is another square.
Referring to claim 5, the combination of Furuya et al, Nakamura et al and Harada et al teaches a semiconductor device is formed using the obtained SiC wafer from the device fabrication region 323; the manufacturing process for semiconductor devices can utilize known methods (Furuya Fig 14; CT [0124]-[0128]), which clearly suggests the device region is utilized for manufacturing one or more semiconductor devices.
Referring to claims 17-18, the combination of Furuya et al, Nakamura et al and Harada et al teaches a semiconductor device is formed using the obtained SiC wafer from the device fabrication region 323; the manufacturing process for semiconductor devices can utilize known methods (Furuya Fig 14; CT [0124]-[0128]), which reads on a semiconductor device, and an effective region of the device is manufactured from the central portion of the device region, and the effective region is a region of the device on which voltage is applied.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5 and 17-18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 07/01/2026 have been fully considered but they are not persuasive.
Applicant’s argument that the prior art does not teach the pinning region each of the pinning regions is configured to provide a potential well which is capable to attract dislocations from a region surrounding said pinning region under a thermal driving force is noted but not found persuasive. Furuya et al teaches as growth progresses spiral dislocations decrease in density because dislocations with opposite signs attract and bond with each other, causing them to disappear (CT [0016]); and SiC growth occurs at a growth temperature; therefore, attraction from a thermal driving force would be expected.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kamata et al (US 2021/0108334) teaches In a single crystal wafer manufactured by an RAF technique of the sublimation method in which a crystal growth is repeated while rotating the orientation of a seed crystal by 90° to discharge the dislocations, the dislocations may be possibly reduced to the same extent as the wafer of the embodiment described above; and the wafer embodiment above has a screw dislocation density of 500 dislocations/cm2 or less; a dislocation density of 3500 dislocations/cm2 or less; and an edge dislocation density of 3000 dislocations/cm2 or less ([0034]-[0045])
Nakabayashi et al (US 2016/0215414) teaches a SiC single crystal wafer, which is manufactured from a SiC single crystal ingot grown by the sublimation-recrystallization method, and which brings about high device performance and high device manufacture yield when used as a wafer for manufacturing a device, wherein the SiC single crystal wafer has, in a surface thereof, a basal plane dislocation density of 1,000 dislocations per cm2 or less, a threading screw dislocation density of 500 dislocations per cm2or less, and a Raman index of 0.2 or less with few defects (Abstract).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW J SONG whose telephone number is (571)272-1468. The examiner can normally be reached Monday-Friday 10AM-6PM.
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MATTHEW J. SONG
Examiner
Art Unit 1714
/MATTHEW J SONG/ Primary Examiner, Art Unit 1714
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