DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I, claims 1-9 and 17-18 in the reply filed on 12/23/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 10-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/23/2025.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in China on 02/15/2022. It is noted, however, that applicant has not filed a certified copy of the 202210138486.X application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 17-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Furuya et al (JP2020147497A), an English computer translation (CT) is provided.
Furuya et al teaches a monocrystalline SiC substrate (CT [0062], [0112]-[0114]), comprising a first surface and a second surface, wherein: the first surface comprises pinning regions and a device region; each of the pinning regions 22 is configured to provide a potential well which is capable to attract dislocations from a region surrounding said pinning region (Fig 6-9 and 14, CT [0016], [0069]-[0078] teaches spiral dislocation initiation point 22 can suppress the generation of heteromorphs and defects associated with the outflow of crystal dislocations; and spiral dislocations decrease in density because dislocations with opposite signs attract and bond with each other, causing them to disappear); the device region is configured to provide a part of the monocrystalline SiC substrate for manufacturing a semiconductor device; the device region 323 is surrounded by the pinning regions; and a density of dislocations in a central portion of the device region is smaller than a density of dislocations in an edge of the device region due to the pinning regions (Fig 6-9 and 14, CT [0019]-[0040], [0109] teaches a semiconductor device has an active region driven as a device and an outer peripheral region surrounding the active region, and a spiral dislocation density in the outer peripheral region is larger than that in the active region; introducing helical dislocations along the dicing line during chip formation to improve the actual quality of the semiconductor device obtained after dicing). Furuya et al teaches a plurality of first helical dislocation generation lines, and the plurality of first helical dislocation generation lines may be arranged periodically at predetermined intervals and a plurality of the second helical dislocation generation lines may be arranged periodically at predetermined intervals, and the second helical dislocation generation line extending in a second direction intersecting the first direction, and the facet growth region may have a second helical dislocation cluster extending from the second helical dislocation generation region in the SiC growth direction. (CT [0022]-[0033]).
Referring to claim 2, Furuya et al teaches the pinning regions 22 are equally separated on the first surface, and the pinning regions which surround the device region are equally separated along a peripheral of the device region (See Fig 7(b), Fig 10 and Fig 14 which shows the pinning regions; CT [0079], [0091] which teaches shape of the region enclosed by the spiral dislocations is a square).
Referring to claims 17-18, Furuya et al teaches a semiconductor device is formed using the obtained SiC wafer from the device fabrication region 323; the manufacturing process for semiconductor devices can utilize known methods (Fig 14; CT [0124]-[0128]), which reads on a semiconductor device, and an effective region of the device is manufactured from the central portion of the device region, and the effective region is a region of the device on which voltage is applied.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Furuya et al (JP2020147497A), an English computer translation (CT) is provided, as applied to claims 1-2 above.
Furuya et al teaches all of the limitations of claim 3, as discussed above, except each of the pinning regions is a square of which a side length ranges from 40 mm to 100 mm; and the device region is a rectangular, and four of the pinning regions are disposed at four vertices, respectively of the device region.
Furuya et al teaches the shape of the region enclosed by a spiral dislocation generation line 21 is a square, and may be a rectangle or other shape (CT [0091]). Furuya et al also teaches the helical dislocation initiation point (pinning region) is artificially created by machining, it will be about 100 μm (CT [0084]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify Furuya et al each of the pinning regions is a square of which a side length ranges from 40 mm to 100 mm which overlaps the size expected for the helical dislocation initiation point (pinning region) taught by Furuya et al, overlapping ranges are prima facie obvious; and the device region is a rectangular, and four of the pinning regions are disposed at four vertices, respectively of the device region because Furuya et al suggests other shapes such as rectangles, and changes in shape are prima facie obvious (MPEP 2144.04), to produce a device region having reduced defects having a desired shape.
Referring to claim 4, Furuya et al teaches the shape of the region enclosed by a spiral dislocation generation line 21 is a square (CT [0091]), which clearly suggests a device region is another square.
Referring to claim 5, Furuya et al teaches a semiconductor device is formed using the obtained SiC wafer from the device fabrication region 323; the manufacturing process for semiconductor devices can utilize known methods (Fig 14; CT [0124]-[0128]), which clearly suggests the device region is utilized for manufacturing one or more semiconductor devices.
Claim(s) 6-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Furuya et al (JP2020147497A), an English computer translation (CT) is provided, as applied to claim 1-5 above, and further in view of Shinya et al (US 2018/0298519).
Furuya et al teaches all of the limitations of claim 6, as discussed above, except the density of dislocations in the device region is less than 3000/cm2.
In a method of making a SiC single crystal, Shinya et al teaches a SiC single crystal of high homogeneity and quality is obtained, which is reduced in threading screw dislocations, threading edge dislocations, basal plane dislocations, micropipes, and stacking faults (Abstract). Shinya et al teaches preparing a SiC single crystal in which the densities of treading screw dislocations (TSDs), threading edge dislocations (TEDs), basal plane dislocations (BPDs), micropipes (MPs) and stacking faults are not more than 10/ cm2, specifically at least one of these densities is substantially zero (0/cm2), more specifically all these densities are substantially zero (0/ cm2), compared to the RAF sublimation process which has a total dislocation density of about 3000/cm2 (Fig 3; [0035]-[0064]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify Furuya et al by using the SiC single crystal taught by Shinya et al having a dislocation density of less than 3000/ cm2, i.e. 0/ cm2, to produce devices having fewer defects and higher quality (Shinya [0030]).
Referring to claim 7-9, the combination of Furuya et al and Shinya et al teaches densities of treading screw dislocations (TSDs), threading edge dislocations (TEDs), basal plane dislocations (BPDs), micropipes (MPs) and stacking faults are not more than 10/ cm2, specifically at least one of these densities is substantially zero (0/cm2), more specifically all these densities are substantially zero (0/ cm2) (Shinya [0035]-[0064]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2021/0108334 teaches a SiC single crystal wafer has a dislocation density is 1750 dislocation/cm2 or less, a edge dislocation density is 1500 dislocations/cm2 or less, a screw dislocation density is 500 dislocations/cm2 or less ([0086]-[0092]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW J SONG whose telephone number is (571)272-1468. The examiner can normally be reached Monday-Friday 10AM-6PM.
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MATTHEW J. SONG
Examiner
Art Unit 1714
/MATTHEW J SONG/Primary Examiner, Art Unit 1714
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