DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1, and 3-14 remain pending in this application. Acknowledgement is made of the amendment received 03/02/2026. Claim 2 is canceled, and claims 1, 4, 6, 7, 11, 13, and 14 are amended.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Uehara et al (US 20170271442 A1, as cited in IDS dated 08/11/2025, hereafter Uehara) in view of Yamaguchi et al (US 20080038850 A1, as cited in IDS dated 08/11/2025, hereafter Yamaguchi), Feng et al (US 20150050751 A1, hereafter Feng) and Kobayashi et al (US 20210183995 A1, hereafter Kobayashi).
Regarding claim 1, Uehara teaches: A manufacturing method for a silicon carbide semiconductor device (Uehara ¶0082-0094, figs 1-9), the manufacturing method comprising the steps of:
(a) forming a drift layer (Uehara 128a-c) of a first conductivity type (Uehara ¶0083, 0086, 0089, “n type”) on a silicon carbide semiconductor substrate (Uehara 124) of the first conductivity type (Uehara ¶0082, “n+ type”) through epitaxial growth (Uehara ¶0083, 0086, 0089, 0092, “128a is formed by epitaxial growth”)(Uehara figs 2, 4, 6);
(c) forming an ion implantation mask (Uehara 150a-c, ¶0084, 0087, 0090, 0093) on the drift layer (Uehara fig 3), the ion implantation mask including a plurality of first openings being periodically provided (Uehara figs 3, 5, 7, 9);
(d) implanting impurity ions (Uehara ¶0084, 0087, 0090, 0093, “Al”) of a second conductivity type (Uehara ¶0084, 0087, 0090, 0093, “Al… as the p type impurities”) through the plurality of first openings (Uehara figs 3, 5, 7, 9), forming a plurality of second pillar regions (Uehara 30, 32, figs 1, 9) of the second conductivity type (Uehara ¶0084, 0087, 0090, 0093, “p type region 30c … p type region 32c”) in the drift layer (Uehara ¶0085, 0088, 0091, 0093, figs 3, 5, 7, 9), and turning the drift layer between the plurality of second pillar regions into a first pillar region (Uehara 28, under a broadest reasonable interpretation of “pillar region”, figs 1, 9) of the first conductivity type (Uehara ¶0085, 0088, 0091, 0093, “n type region 28d”, figs 3, 5, 7, 9);
(e) forming an epitaxial layer (Uehara 128d) of the first conductivity type (Uehara ¶0092, “n type fifth silicon carbide layer 128d”) on the drift layer through epitaxial growth (Uehara ¶0092, “128d is formed by epitaxial growth”, fig 8); and
(f) forming a plurality of unit cells of a transistor (Uehara 100, ¶0094) in the epitaxial layer (Uehara fig 9).
Uehara does not teach: (b) measuring impurity concentration of the drift layer;
wherein the step (d) comprises performing feedforward control on an ion implantation amount of the impurity ions so that there is a positive correlation with measurement results of the step (b),
the method further comprising:
(g) measuring film thickness of the drift layer, between the step (b) and the step (c), wherein
the step (d) further comprises performing feedforward control on ion implantation energy for the impurity ions so that there is a positive correlation with measurement results of the step (g).
Yamaguchi, in the same field of endeavor of semiconductor device manufacturing, teaches: (a) providing a drift layer (Yamaguchi 10, ¶0128, “a substrate (10) of the first conductivity type to become the first layer (2) of the first conductivity type as a drift region”) of a first conductivity type (Yamaguchi ¶0044, “substrate of first conductivity type”);
(b) measuring impurity concentration of the drift layer (Yamaguchi ¶0044, “impurity concentration of the N type substrate 10 doped with the impurity is measured”);
(d) forming a second pillar region (Yamaguchi 12, ¶0048, under a broadest reasonable interpretation of “pillar region”, figs 2A-2F) of a second conductivity type (Yamaguchi, ¶0048, “P type”) in the drift layer (Yamaguchi ¶0048, figs 2A-2F), and turning the drift layer into a plurality of first pillar regions (Yamaguchi ¶0048, under a broadest reasonable interpretation of “pillar regions”, figs 2A-2F) of the first conductivity type (Yamaguchi, ¶0048, figs 2A-2F)(similar to step (d) of Uehara);
wherein the step (d) comprises performing feedforward control on an amount of the impurity ions so that there is a positive correlation with measurement results of the step (b)(Yamaguchi ¶0048, “using the concentration of the N type substrate 10 measured at the step shown in FIG. 2A, the P type epitaxial layer 12 is formed while the concentration of this P type epitaxial layer 12 is being adjusted”, under a broadest reasonable interpretation of “feedforward control”, Yamaguchi is at least using parameters from an earlier process step to adjust process conditions in a subsequent step, before the subsequent step is performed. Further, there is positive correlation between the results of the measurement performed by Yamaguchi, and the resultant concentration of the P type epitaxial layer, specifically, in order to achieve charge balance stated by Yamaguchi, if the concentration of N type goes up or down, so must that of the P type epitaxial layer).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Uehara to include the measuring and feedforward control of Yamaguchi, such that “the step (d) comprises performing feedforward control on an ion implantation amount of the impurity ions so that there is a positive correlation with measurement results of the step (b)”, in order to hold constant a ratio between the first and second type conductivity ions during manufacturing, thereby providing a charge balance in the drift layer to suppress impurity migration and/or outward diffusion (Yamaguchi ¶0048-0049).
Uehara in view of Yamaguchi does not teach: the method further comprising:
(g) measuring film thickness of the drift layer, between the step (b) and the step (c), wherein
the step (d) further comprises performing feedforward control on ion implantation energy for the impurity ions so that there is a positive correlation with measurement results of the step (g).
Feng, in the same field of endeavor of semiconductor device manufacturing, teaches: (g) measuring film thickness of a layer (Feng ¶0040), before a step of ion implantation (Feng ¶0054), wherein a step (d) further comprises performing feedforward control on ion implantation energy (Feng ¶0012, 0041, “The parameter of the ion implantation process is, for instance, energy”) for the impurity ions with measurement results of the step (g)(Feng ¶0041, 0042).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Uehara in view of Yamaguchi to include measuring a drift layer thickness before ion implantation, such that it is “between the step (b) and the step (c)”, and to adjust the implantation energy of the ion implantation, such that “the step (d) further comprises performing feedforward control on ion implantation energy for the impurity ions with measurement results of the step (g)”, in order to improve device uniformity by compensating for drift layer thickness variations (Feng ¶0064).
Uehara in view of Yamaguchi and Feng does not explicitly teach: a positive correlation with measurement results of the step (g).
Kobayashi, in the same field of endeavor of semiconductor device manufacturing, teaches: adjusting ion implantation energy so that there is a positive correlation with a drift layer thickness (Kobayashi ¶0045, 0048, “acceleration energy is assumed to be in a range from 60 keV to 700 keV”, “this number is dependent on the film thicknesses of the parallel pn structures 33, the acceleration energy of the ion implantations”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify step (g) of Uehara in view of Yamaguchi and Feng to have a positive correlation between ion implantation energy and a drift layer thickness, and such that “the step (d) further comprises performing feedforward control on ion implantation energy for the impurity ions so that there is a positive correlation with measurement results of the step (g)”, in order to ensure that proper implantation depth and charge balance is maintained despite epitaxial film thickness variations (Kobayashi ¶0048, Yamaguchi ¶0134).
Regarding claim 3, Uehara in view of Yamaguchi, Feng, and Kobayashi teaches: The manufacturing method for the silicon carbide semiconductor device according to claim 1.
Uehara in view of Yamaguchi, Feng, and Kobayashi does not explicitly teach: further comprising (h) measuring average opening width of the plurality of first openings of the ion implantation mask, between the step (c) and the step (d), wherein the step (d) further comprises performing feedforward control on the ion implantation amount so that there is a negative correlation with measurement results of the step (h).
Yamaguchi further teaches: (h) measuring a width of an opening (Yamaguchi 11) before forming a pillar of a second conductivity type (Yamaguchi 12, 3, under a broadest reasonable interpretation of “pillar”)(Yamaguchi ¶0134), and
adjusting a concentration of impurity ions to have a negative correlation with measurement results of the step (h)(Yamaguchi ¶0148, 0149, in order to maintain charge balance, if width increases, impurity concentration must decrease, therefore the concentration of impurity ions has a negative correlation to the width measurement).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Uehara in view of Yamaguchi, Feng, and Kobayashi to include a step of “(h) measuring average opening width of the plurality of first openings of the ion implantation mask, between the step (c) and the step (d)”, and to adjust the impurity concentration based on the measurement, such that “the step (d) further comprises performing feedforward control on the ion implantation amount so that there is a negative correlation with measurement results of the step (h)”, in order to maintain a charge balance relationship, thereby holding constant a ratio between the first and second type conductivity ions during manufacturing, thereby suppressing impurity migration and/or outward diffusion (Yamaguchi ¶0048-0049).
Regarding claim 6, Uehara in view of Yamaguchi, Feng, and Kobayashi teaches: The manufacturing method for the silicon carbide semiconductor device according to claim 1.
Uehara in view of Yamaguchi, Feng, and Kobayashi does not explicitly teach: wherein the transistor is a trench transistor including a trench gate being provided in the epitaxial layer,
the step (f) comprises forming an electric field protection region of the second conductivity type at a bottom portion of the trench gate, the electric field protection region having an impurity concentration of the second conductivity type that is higher than an impurity concentration of the second conductivity type of the plurality of second pillar regions, and
the electric field protection region is connected to the plurality of second pillar regions.
Uehara further teaches: a trench gate type transistor (Uehara ¶0112).
Kobayashi further teaches: a transistor is a trench transistor (Kobayashi 301, ¶0060) including a trench gate (Kobayashi 20) being provided in an epitaxial layer (Kobayashi 32, ¶0048, figs 6-9)(Kobayashi ¶0051, fig 9),
a step (f) comprises forming an electric field protection region (Kobayashi 3, ¶0063, “mitigating electric field concentration”) of the second conductivity type (Kobayashi ¶0063, “p+-type”) at a bottom portion of the trench gate (Kobayashi ¶0063, “near the bottoms of the trenches 23”, fig 9), the electric field protection region having an impurity concentration of a second conductivity type (Kobayashi ¶0063, “p+-type”, fig 9) higher than an impurity concentration of the second conductivity type (Kobayashi ¶0048, “p-type”, fig 9) of a plurality of second pillar regions (Kobayashi 30, ¶0078, “p-type column regions 30”)(Kobayashi fig 9, ¶0031), and
the electric field protection region is connected to the plurality of second pillar regions (Kobayashi, ¶0062, fig 9).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Uehara in view of Yamaguchi, Feng, and Kobayashi to implement the device as a trench gate type transistor, as taught by Kobayashi and Uehara, in order to reduce on resistance of a device (Kobayashi ¶0071), and such that “the electric field protection region having an impurity concentration of the second conductivity type that is higher than an impurity concentration of the second conductivity type of the plurality of second pillar regions”, in order to suppress electric field increases at the trench bottoms, thereby suppressing gate insulation breakdown (Kobayashi ¶0064-0065), and/or to increase source-drain capacitance, thereby suppressing hard recovery (Kobayashi ¶0076).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Uehara et al (US 20170271442 A1, as cited in IDS dated 08/11/2025, hereafter Uehara) in view of Yamaguchi et al (US 20080038850 A1, as cited in IDS dated 08/11/2025, hereafter Yamaguchi), Feng et al (US 20150050751 A1, hereafter Feng) and Kobayashi et al (US 20210183995 A1, hereafter Kobayashi), as applied to claim 1, and further in view of Saito et al (US 20050280086 A1, hereafter Saito).
Regarding claim 4, Uehara in view of Yamaguchi, Feng, and Kobayashi teaches: The manufacturing method for the silicon carbide semiconductor device according to claim 1, wherein in the step (d), ion implantation of the impurity ions is performed (Uehara ¶0084, 0087, 0090, 0093, “aluminum (Al) is ion-implanted”, figs 3-7).
Uehara in view of Yamaguchi, Feng, and Kobayashi does not explicitly teach: ion implantation of the impurity ions is performed, with predetermined two implantation conditions being set for width of unevenness of the impurity concentration of the drift layer.
Yamaguchi further teaches: adjusting a p-type concentration based on a width measurement (Yamaguchi ¶0048, 0134), and discrete condition selection based on a measurement threshold (Yamaguchi ¶0076-0078)
Saito, in the same field of endeavor of semiconductor device manufacturing, teaches: impurity concentration variability affects device breakdown voltage (Saito ¶0022, 0068).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Uehara in view of Yamaguchi, such that implantation conditions are selected based on the measurement in variability of unevenness of the impurity concentration of the drift layer during step (b), and to select from discrete implantation conditions, as taught by Yamaguchi, and such that “ion implantation of the impurity ions is performed, with predetermined two implantation conditions being set for width of unevenness of the impurity concentration of the drift layer”, in order to suppress a reduction in breakdown voltage caused by fluctuations in impurity concentrations (Saito ¶0074).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Uehara et al (US 20170271442 A1, as cited in IDS dated 08/11/2025, hereafter Uehara) in view of Yamaguchi et al (US 20080038850 A1, as cited in IDS dated 08/11/2025, hereafter Yamaguchi), Feng et al (US 20150050751 A1, hereafter Feng) and Kobayashi et al (US 20210183995 A1, hereafter Kobayashi), as applied to claim 1, and further in view of Bolotnikov et al (US 20190140048 A1, as cited in IDS dated 08/11/2025, hereafter Bolotnikov).
Regarding claim 5, Uehara in view of Yamaguchi, Feng, and Kobayashi teaches: The manufacturing method for the silicon carbide semiconductor device according to claim 1.
Uehara in view of Yamaguchi, Feng, and Kobayashi does not teach: wherein in the step (c), the ion implantation mask is formed so as to form a plurality of second openings for forming a plurality of guard rings at an outer peripheral portion of the silicon carbide semiconductor substrate, and in the step (d), the impurity ions of the second conductivity type are implanted through the plurality of second openings, and the plurality of guard rings are formed at the outer peripheral portion in an implantation profile same as the implantation profile of the plurality of second pillar regions.
Bolotnikov, in the same field of endeavor of semiconductor device manufacturing, teaches: forming an ion implantation mask (Bolotnikov 150) with a plurality of first openings (Bolotnikov 152, ¶0038, in an active region 8) and a plurality of second openings (Bolotnikov fig 5B, unlabeled, openings in 150 within termination region 6), the plurality of second openings are formed for forming a plurality of guard rings (Bolotnikov 54, 68, 92, ¶0020, 0031 “continuous, vertical pillars”, under a broadest reasonable interpretation of “guard ring”, Bolotnikov is at least forming periodic termination structures at a device periphery to suppress electric field leakage) at an outer peripheral portion (Bolotnikov 6, “termination region”) of a silicon carbide semiconductor substrate (Bolotnikov 12)(Bolotnikov figs 2, 5B, 7, ¶0021, 0031),
(d) implanting impurity ions of a second conductivity type (Bolotnikov 154, ¶0038) through the plurality of first openings (Bolotnikov fig 5B), forming a plurality of second pillar regions (Bolotnikov 52) of the second conductivity type (Bolotnikov fig 5B) in a drift layer (Bolotnikov 20, ¶0020),
and in the step (d), the impurity ions of the second conductivity type are implanted through the plurality of second openings (Bolotnikov fig 5B), and the plurality of guard rings are formed at the outer peripheral portion in an implantation profile same as the implantation profile of the plurality of second pillar regions (Bolotnikov fig 5B, ¶0038, “implant dopant of the second conductivity-type into both the active region 8 and the termination region 6 of the epi layer 20”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Uehara in view of Yamaguchi, Feng, and Kobayashi to include forming second openings in a peripheral portion in step (c), and to perform the implantation of (d), using the same profile to implant through the second openings, to form guard rings in a peripheral portion the silicon carbide semiconductor substrate, as taught by Bolotnikov, and such that “wherein in the step (c), the ion implantation mask is formed so as to form a plurality of second openings for forming a plurality of guard rings at an outer peripheral portion of the silicon carbide semiconductor substrate, and in the step (d), the impurity ions of the second conductivity type are implanted through the plurality of second openings, and the plurality of guard rings are formed at the outer peripheral portion in an implantation profile same as the implantation profile of the plurality of second pillar regions”, in order to provide effective edge termination, thereby preventing edge breakdown, without requiring an additional implantation step (Bolotnikov ¶0020, 0024, 0047).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Uehara et al (US 20170271442 A1, as cited in IDS dated 08/11/2025, hereafter Uehara) in view of Yamaguchi et al (US 20080038850 A1, as cited in IDS dated 08/11/2025, hereafter Yamaguchi), Feng et al (US 20150050751 A1, hereafter Feng) and Kobayashi et al (US 20210183995 A1, hereafter Kobayashi), as applied to claim 1, and further in view of Kono et al (US 20230088612 A1, hereafter Kono).
Regarding claim 7, Uehara in view of Yamaguchi, Feng, and Kobayashi teaches: The manufacturing method for the silicon carbide semiconductor device according to claim 1,
wherein the transistor (Uehara 100) is a planar transistor including a gate (Uehara 18) being provided on the epitaxial layer (Uehara fig 1),
the step (f) comprises forming a body region of the second conductivity type (Uehara 34, ¶0056, “p type”) at an upper layer portion of the epitaxial layer (Uehara 128d)(Uehara fig 1, 9), and
the body region is connected to the plurality of second pillar regions (Uehara fig 1).
Uehara in view of Yamaguchi, Feng, and Kobayashi does not explicitly teach: the body region having an impurity concentration of the second conductivity type that is higher than an impurity concentration of the second conductivity type of the plurality of second pillar regions.
Kono, in the same field of endeavor of semiconductor device manufacturing, teaches: a body region (Kono 26) having an impurity concentration of a second conductivity type (Kono ¶0069) higher than an impurity concentration of the second conductivity type (Kono ¶0099) of a plurality of second pillar regions (Kono 32)(Kono ¶0099, “The p-type impurity concentration in the pillar region 32 is lower than, for example, the p-type impurity concentration in the body region 26”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Uehara in view of Yamaguchi, Feng, and Kobayashi, such that an impurity concentration of the second conductivity type is higher in the body region than the second pillar regions, as taught by Kono, in order to suppress a decrease in dielectric breakdown voltage of the device (Kono ¶0141).
Claims 8 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Uehara et al (US 20170271442 A1, as cited in IDS dated 08/11/2025, hereafter Uehara) in view of Feng et al (US 20150050751 A1, hereafter Feng) and Kobayashi et al (US 20210183995 A1, hereafter Kobayashi).
Regarding claim 8, Uehara teaches: A manufacturing method for a silicon carbide semiconductor device (Uehara ¶0082-0094, figs 1-9), the manufacturing method comprising the steps of:
(a) forming a drift layer (Uehara 128a-c) of a first conductivity type (Uehara ¶0083, 0086, 0089, “n type”) on a silicon carbide semiconductor substrate (Uehara 124) of the first conductivity type (Uehara ¶0082, “n+ type”) through epitaxial growth (Uehara ¶0083, 0086, 0089, 0092, “128a is formed by epitaxial growth”)(Uehara figs 2, 4, 6);
(c) forming an ion implantation mask (Uehara 150a-c, ¶0084, 0087, 0090, 0093) on the drift layer (Uehara fig 3), the ion implantation mask including a plurality of first openings being periodically provided (Uehara figs 3, 5, 7, 9);
(d) implanting impurity ions (Uehara ¶0084, 0087, 0090, 0093, “Al”) of a second conductivity type (Uehara ¶0084, 0087, 0090, 0093, “Al… as the p type impurities”) through the plurality of first openings (Uehara figs 3, 5, 7, 9), forming a plurality of second pillar regions (Uehara 30, 32, figs 1, 9) of the second conductivity type (Uehara ¶0084, 0087, 0090, 0093, “p type region 30c … p type region 32c”) in the drift layer (Uehara ¶0085, 0088, 0091, 0093, figs 3, 5, 7, 9), and turning the drift layer between the plurality of second pillar regions into a first pillar region (Uehara 28, under a broadest reasonable interpretation of “pillar region”, figs 1, 9) of the first conductivity type (Uehara ¶0085, 0088, 0091, 0093, “n type region 28d”, figs 3, 5, 7, 9);
(e) forming an epitaxial layer (Uehara 128d) of the first conductivity type (Uehara ¶0092, “n type fifth silicon carbide layer 128d”) on the drift layer through epitaxial growth (Uehara ¶0092, “128d is formed by epitaxial growth”, fig 8); and
(f) forming a plurality of unit cells of a transistor (Uehara 100, ¶0094) in the epitaxial layer (Uehara fig 9).
Uehara does not teach: (b) measuring film thickness of the drift layer;
wherein the step (d) comprises performing feedforward control on ion implantation energy for the impurity ions so that there is a positive correlation with measurement results of the step (b).
Feng, in the same field of endeavor of semiconductor device manufacturing, teaches: (b) measuring film thickness of a layer (Feng ¶0040), wherein a step (d) further comprises performing feedforward control on ion implantation energy (Feng ¶0012, 0041, “The parameter of the ion implantation process is, for instance, energy”) for the impurity ions with measurement results of the step (b)(Feng ¶0041, 0042).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Uehara to include measuring a drift layer thickness before ion implantation, and to adjust the implantation energy of the ion implantation, such that “the step (d) further comprises performing feedforward control on ion implantation energy for the impurity ions with measurement results of the step (b)”, in order to improve device uniformity by compensating for drift layer thickness variations (Feng ¶0064).
Uehara in view of Feng does not explicitly teach: a positive correlation with measurement results of the step (b).
Kobayashi, in the same field of endeavor of semiconductor device manufacturing, teaches: adjusting ion implantation energy so that there is a positive correlation with a drift layer thickness (Kobayashi ¶0045, 0048, “acceleration energy is assumed to be in a range from 60 keV to 700 keV”, “this number is dependent on the film thicknesses of the parallel pn structures 33, the acceleration energy of the ion implantations”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify step (g) of Uehara in view of Feng to have a positive correlation between ion implantation energy and a drift layer thickness, and such that “the step (d) further comprises performing feedforward control on ion implantation energy for the impurity ions so that there is a positive correlation with measurement results of the step (b)”, in order to ensure that proper implantation depth and charge balance is maintained despite epitaxial film thickness variations (Kobayashi ¶0048).
Regarding claim 13, Uehara in view of Feng and Kobayashi teaches: The manufacturing method for the silicon carbide semiconductor device according to claim 8.
Uehara in view of Feng and Kobayashi does not explicitly teach: wherein the transistor is a trench transistor including a trench gate being provided in the epitaxial layer,
the step (f) comprises forming an electric field protection region of the second conductivity type at a bottom portion of the trench gate, the electric field protection region having an impurity concentration of the second conductivity type that is higher than an impurity concentration of the second conductivity type of the plurality of second pillar regions, and
the electric field protection region is connected to the plurality of second pillar regions.
Uehara further teaches: a trench gate type transistor (Uehara ¶0112).
Kobayashi further teaches: a transistor is a trench transistor (Kobayashi 301, ¶0060) including a trench gate (Kobayashi 20) being provided in an epitaxial layer (Kobayashi 32, ¶0048, figs 6-9)(Kobayashi ¶0051, fig 9),
a step (f) comprises forming an electric field protection region (Kobayashi 3, ¶0063, “mitigating electric field concentration”) of the second conductivity type (Kobayashi ¶0063, “p+-type”) at a bottom portion of the trench gate (Kobayashi ¶0063, “near the bottoms of the trenches 23”, fig 9), the electric field protection region having an impurity concentration of a second conductivity type (Kobayashi ¶0063, “p+-type”, fig 9) higher than an impurity concentration of the second conductivity type (Kobayashi ¶0048, “p-type”, fig 9) of a plurality of second pillar regions (Kobayashi 30, ¶0078, “p-type column regions 30”)(Kobayashi fig 9, ¶0031), and
the electric field protection region is connected to the plurality of second pillar regions (Kobayashi, ¶0062, fig 9).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Uehara in view of Feng and Kobayashi to implement the device as a trench gate type transistor, as taught by Kobayashi and Uehara, in order to reduce on resistance of a device (Kobayashi ¶0071), and such that “the electric field protection region having an impurity concentration of the second conductivity type that is higher than an impurity concentration of the second conductivity type of the plurality of second pillar regions”, in order to suppress electric field increases at the trench bottoms, thereby suppressing gate insulation breakdown (Kobayashi ¶0064-0065), and/or to increase source-drain capacitance, thereby suppressing hard recovery (Kobayashi ¶0076).
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Uehara et al (US 20170271442 A1, as cited in IDS dated 08/11/2025, hereafter Uehara) in view of Feng et al (US 20150050751 A1, hereafter Feng) and Kobayashi et al (US 20210183995 A1, hereafter Kobayashi), as applied to claim 8, and further in view of Yamaguchi et al (US 20080038850 A1, as cited in IDS dated 08/11/2025, hereafter Yamaguchi).
Regarding claim 9, Uehara in view of Feng and Kobayashi teaches: The manufacturing method for the silicon carbide semiconductor device according to claim 8.
Uehara in view of Feng and Kobayashi does not teach: further comprising (g) measuring impurity concentration of the drift layer, between the step (b) and the step (c), wherein
the step (d) further comprises performing feedforward control on an ion implantation amount of the impurity ions so that there is a positive correlation with measurement results of the step (g).
Yamaguchi, in the same field of endeavor of semiconductor device manufacturing, teaches: (g) measuring impurity concentration of a drift layer (Yamaguchi 10, ¶0128 )(Yamaguchi ¶0044, “impurity concentration of the N type substrate 10 doped with the impurity is measured”), wherein
the step (d) comprises performing feedforward control on an amount of the impurity ions so that there is a positive correlation with measurement results of the step (b)(Yamaguchi ¶0048, “using the concentration of the N type substrate 10 measured at the step shown in FIG. 2A, the P type epitaxial layer 12 is formed while the concentration of this P type epitaxial layer 12 is being adjusted”, under a broadest reasonable interpretation of “feedforward control”, Yamaguchi is at least using parameters from an earlier process step to adjust process conditions in a subsequent step, before the subsequent step is performed. Further, there is positive correlation between the results of the measurement performed by Yamaguchi, and the resultant concentration of the P type epitaxial layer, specifically, in order to achieve charge balance stated by Yamaguchi, if the concentration of N type goes up or down, so must that of the P type epitaxial layer).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Uehara in view of Feng and Kobayashi to include the measuring and feedforward control of Yamaguchi before conducting ion implantation, such that it is “between the step (b) and the step (c)”, and such that “the step (d) further comprises performing feedforward control on an ion implantation amount of the impurity ions so that there is a positive correlation with measurement results of the step (g)”, in order to hold constant a ratio between the first and second type conductivity ions during manufacturing, thereby providing a charge balance in the drift layer to suppress impurity migration and/or outward diffusion (Yamaguchi ¶0048-0049).
Regarding claim 10, Uehara in view of Feng, Kobayashi, and Yamaguchi teaches: The manufacturing method for the silicon carbide semiconductor device according to claim 9.
Uehara in view of Feng, Kobayashi, and Yamaguchi does not explicitly teach: further comprising (h) measuring average opening width of the plurality of first openings of the ion implantation mask, between the step (c) and the step (d), wherein the step (d) further comprises performing feedforward control on the ion implantation amount so that there is a negative correlation with measurement results of the step (h).
Yamaguchi further teaches: (h) measuring a width of an opening (Yamaguchi 11) before forming a pillar of a second conductivity type (Yamaguchi 12, 3, under a broadest reasonable interpretation of “pillar”)(Yamaguchi ¶0134), and
adjusting a concentration of impurity ions to have a negative correlation with measurement results of the step (h)(Yamaguchi ¶0148, 0149, in order to maintain charge balance, if width increases, impurity concentration must decrease, therefore the concentration of impurity ions has a negative correlation to the width measurement).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Uehara in view of Feng, Kobayashi, and Yamaguchi to include a step of “(h) measuring average opening width of the plurality of first openings of the ion implantation mask, between the step (c) and the step (d)”, and to adjust the impurity concentration based on the measurement, such that “the step (d) further comprises performing feedforward control on the ion implantation amount so that there is a negative correlation with measurement results of the step (h)”, in order to maintain a charge balance relationship, thereby holding constant a ratio between the first and second type conductivity ions during manufacturing, thereby suppressing impurity migration and/or outward diffusion (Yamaguchi ¶0048-0049).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Uehara et al (US 20170271442 A1, as cited in IDS dated 08/11/2025, hereafter Uehara) in view of Feng et al (US 20150050751 A1, hereafter Feng), Kobayashi et al (US 20210183995 A1, hereafter Kobayashi), and Yamaguchi et al (US 20080038850 A1, as cited in IDS dated 08/11/2025, hereafter Yamaguchi), as applied to claim 9, and further in view of Saito et al (US 20050280086 A1, hereafter Saito).
Regarding claim 11, Uehara in view of Feng, Kobayashi, and Yamaguchi teaches: The manufacturing method for the silicon carbide semiconductor device according to claim 9, wherein in the step (d), ion implantation of the impurity ions is performed (Uehara ¶0084, 0087, 0090, 0093, “aluminum (Al) is ion-implanted”, figs 3-7).
Uehara in view of Feng, Kobayashi, and Yamaguchi does not teach: ion implantation of the impurity ions is performed, with predetermined two implantation conditions being set for width of unevenness of the impurity concentration of the drift layer.
Yamaguchi further teaches: adjusting a p-type concentration based on a width measurement (Yamaguchi ¶0048, 0134), and discrete condition selection based on a measurement threshold (Yamaguchi ¶0076-0078)
Saito, in the same field of endeavor of semiconductor device manufacturing, teaches: impurity concentration variability affects device breakdown voltage (Saito ¶0022, 0068).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Uehara in view of Feng, Kobayashi, and Yamaguchi, such that implantation conditions are selected based on the measurement in variability of unevenness of the impurity concentration of the drift layer during step (b), and to select from discrete implantation conditions, as taught by Yamaguchi, and such that “ion implantation of the impurity ions is performed, with predetermined two implantation conditions being set for width of unevenness of the impurity concentration of the drift layer”, in order to suppress a reduction in breakdown voltage caused by fluctuations in impurity concentrations (Saito ¶0074).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Uehara et al (US 20170271442 A1, as cited in IDS dated 08/11/2025, hereafter Uehara) in view of Feng et al (US 20150050751 A1, hereafter Feng) and Kobayashi et al (US 20210183995 A1, hereafter Kobayashi), as applied to claim 8, and further in view of Bolotnikov et al (US 20190140048 A1, as cited in IDS dated 08/11/2025, hereafter Bolotnikov).
Regarding claim 12, Uehara in view of Feng and Kobayashi teaches: The manufacturing method for the silicon carbide semiconductor device according to claim 8.
Uehara in view of Feng and Kobayashi does not teach: wherein in the step (c), the ion implantation mask is formed so as to form a plurality of second openings for forming a plurality of guard rings at an outer peripheral portion of the silicon carbide semiconductor substrate, and in the step (d), the impurity ions of the second conductivity type are implanted through the plurality of second openings, and the plurality of guard rings are formed at the outer peripheral portion in an implantation profile same as the implantation profile of the plurality of second pillar regions.
Bolotnikov, in the same field of endeavor of semiconductor device manufacturing, teaches: forming an ion implantation mask (Bolotnikov 150) with a plurality of first openings (Bolotnikov 152, ¶0038, in an active region 8) and a plurality of second openings (Bolotnikov fig 5B, unlabeled, openings in 150 within termination region 6), the plurality of second openings are formed for forming a plurality of guard rings (Bolotnikov 54, 68, 92, ¶0020, 0031 “continuous, vertical pillars”, under a broadest reasonable interpretation of “guard ring”, Bolotnikov is at least forming periodic termination structures at a device periphery to suppress electric field leakage) at an outer peripheral portion (Bolotnikov 6, “termination region”) of a silicon carbide semiconductor substrate (Bolotnikov 12)(Bolotnikov figs 2, 5B, 7, ¶0021, 0031),
(d) implanting impurity ions of a second conductivity type (Bolotnikov 154, ¶0038) through the plurality of first openings (Bolotnikov fig 5B), forming a plurality of second pillar regions (Bolotnikov 52) of the second conductivity type (Bolotnikov fig 5B) in a drift layer (Bolotnikov 20, ¶0020),
and in the step (d), the impurity ions of the second conductivity type are implanted through the plurality of second openings (Bolotnikov fig 5B), and the plurality of guard rings are formed at the outer peripheral portion in an implantation profile same as the implantation profile of the plurality of second pillar regions (Bolotnikov fig 5B, ¶0038, “implant dopant of the second conductivity-type into both the active region 8 and the termination region 6 of the epi layer 20”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Uehara in view of Feng and Kobayashi to include forming second openings in a peripheral portion in step (c), and to perform the implantation of (d), using the same profile to implant through the second openings, to form guard rings in a peripheral portion the silicon carbide semiconductor substrate, as taught by Bolotnikov, and such that “wherein in the step (c), the ion implantation mask is formed so as to form a plurality of second openings for forming a plurality of guard rings at an outer peripheral portion of the silicon carbide semiconductor substrate, and in the step (d), the impurity ions of the second conductivity type are implanted through the plurality of second openings, and the plurality of guard rings are formed at the outer peripheral portion in an implantation profile same as the implantation profile of the plurality of second pillar regions”, in order to provide effective edge termination, thereby preventing edge breakdown, without requiring an additional implantation step (Bolotnikov ¶0020, 0024, 0047).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Uehara et al (US 20170271442 A1, as cited in IDS dated 08/11/2025, hereafter Uehara) in view of Feng et al (US 20150050751 A1, hereafter Feng) and Kobayashi et al (US 20210183995 A1, hereafter Kobayashi), as applied to claim 8, and further in view of Kono et al (US 20230088612 A1, hereafter Kono).
Regarding claim 14, Uehara in view of Feng and Kobayashi teaches: The manufacturing method for the silicon carbide semiconductor device according to claim 8,
wherein the transistor (Uehara 100) is a planar transistor including a gate (Uehara 18) being provided on the epitaxial layer (Uehara fig 1),
the step (f) comprises forming a body region of the second conductivity type (Uehara 34, ¶0056, “p type”) at an upper layer portion of the epitaxial layer (Uehara 128d)(Uehara fig 1, 9), and
the body region is connected to the plurality of second pillar regions (Uehara fig 1).
Uehara in view of Feng and Kobayashi does not explicitly teach: the body region having concentration an impurity concentration of the second conductivity type that is higher than an impurity concentration of the second conductivity type of the plurality of second pillar regions.
Kono, in the same field of endeavor of semiconductor device manufacturing, teaches: a body region (Kono 26) having an impurity concentration of a second conductivity type (Kono ¶0069) higher than an impurity concentration of the second conductivity type (Kono ¶0099) of a plurality of second pillar regions (Kono 32)(Kono ¶0099, “The p-type impurity concentration in the pillar region 32 is lower than, for example, the p-type impurity concentration in the body region 26”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Uehara in view of Feng and Kobayashi, such that an impurity concentration of the second conductivity type is higher in the body region than the second pillar regions, as taught by Kono, in order to suppress a decrease in dielectric breakdown voltage of the device (Kono ¶0141).
Response to Arguments
Applicants arguments with respect to claims 1, and 3-14, have been fully considered and are not persuasive.
Regarding claims 1 and 8, the applicant alleges at page 9:
Applicant respectfully submits that Kobayashi, taken alone or in combination with any one or more of Uehara, Yamaguchi, and Feng, fails to suggest "a positive correlation with measurement results of the step (g)," as recited in amended claim 1, and "the step (d) comprises performing feedforward control on ion implantation energy for the impurity ions so that there is a positive correlation with measurement results of the step (b)," as recited in claim 8.
Examiner’s response:
The Examiner respectfully disagrees. The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Further, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Kobayashi is relied upon to establish that film thickness and acceleration energy are recognized interdependent variables within a super-junction ion-implantation process (Kobayashi ¶0048). The combination renders the claimed positive correlation obvious in implementing Feng’s measurement based energy feedforward in Uehara’s super-junction pillar process, as a person of ordinary skill in the art would adjust the implantation energy to adjust an implantation depth across thickness variations, consistent with energy dependent implant depth as disclosed by Feng (Feng ¶0042); the positive correlation being a higher implantation energy required for thicker drift layers.
Further, it appears that the applicant’s reading of Kobayashi ¶0048 is too narrow, and appears focused on the “number of processes” within the sentence, while ignoring the critical teaching of “the acceleration energy of the ion implantations”. The sentence clearly establishes implantation energy as an interrelated parameter of film thickness, not that the number of processes alone is the dependent variable. Kobayashi establishes that in a cycle of repeated cycles, film thickness and acceleration energy are interdependent variables. Kobayashi further teaches the adjustment of acceleration energy for ion implantation (Kobayashi ¶0045, 60-700 keV).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/Mounir S Amer/Primary Examiner, Art Unit 2818
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