DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The 12/3/2025 "Reply" elects without traverse and identifies claims 1-5 and 8-20 as being drawn to Species A1. Accordingly, Examiner has withdrawn claims 6-7 from further consideration as being drawn to a non-elected invention. See, for example, 37 CFR § 1.142(b).
The 10/21/2025 restriction requirement is proper, is maintained, and is hereby made final.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 8, 11-16, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lue (US Pub. No. 20220130862).
Regarding claim 1, in FIGs. 1A-2H, Lue discloses a ferroelectric memory device comprising: a substrate (100); a gate structure disposed over the substrate and including a plurality of gate electrode layers (109/126, paragraph [0021]) spaced apart from each other along a first direction (Z) substantially perpendicular to a surface of the substrate; a first electrode pillar (122) and a second electrode pillar (124, paragraph [0022]) that extend along the first direction and are disposed to be spaced apart from each other in a second direction (X) substantially parallel to the surface of the substrate inside a hole (filled by at least 122 and 124) penetrating the gate structure; and a device isolation structure (116, paragraph [0040]) disposed to cross (overlap with) the first and second electrode pillars and to separate the gate structure over the substrate, wherein the gate structure further includes a plurality of ferroelectric layers (125, paragraph [0021]) and a plurality of channel layers (left and right portions of 112 associated with each cell region 12, paragraph [0022]) that are disposed to correspond to the plurality of gate electrode layers.
Regarding claim 2, in FIGs. 1A-2H, Lue discloses that each of the first and second electrode pillars is electrically connected to the plurality of channel layers (directly contacting).
Regarding claim 3, in FIGs. 1A-2H, Lue discloses that a portion of an outer circumferential surface of the first electrode pillar and a portion of an outer circumferential surface of the second electrode pillar are disposed to contact each of the plurality of channel layers.
Regarding claim 4, in FIGs. 1A-2H, Lue discloses that among the plurality of gate electrode layers, the plurality of ferroelectric layers, and the plurality of channel layers, one gate electrode layer, one ferroelectric layer, and one channel layer corresponding to each other are sequentially disposed on a plane parallel to the surface of the substrate.
Regarding claim 5, in FIGs. 1A-2H, Lue discloses that the plurality of channel layers are disposed along a circumference of the hole, wherein each of the plurality of ferroelectric layers is disposed to surround each of the plurality of channel layers, and wherein each of the plurality of gate electrode layers is disposed to surround each of the plurality of ferroelectric layers.
Regarding claim 8, in FIGs. 1A-2H, Lue discloses that the gate structure further includes interlayer insulation layers (104, paragraph [0020]) disposed between the plurality of gate electrode layers, the plurality of ferroelectric layers, and the plurality of channel layers along the first direction (Z).
Regarding claim 11, in FIGs. 1A-2H, Lue discloses that the device isolation structure is disposed to extend in a direction substantially parallel to the surface of the substrate (116 is a 3D object that extends in the X direction).
Regarding claim 12, in FIGs. 1A-2H, Lue discloses a hole filling material layer (114, paragraph [0040]) that fills the hole over the substrate.
Regarding claim 13, in FIGs. 1A-2H, Lue discloses a ferroelectric memory device comprising: a substrate (100); a gate structure disposed over the substrate and including a plurality of gate electrode layers (109/126, paragraph [0021]) spaced apart from each other along a first direction (Z) substantially perpendicular to a surface of the substrate; a plurality of holes penetrating the gate structure over the substrate, the plurality of holes arranged along a second direction (X) substantially parallel to the surface of the substrate; first and second electrode pillars (122 and 124) disposed to extend along the first direction inside the plurality of holes; and a device isolation structure (116) disposed over the substrate to cross (overlap) the plurality of holes and to extend along the second direction, wherein the gate structure further includes a plurality of ferroelectric layers (125) and a plurality of channel layers (left and right portions of 112 associated with each cell region 12, paragraph [0022]), which are disposed to correspond to the plurality of gate electrode layers, and wherein the first and second electrode pillars are disposed to be electrically connected to the plurality of channel layers.
Regarding claim 14, in FIGs. 1A-2H, Lue discloses that a portion of an outer circumferential surface of the first electrode pillar and a portion of an outer circumferential surface of the second electrode pillar are disposed to contact each of the plurality of channel layers.
Regarding claim 15, in FIGs. 1A-2H, Lue discloses that among the plurality of gate electrode layers, the plurality of ferroelectric layers, and the plurality of channel layers, one gate electrode layer, one ferroelectric layer, and one channel layer corresponding to each other are sequentially disposed on a plane parallel to the surface of the substrate.
Regarding claim 16, in FIGs. 1A-2H, Lue discloses that each of the plurality of channel layers is disposed along a circumference of each of the plurality of holes, wherein each of the plurality of ferroelectric layers is disposed to surround each of the plurality of channel layers, and wherein each of the plurality of gate electrode layers is disposed to surround each of the plurality of ferroelectric layers.
Regarding claim 19, in FIGs. 1A-2H, Lue discloses that the device isolation structure is disposed inside the plurality of holes to cross (overlap) the first and second electrode pillars.
Regarding claim 20, in FIGs. 1A-2H, Lue discloses a gate isolation structure (104) disposed between the plurality of holes and extending in the second direction.
Allowable Subject Matter
Claims 9-10 and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 9 and 17, in FIGs. 1A-2H, Lue discloses that the gate structure includes a first gate part (to the left of 116) and a second gate part (to the right of 116) that are separated by the device isolation structure (116).
However, the prior art failed to disclose or reasonably suggest the claimed ferroelectric memory device particularly characterized by the plurality of gate electrode layers of the first gate part being electrically insulated from the plurality of gate electrode layers of the second gate part.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In FIG. 7B, US Pub. No. 2021/0399013 discloses a similar ferroelectric memory device having a device isolation structure (127) disposed over the substrate to separate the first (124A) and second (124B) electrode pillars.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TUCKER J WRIGHT/ Primary Examiner, Art Unit 2891