DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/16/2024 and 12/11/2023 and 06/07/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Group II, Figs. 2 and 4A, as presented in claims 1-5, 7 & 25 in the reply filed on 01/13/2026 is acknowledged.
Claims 6 & 8-24 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/13/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-5, 7 & 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dey (US 10,778,189 B1, of record).
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Regarding claims 1 & 25, Dey (Fig. 4) discloses a device or a method, comprising:
a differential voltage-mode filter circuit comprising a first voltage-mode filter (filter 450a) circuit, a second voltage-mode filter circuit (filter 450b), and
a neutralization network (includes resistors 412a in series with capacitor 418a and , 412b in series with capacitor 418b),
wherein:
the first voltage-mode filter circuit (filter 450) and the second voltage-mode filter (filter 450b) circuit each comprise a unity gain buffer (buffer 410a and 410b, Col. 9, lines 10-12, Col. 7, lines 18-19, unity gain amplifier) having a nonzero output impedance;
the neutralization network comprises a first neutralization impedance circuit (resistor 412a, capacitor 418a) which couples an input node (gate terminal of transistor 422a) of the first voltage-mode filter circuit (450a) to an output node (drain of transistor 422b) of the second voltage-mode filter circuit (filter 450b), and
a second neutralization impedance circuit (resistor 412b and capacitor 418b) which couples an input node (gate terminal of transistor 422b) of the second voltage-mode filter circuit to an output node (drain terminal of transistor 422a) of the first voltage-mode filter circuit (450a); and
the neutralization network is configured to correct a frequency response of each of the first voltage-mode filter circuit and the second voltage-mode filter circuit by at least one of cancelling and compensating for at least one transmission zero of a transfer function of each of the first voltage-mode filter circuit and the second voltage-mode filter circuit, which results from the nonzero output impedance of the respective unity gain buffers (Col. 9, lines 2-10).
Regarding claim 4, Dey (Fig. 4) discloses wherein the first neutralization impedance circuit (resistor 412a and capacitor 418a) and the second neutralization impedance circuit (resistor 412b and capacitor 418b) each comprise passive impedance elements.
Regarding claim 5, Dey (Fig. 4) discloses wherein:
the first neutralization impedance circuit comprises at least a first resistor (resistor 412a) and a first capacitor (capacitor 418a) serially connected between the input node of the first voltage-mode filter circuit and the output node of the second voltage-mode filter circuit; and the second neutralization impedance circuit comprises at least a second resistor (resistor 412b) and a second capacitor (capacitor 418b) serially connected between the input node of the second voltage-mode filter circuit and the output node of the first voltage-mode filter circuit.
Regarding claim 7, Dey (Fig. 4) discloses wherein the first voltage-mode filter circuit (450a)and the second voltage-mode filter circuit each comprise an analog Sallen-Key filter circuit comprising a unity gain source follower (Col. 8, lines 21-23, the buffers 410a and 410b of the first 450a and second 450b integrated Sallen-Key filters are implemented using PMOS source followers).
Allowable Subject Matter
Claims 2-3 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 7697915 B2, Behzad et al. discloses in Fig. 6 an amplifier circuit comprising a resistor 220 being connected in series with capacitor 10 and a resistor 201 being connected in series with capacitor 107.
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/KHIEM D NGUYEN/Examiner, Art Unit 2843