DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
The Amendment filed on 3/11/2026, responding to the Office action mailed on 12/12/2025, has been entered into the record. The present Office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-9 are pending in this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Yanase (WO 2014185010 A1) in view of Nishihata (WO 2022137966 A1).
Re Claim 1 Yanase teaches a semiconductor device (100, page 12 par 4, FIG. 12) comprising:
a chip mounting portion (area over 102b, page 12 par 4); and
a semiconductor chip (10, page 12 par 4) including:
a silicon (carbide) substrate (11, page 9 par 2) having a front surface (top) and a back surface (bottom) opposite the front surface (FIG. 9);
a back surface electrode (15, page 9 last par) formed on the back surface of the silicon substrate (11),
wherein the semiconductor chip (10) is mounted on the chip mounting portion (102b) via a conductive adhesive material (103, page 12 par 4) such that the back surface (bottom) of the silicon substrate (11) of the semiconductor chip (10) faces the chip mounting portion (102b),
wherein a planar shape (10, FIG. 9A, page 11 par 1) of the semiconductor chip (10) is a quadrangular shape (FIG. 9A),
wherein, in plan view, a plurality of thin portions is respectively formed at a plurality of corner portions (FIG. 9) of the back surface (bottom) of the silicon substrate (11) of the semiconductor chip (10),
wherein, in plan view, the plurality of thin portions is spaced apart from each other (FIG. 9A), and
wherein a thickness of a portion of the silicon substrate at each of the plurality of thin portions is smaller than a thickness of a portion of the silicon substrate located between any two adjacent thin portions (FIG. 9A, use region in circle area) of the plurality of thin portions (FIG. 9A).
Yanase does not teach a polyimide resin film formed on the front surface of the silicon substrate.
Nishihata teaches a polyimide resin film (240, page 6 par 4) formed on the front surface of the silicon substrate (200, page 1 par 1, FIG. 3).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Nishihata into the structure of Yanase since Nishihata teaches a semiconductor device structure.
The ordinary artisan would have been motivated to modify Nishihata in combination with Yanase in the above manner for the motivation of integrating a polyimide resin film to protect the device. Page 6 par 4 refers to 240 as a “the first protective film”.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yanase (WO 2014185010 A1) in view of Nishihata (WO 2022137966 A1) as applied to claim 1 above, and further in view of Ko (US 20220020701 A1).
Re Claim 2 Yanase in view of Nishihata teaches the semiconductor device according to claim 1,
wherein the semiconductor chip (Yanase, 10) is a silicon chip (11 contains silicon carbide, page 9 par 2), wherein each of the plurality of thin portions (corners, FIG. 9A) has:
an inclined portion (25, FIG. 9B and C) connected to the back surface (bottom) of the silicon substrate (11) of the semiconductor chip (10); and
a flat portion (25 sides) connected to the inclined portion (top of 25), and
wherein a normal direction of the inclined portion is <111> direction (FIG. 9B and C).
Yanase in view of Nishihata does not teach a normal direction of the flat portion is <100> direction.
Ko teaches a normal direction of the flat portion (500 [0015] portion that contacts upper surface of 513) is <100> direction (FIG. 12).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Ko into the structure of Yanase in view of Nishihata since the patent teaches a mounted semiconductor element.
The ordinary artisan would have been motivated to modify Ko in combination with Yanase in view of Nishihata in the above manner for the motivation of optimally shaping the substrate to allow for the device to be as small as possible as the industry continues to scale down the size of semiconductor devices. [0003] states, “Portable devices have been increasingly demanded in recent electronic product markets, where much portability may be achieved through a reduction in size and weight of electronic parts mounted on the portable devices.”
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yanase (WO 2014185010 A1) in view of Nishihata (WO 2022137966 A1) as applied to claim 1 above, and further in view of Tanaka (JP 2015087131 A).
Re Claim 3 Yanase in view of Nishihata teaches the semiconductor device according to claim 1, but does not teach a planar shape of each of the plurality of thin portions is a triangular shape.
Tanaka teaches a planar shape of each of the plurality of thin portions (use top surface of 310 in 323 regions, FIG. 70) is a triangular shape (FIG. 70 and 74).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Tanaka into the structure of Yanase in view of Nishihata since Tanaka teaches a semiconductor device structure.
The ordinary artisan would have been motivated to modify Tanaka in combination with Yanase in view of Nishihata in the above manner for the motivation of integrating thin portions with a triangular shape to allow for triaxial force detection tests on the device. Page 21 par 2 states, “Even in such a configuration, triaxial force detection of the X axis, the Y axis, and the Z axis may be performed by matrix calculation.”
Claims 4 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yanase (WO 2014185010 A1) in view of Nishihata (WO 2022137966 A1) as applied to claim 1 above, and further in view of Yutani (US 20220037488 A1).
Re Claim 4 Yanase in view of Nishihata teaches the semiconductor device according to claim 1, but does not teach the semiconductor chip has:
a first corner portion provided at one end portion of a first side of the semiconductor chip; and
a second corner portion provided at another end portion of the first side of the semiconductor chip,
wherein a first thin portion of the plurality of thin portions is formed at the first corner portion,
wherein a second thin portion of the plurality of thin portions is formed at the second corner portion,
wherein a length of a side of the first thin portion is less than or equal to a quarter of a length of the first side, the side of the first thin portion being one of three sides each composing the first thin portion, and the side of the first thin portion overlapping the first side of the semiconductor chip, and
wherein a length of a side of the second thin portion is less than or equal to a quarter of the length of the first side, the side of the second thin portion being one of three sides each composing the second thin portion, and the side of the second thin portion overlapping the first side of the semiconductor chip.
Yutani teaches the semiconductor chip (1, [0050], FIG. 1) has:
a first corner portion (63, top right FIG. 1, [0062]) provided at one end portion of a first side of the semiconductor chip (1); and
a second corner portion (63 top left FIG. 1) provided at another end portion of the first side of the semiconductor chip (1),
wherein a first thin portion (402 in upper right corner of 1, FIG. 1) of the plurality of thin portions is formed at the first corner portion (FIG. 4 and 13B),
wherein a second thin portion (42) of the plurality of thin portions is formed at the second corner portion (FIG. 4 and 13B, FIG. 4 shows 1st corner, but the 2nd corner’s architecture will be similar),
wherein a length of a side of the first thin portion (use bottom of 402 trench, FIG. 13B) is less than or equal to a quarter of a length of the first side (use length of 63 along right edge, FIG. 1), the side of the first thin portion being one of three sides (bottom right and bottom left corners of 1) each composing the first thin portion (402), and the side of the first thin portion overlapping the first side (use 63 on right edge of 1, FIG. 1) of the semiconductor chip (FIG. 4), and
wherein a length of a side of the second thin portion (use bottom of 42 trench, FIG. 13B) is less than or equal to a quarter of the length of the first side (use length of 63 along right edge, FIG. 1), the side of the second thin portion being one of three sides each composing the second thin portion (42), and the side of the second thin portion (42) overlapping the first side (use 63 on right edge of 1, FIG. 1) of the semiconductor chip (FIG. 4).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Yutani into the structure of Yanase in view of Nishihata since Yutani teaches a semiconductor device containing an active region and a peripheral region.
The ordinary artisan would have been motivated to modify Yutani in combination with Yanase in view of Nishihata in the above manner for the motivation of shaping the outer edges of the semiconductor device to help optimize the resistance in the device. [0033] states, “Thus, in the corner portion of the second trench where the electric field is likely to be gathered in the semiconductor chip, the resistance to insulation damage of the second insulating film (the second thin portion) can be enhanced.”
Re Claim 8 Yanase in view of Nishihata and Yutani teaches the semiconductor device according to claim 1, wherein each of the plurality of thin portions (Yutani, 402 and 42) is comprised of a plurality of slit-groove portions (FIG. 4, see section since VI section).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Yanase (WO 2014185010 A1) in view of Nishihata (WO 2022137966 A1) as applied to claim 1 above, and further in view of Han (US 20220165652 A1).
Re Claim 5 Yanase in view of Nishihata teaches the semiconductor chip (Nishihata, 100, page 2 last par) has:
an active region (280) in which a power transistor is formed (page 5 par 2 states, “…the power transistor is provided in the portion corresponding to the active region 280 …”);
a guard ring region (230) surrounding the active region (280) in plan view (page 5 par 3 states, “Further, the active region 280 is surrounded by the pressure resistant structure region 283 provided with a plurality of pressure resistant structure portions 230 such as guard rings in the circumferential direction around the z direction.”); and
wherein the polyimide resin film (240 and 250) is formed in each of the active region (240 in 280, page 6 par 4) and the guard ring region (250 in 230, page 7 par 1, FIG. 1),
Yanase in view of Nishihata does not teach a scribe region surrounding the guard ring region in plan view, wherein the polyimide resin film is not formed in the scribe region, and
wherein each of the plurality of thin portions has a region overlapping at least the scribe region and the guard ring region.
Han teaches a scribe region (SL) [0057] surrounding the guard ring region (FIG. 5, [0058] states, “…the guard ring region II, and the edge region III are provided, may be included in each of the first and second semiconductor chips 10 and 20.” SL surrounds the chips in FIG. 5 and therefore surrounds the guard ring regions in the chips) in plan view, wherein the polyimide resin film (Han does not teach a polyimide layer, so the scribe region does not contain polyimide) is not formed in the scribe region (SL), and
wherein each of the plurality of thin portions (device shows thin portions at outer edges of SL region, FIG. 9) has a region overlapping at least the scribe region and the guard ring region (SL, FIG. 9).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Han into the structure of Yanase in view of Nishihata since Han teaches a semiconductor device structure.
The ordinary artisan would have been motivated to modify Han in combination with Yanase in view of Nishihata in the above manner for the motivation of integrating scribe lines between the active regions of each individual device to allow on to easily cut the chips apart from each other. [0069] states, “Referring to FIG. 10, the scribe line SL may be cut through, for example, a sawing process using a blade.”
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Yanase (WO 2014185010 A1) in view of Nishihata (WO 2022137966 A1) as applied to claim 1 above, and further in view of Li (US 20220093754 A1) and Mori (JP 2017103272 A).
Re Claim 6 Yanase in view of Nishihata teaches the semiconductor device according to claim 1, but does not teach a vertical typed trench power MOSFET is formed in the semiconductor chip.
Li teaches a vertical typed trench power MOSFET (126) [0047] is formed in the semiconductor chip (100G, FIG. 1G).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Li into the structure of Yanase in view of Nishihata since Li teaches a semiconductor device containing a vertical typed trench power MOSFET.
The ordinary artisan would have been motivated to modify Li in combination with Yanase in view of Nishihata in the above manner for the motivation of integrating a vertical power MOSFET to help optimize the electric fields in adjacent semiconductor regions. [0032] states, “FIG. 1A through FIG. 1H depict respective cross-sections of a semiconductor device 100 at various points in the fabrication of power metal-oxide-semiconductor field effect transistors (MOSFETs) that includes field plates. Field plates often function to reduce an electric field in an adjacent semiconductor region.”
Yanase in view of Nishihata and Li does not teach the back surface electrode is provided at each of the plurality of thin portions.
Mori teaches the back surface electrode (13d, page 8 par 1) is provided at each of the plurality of thin portions (FIG 11, edges are thinner than the center of the 10L in FIG. 11 and 13 expands across the device).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Mori into the structure of Yanase in view of Nishihata and Li since Mori teaches a semiconductor device containing a backside electrode.
The ordinary artisan would have been motivated to modify Mori in combination with Yanase in view of Nishihata and Li in the above manner for the motivation of adding a backside electrode to the device to help the semiconductor maintain power levels. Page 1 last par states, “A semiconductor device (power device) capable of handling a power of several watts or more, when an abnormality occurs in a load, causes an immediate breakdown because the power is larger than that of a logic semiconductor device.”
Re Claim 7 Yanase in view of Nishihata and Li and Mori teaches the semiconductor device according to claim 6, wherein a channel plane (Li, bottom of 128 trench) of the vertical typed trench power MOSFET is {100} plane (FIG. 1G).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yanase (WO 2014185010 A1) in view of Nishihata (WO 2022137966 A1) as applied to claim 1 above, and further in view of Hattori (WO 2022123954 A1).
Re Claim 9 Yanase in view of Nishihata teaches the semiconductor device according to claim 1, but does not teach each of the plurality of thin portions is comprised of a plurality of lattice-groove portions.
Hattori teaches each of the plurality of thin portions (37, page 8 par 4) is comprised of a plurality of lattice-groove portions (FIG. 4G).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Hattori into the structure of Yanase in view of Nishihata since Hattori teaches a semiconductor device with lattice shaped grooves.
The ordinary artisan would have been motivated to modify Hattori in combination with Yanase in view of Nishihata in the above manner for the motivation of making the grooves in the semiconductor device lattice shaped to help optimize the groove dimensions and shape. Page 2 par 1 states, “…the groove width of the lattice-shaped grooves can be expanded with proximity to the light incident surface side…”
Response to Arguments
Applicant’s arguments with respect to claims 1-9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH MARK SIPLING/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 3/24/26