DETAILED ACTION
This Office action responds to the application filed on 06/07/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election with traverse of Species 3, in the reply filed on 12/01/2025, is acknowledged. The traversal is on the ground(s) that the species are not mutually exclusive. This is found persuasive because there is overlap between subject matter such as Species 2 including the subject matter of Species 3 and 5, and Species 3 including the subject matter of Species 1 and 6. Examiner concedes, and the restriction filed on 10/17/2025 is withdrawn. Claims 1-30 will be examined in this Office action.
Claim Rejections - 35 USC § 102 & 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 12, 13, 14, 17, 23, 24, & 30 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by El Amrani (US 20240113060).
Regarding Claim 1, El Amrani (see, e.g., fig. 1, fig. 2a) shows an integrated device comprising:
a die 106 (see, e.g., para.0038) having a contact pad 102 (see, e.g., para.0037);
and a solder cap 114 (see, e.g., para.0042) electrically connected to the contact pad by a multi-layer interconnect pillar 100, the multi-layer interconnect pillar comprising:
a base reinforcement layer 1102 (see, e.g., para.0041);
a cap reinforcement layer 1201 (see, e.g., para.0046);
and a solder layer 112 (see, e.g., para.0042) disposed between the base reinforcement layer and the cap reinforcement layer .
Regarding Claim 2, El Amrani (see, e.g., fig. 1, fig. 2a) shows the integrated device of claim 1, further comprising
one or more under bump metallization (UBM) layers 1101 & 108 (see, e.g., para.0040) coupled to and disposed between the contact pad and the multi-layer interconnect pillar.
Regarding Claim 12, El Amrani (see, e.g., para.0041, para.0046) shows the integrated device of claim 1,
wherein the cap reinforcement layer 1201 (see, e.g., para.0046) and the base reinforcement layer 1102 (see, e.g., para.0041) comprise nickel.
Regarding Claim 13, El Amrani (see, e.g., para.0041) shows the integrated device of claim 1,
wherein the cap reinforcement layer and the base reinforcement layer comprise cobalt (see, e.g., para.0041).
Regarding Claim 14, El Amrani (see, e.g., fig. 1, fig. 2a) shows a method comprising:
forming a base reinforcement layer 1102 (see, e.g., para.0041) of a multi-layer interconnect pillar 100,
the base reinforcement layer electrically connected to a contact pad 102 (see, e.g., para.0037) of a die 106 (see, e.g., para.0038);
forming a first solder layer 112 (see, e.g., para.0042) of the multi-layer interconnect pillar,
wherein the first solder layer is disposed over the base reinforcement layer;
forming a cap reinforcement layer 1201 (see, e.g., para.0046) of the multi-layer interconnect pillar,
wherein the cap reinforcement layer is electrically connected to the contact pad by at least the base reinforcement layer and the first solder layer;
and forming a solder cap 114 (see, e.g., para.0042) of the multi-layer interconnect pillar,
wherein the solder cap is disposed over the cap reinforcement layer.
Regarding Claim 17, El Amrani (see, e.g., fig. 2a, fig. 3a) shows the method of claim 14, further comprising,
before forming the base reinforcement layer, forming one or more under bump metallization (UBM) layers 1101 & 108 (see, e.g., para.0040),
wherein at least one of the one or more UBM layers contacts the contact pad.
Regarding Claim 23, El Amrani (see, e.g., fig. 1, fig. 2a) shows a device comprising:
a substrate 104 including an interface (see, e.g., para.0038);
a die 106 (see, e.g., para.0038) including a contact pad 102 (see, e.g., para.0037);
a multi-layer interconnect pillar 100 disposed between the substrate and the die and electrically connected to the contact pad, the multi-layer interconnect pillar comprising:
a base reinforcement layer 1102 (see, e.g., para.0041);
a cap reinforcement layer 1201 (see, e.g., para.0046);
and a solder layer 112 (see, e.g., para.0042) disposed between the base reinforcement layer and the cap reinforcement layer;
and a solder cap 114 (see, e.g., para.0042) electrically connected to the multi-layer interconnect pillar and to the interface.
Regarding Claim 24, El Amrani (see, e.g., fig. 1, fig. 2a) shows the device of claim 23, further comprising
one or more under bump metallization (UBM) layers 1101 & 108 (see, e.g., para.0040) coupled to and disposed between the contact pad and to the multi-layer interconnect pillar.
Regarding Claim 30, El Amrani (see, e.g., para.0041, para.0046) shows the device of claim 23,
wherein the cap reinforcement layer 1201 and the base reinforcement layer 1102 comprise nickel, cobalt, or both (see, e.g., para.0041, para.0046).
Claims 10 & 11 are rejected under 35 U.S.C. 103 as being unpatentable over El Amrani (US 20240113060) in view of Brun (US 20220375844).
Regarding Claim 10, El Amrani (see, e.g., para.0037) shows the integrated device of claim 1,
wherein the contact pad is one of a plurality of contact pads of the die,
and the solder cap is one of a plurality of solder caps,
wherein each of the plurality of solder caps is electrically connected to a respective one of the plurality of contact pads,
and wherein a pitch of the plurality of solder caps is less than 150 micrometers.
El Amrani, however, fails to show a range of the pitch less than 150 micrometers. However, ranges of pitch will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such ranges are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Brun (see, e.g., fig. 2, para.0046-0047), in a similar device to El Amrani, shows a pitch of a plurality of solder caps from .7 micrometers to 100 micrometers. Since the applicant has not established the criticality (see next paragraph below) of the claimed pitch range, and similar ranges have been used in the art, it would have been obvious to one of ordinary skill in the art to use the ranges of the pitch of Brun in the device of El Amrani as an obvious range for the pitch of the plurality of solder caps.
Criticality
The specification contains no disclosure of either the critical nature of the claimed temperature and pressure ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding Claim 11, El Amrani, in view of Brun (see, e.g., fig. 2, para.0046-0047), shows the integrated device of claim 10,
wherein the pitch is less than 130 micrometers.
Brun (see, e.g., fig. 2, para.0046-0047), in a similar device to El Amrani, shows a pitch of a plurality of solder caps from .7 micrometers to 100 micrometers. The criticality rejection of claim 11 applies to claim 10, see paragraphs 17-19 above.
Claims 1, 3, 4, 5, 14, 18, 19, & 20 are rejected under 35 U.S.C. 103 as being unpatentable over Arvin (US 20140262458) in view of Jin (US 20030219966).
Regarding Claim 1, Arvin (see, e.g., fig. 2) shows an integrated device comprising:
a die (electrical components in substrate, see, e.g., para.0019) having a contact pad 10 (see, e.g., para.0019);
and a solder cap 30 (see, e.g., para.0042) electrically connected to the contact pad by a multi-layer interconnect pillar 100, the multi-layer interconnect pillar comprising:
a base reinforcement layer 17 (see, e.g., para.0029);
a cap reinforcement layer 22 (see, e.g., para.0039);
and a layer 20 (see, e.g., para.0030) disposed between the base reinforcement layer and the cap reinforcement layer .
Arvin (see, e.g., fig. 2, para.0030) states layer 20 is a copper conductor layer.
Arvin, however, fails to show
and a solder layer disposed between the base reinforcement layer and the cap reinforcement layer.
Jin (see, e.g., fig. 11, para.0051), in a similar device to Arvin, teaches that a configuration wherein a solder layer is a suitable material and obvious substitution for the copper conductor layer of a multi-layer interconnect pillar.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the solder layer of Jin in the device of Arvin as a suitable material and substitution for layer 20 disposed between the base reinforcement layer and the cap reinforcement layer.
Regarding Claim 3, Arvin (see, e.g., fig. 2), in view of Jin, shows the integrated device of claim 1, further comprising
a barrier layer 24 (see, e.g., para.0041) coupled to and disposed between the solder cap and the multi-layer interconnect pillar .
Regarding Claim 4, Arvin (see, e.g., fig. 2, para.0030), in view of Jin, shows the integrated device of claim 3,
wherein a material of the solder cap forms Intermetallic compounds (IMCs) with a material of the barrier layer 24 at a first rate,
wherein the material of the solder cap forms IMCs with a material of the cap reinforcement layer 22 at a second rate,
and wherein the first rate is greater than the second rate.
Arvin (see, e.g., para.0030) states the IMC reaction rate of nickel, the material of cap reinforcement layer 22, is less than the IMC reaction rate of copper, the material of barrier layer 24.
Regarding Claim 5, Arvin (see, e.g., fig. 2), in view of Jin, shows the integrated device of claim 3,
wherein the barrier layer comprises copper (see, e.g., para.0041).
Regarding Claim 14, Arvin (see, e.g., fig. 2) shows a method comprising:
forming a base reinforcement layer 17 (see, e.g., para.0029) of a multi-layer interconnect pillar,
the base reinforcement layer electrically connected to a contact pad 10 (see, e.g., para.0019) of a die (electrical components in substrate not shown, see, e.g., para.0019);
forming a first layer 20 (see, e.g., para.0039) of the multi-layer interconnect pillar,
wherein the first layer is disposed over the base reinforcement layer;
forming a cap reinforcement layer 22 (see, e.g., para.0039) of the multi-layer interconnect pillar,
wherein the cap reinforcement layer is electrically connected to the contact pad by at least the base reinforcement layer and the first layer;
and forming a solder cap 30 (see, e.g., para.0042) of the multi-layer interconnect pillar,
wherein the solder cap is disposed over the cap reinforcement layer.
Arvin (see, e.g., fig. 2, para.0030) states layer 20 is a copper conductor layer.
Arvin, however, fails to show
forming a first solder layer 20 (see, e.g., para.0039) of the multi-layer interconnect pillar,
wherein the first solder layer is disposed over the base reinforcement layer;
wherein the cap reinforcement layer is electrically connected to the contact pad by at least the base reinforcement layer and the first solder layer;
Jin (see, e.g., fig. 11, para.0051), in a similar device to Arvin, teaches that a configuration wherein a solder layer is a suitable material and substitution for the copper conductor layer of a multi-layer interconnect pillar.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the solder layer of Jin in the device of Arvin as a suitable material and obvious substitution for layer 20.
Regarding Claim 18, Arvin (see, e.g., fig. 2), in view of Jin, shows the method of claim 14, further comprising,
before forming the solder cap (see, e.g., para.0042), forming one or more barrier layers 24 (see, e.g., para.0041),
wherein at least one of the one or more barrier layers contacts the cap reinforcement layer 22 (see, e.g., fig. 2).
Regarding Claim 19, Arvin (see, e.g., fig. 2, para.0024), in view of Jin, shows the method of claim 14, further comprising:
forming a photoresist layer (photoresist etch mask) on the die;
and patterning the photoresist layer to form an opening(trench of 14 & 12, see, e.g., para.0024) exposing the contact pad,
wherein the base reinforcement layer, the first solder layer, the cap reinforcement layer, and a solder layer of the solder cap are formed in the opening (see, e.g., fig. 2).
Regarding Claim 20, Arvin (see, e.g., fig. 2, para.0043), in view of Jin, shows the method of claim 19, further comprising,
after forming at least the base reinforcement layer, the first solder layer, the cap reinforcement layer, and the solder layer of the solder cap in the opening,
stripping the photoresist layer from the die to expose the multi-layer interconnect pillar (see, e.g., para.0043).
Claims 23, 25, 26, & 27 are rejected under 35 U.S.C. 103 as being unpatentable over Arvin (US 20140262458) in view of Jadhav (US 20090095502) and further in view of Jin (US 20030219966).
Regarding Claim 23, Arvin (see, e.g., fig. 2) shows a device comprising:
a die (electrical components in substrate, see, e.g., para.0019) including a contact pad 10 (see, e.g., para.0019);
a multi-layer interconnect pillar 100 electrically connected to the contact pad (see, e.g., para.0053), the multi-layer interconnect pillar comprising:
a base reinforcement layer 17 (see, e.g., para.0029);
a cap reinforcement layer 22 (see, e.g., para.0039);
and a layer 20 (see, e.g., para.0020) disposed between the base reinforcement layer and the cap reinforcement layer;
and a solder cap 30 (see, e.g., para.0042) electrically connected to the multi-layer interconnect pillar.
Arvin, however, fails to show
a substrate including an interface;
the multi-layer interconnect pillar 100 disposed between the substrate and the die
and the solder cap 30 electrically connected to the multi-layer interconnect pillar and to the interface
Jadhav (see, e.g., fig. 5, para.0051-0053), in a similar device to Arvin, shows a substrate including an interface 50 & 70, a multi-layer interconnect pillar 10 disposed between the substrate and the die 60, and the solder cap 22 electrically connected to the multi-layer interconnect pillar 10 and to the interface 50 & 70.
The multi-layer interconnect pillars of Arvin and Jadhav have the same function of providing electrical and physical connections between devices. The device of Arvin would operate in the same manner as Jadhav were it to be connected to a substrate. Therefore, the results of combining the substrate of Jadhav into the device of Arvin would be predictable to one of ordinary skill in the art.
It would have been obvious to one or ordinary skill in the art to connect the device and multi-layer interconnect pillar of Arvin to the substrate of Jadhav as being no more than the predictable use of prior art elements according to their established functions.
Arvin (see, e.g., fig. 2, para.0030), in view of Jadhav, states layer 20 is a copper conductor layer.
Arvin, in view of Jadhav, however, fails to show
and a solder layer disposed between the base reinforcement layer and the cap reinforcement layer.
Jin (see, e.g., fig. 11, para.0051), in a similar device to Arvin, in view of Jadhav, teaches that a configuration wherein a solder layer is a suitable material and obvious substitution for the copper conductor layer of a multi-layer interconnect pillar.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the solder layer of Jin in the device of Arvin, in view of Jadhav, as a suitable material and substitution for layer 20 disposed between the base reinforcement layer and the cap reinforcement layer.
Regarding Claim 25, Arvin (see, e.g., fig. 2), in view of Jadhav and further in view of Jin, shows the device of claim 23, further comprising
a barrier layer 24 (see, e.g., para.0041) coupled to and disposed between the solder cap and the multi-layer interconnect pillar.
Regarding Claim 26, Arvin (see, e.g., fig. 2), in view of Jadhav and further in view of Jin, shows the device of claim 25,
wherein a material of the solder cap forms Intermetallic compounds (IMCs) with a material of the barrier layer 24 at a first rate,
wherein the material of the solder cap forms IMCs with a material of the cap reinforcement layer 22 at a second rate,
and wherein the first rate is greater than the second rate.
Arvin (see, e.g., para.0030) states the IMC reaction rate of nickel, the material of cap reinforcement layer 22, is less than the IMC reaction rate of copper, the material of barrier layer 24.
Regarding Claim 27, Arvin (see, e.g., fig. 2), in view of Jadhav and further in view of Jin, shows the device of claim 25,
wherein the barrier layer 24 comprises copper (see, e.g., para.0041).
Claims 1, 6, 7, 8, 14, 15, 16, 21, 22, 23, 28, & 29 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jadhav (US 20090095502).
Regarding Claim 1, Jadhav (see, e.g., fig. 2, fig. 5) shows an integrated device comprising:
a die 60 (see, e.g., para.0051) having a contact pad 12 (see, e.g., para.0018);
and a solder cap 22 (see, e.g., para.0025) electrically connected to the contact pad by a multi-layer interconnect pillar 10, the multi-layer interconnect pillar comprising:
a base reinforcement layer 16a (see, e.g., para.0020);
a cap reinforcement layer 16c (see, e.g., para.0034);
and a solder layer 18a (see, e.g., para.0020) disposed between the base reinforcement layer and the cap reinforcement layer.
Regarding Claim 6, Jadhav (see, e.g., fig. 2) shows the integrated device of claim 1,
wherein the multi-layer interconnect pillar further comprises:
one or more intermediate reinforcement layers 16b (see, e.g., para.0025) disposed between the cap reinforcement layer and the base reinforcement layer;
and one or more additional solder layers 18b (see, e.g., para.0031),
wherein solder layers and reinforcement layers alternate in the multi-layer interconnect pillar.
Regarding Claim 7, Jadhav (see, e.g., fig. 2) shows the integrated device of claim 6,
wherein each of the one or more additional solder layers 18b has a thickness between 5 micrometers to 20 micrometers (see, e.g., para.0032).
Regarding Claim 8, Jadhav (see, e.g., fig. 2) shows the integrated device of claim 1,
wherein the multi-layer interconnect pillar further comprises a copper pillar 14 (see, e.g., para.0019) between the base reinforcement layer and the contact pad.
Although Jadhav (see, e.g., para.0019) states element 14 is a seed layer, said element satisfies the limitations of “a copper pillar” since the structure of 14 can be considered a pillar, and its material is made of copper.
Regarding Claim 14, Jadhav (see, e.g., fig. 2, fig. 5) shows a method comprising:
forming a base reinforcement layer 16a (see, e.g., para.0020) of a multi-layer interconnect pillar 10,
the base reinforcement layer electrically connected to a contact pad 12 (see, e.g., para.0018) of a die 60 (see, e.g., para.0051);
forming a first solder layer 18a (see, e.g., para.0020) of the multi-layer interconnect pillar,
wherein the first solder layer is disposed over the base reinforcement layer;
forming a cap reinforcement layer 16c (see, e.g., para.0034) of the multi-layer interconnect pillar,
wherein the cap reinforcement layer is electrically connected to the contact pad by at least the base reinforcement layer and the first solder layer;
and forming a solder cap 22 (see, e.g., para.0025) of the multi-layer interconnect pillar,
wherein the solder cap is disposed over the cap reinforcement layer.
Regarding Claim 15, Jadhav (see, e.g., fig. 2) shows the method of claim 14, further comprising:
forming one or more additional reinforcement layers 16b (see, e.g., para.0025) between the base reinforcement layer and the cap reinforcement layer;
and forming one or more additional solder layers 18b (see, e.g., para.0031) disposed between adjacent reinforcement layers.
Regarding Claim 16, Jadhav (see, e.g. fig. 2) shows the method of claim 14, further comprising
forming a copper pillar 14 (see, e.g., para.0019) of the multi-layer interconnect pillar,
wherein the copper pillar is disposed over the contact pad.
Regarding Claim 21, Jadhav (see, e.g., fig. 5) shows the method of claim 14, further comprising,
after forming at least the base reinforcement layer, the first solder layer, the cap reinforcement layer, and the solder cap,
applying heat to the multi-layer interconnect pillar sufficient to soften the solder cap and one or more solder layers of the multi-layer interconnect pillar (see, e.g., para.0051, para.0052),
wherein reinforcement layers of the multi-layer interconnect pillar limit deformation of the multi-layer interconnect pillar due to heating (see, e.g., para.0033, para.0053).
Regarding Claim 22, Jadhav (see, e.g., fig. 5, para.0051-0053) shows the method of claim 14, further comprising,
after forming at least the base reinforcement layer, the first solder layer, the cap reinforcement layer, and the solder cap,
attaching the solder cap to another device 50 & 70 (see, e.g., para.0052) to electrically connect the other device and the contact pad.
Regarding Claim 23, Jadhav (see, e.g., fig. 2, fig. 5) shows a device comprising:
a substrate 50 including an interface (see, e.g., para.0052);
a die 60 (see, e.g., para.0051) including a contact pad 12 (see, e.g., para.0018);
a multi-layer interconnect pillar 10 disposed between the substrate and the die and electrically connected to the contact pad (see, e.g., para.0053), the multi-layer interconnect pillar comprising:
a base reinforcement layer 16a (see, e.g., para.0020);
a cap reinforcement layer 16c (see, e.g., para.0034);
and a solder layer 18a (see, e.g., para.0020) disposed between the base reinforcement layer and the cap reinforcement layer;
and a solder cap 22 (see, e.g., para.0025) electrically connected to the multi-layer interconnect pillar and to the interface.
Regarding Claim 28, Jadhav (see, e.g., fig. 2, fig. 5) shows the device of claim 23,
wherein the multi-layer interconnect pillar further comprises:
a copper pillar 14 (see, e.g., para.0019),
one or more intermediate reinforcement layers 16b (see, e.g., para.0025) disposed between the cap reinforcement layer and the base reinforcement layer;
and one or more additional solder layers 18b (see, e.g., para.0031),
wherein solder layers and reinforcement layers alternate in the multi-layer interconnect pillar.
Regarding Claim 29, Jadhav (see, e.g., fig. 2, fig. 5) shows the device of claim 23,
wherein the multi-layer interconnect pillar further comprises a copper pillar 14 (see, e.g., para.0019) between the base reinforcement layer and the contact pad.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Jadhav (US 20090095502) in view of Lin (US 20100244263).
Regarding Claim 9, Jadhav shows the integrated device of claim 8,
Jadhav, however, fails to show
wherein the copper pillar has a height between 10 micrometers to 40 micrometers.
However, ranges of copper pillar height will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such ranges are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Lin (see, e.g., para.0071), in a similar device to Jadhav, shows a copper pillar with a height between 5 micrometers to 50 micrometers. Since the applicant has not established the criticality (see next paragraph below) of the claimed range, and similar ranges have been used in the art, it would have been obvious to one of ordinary skill in the art to use the ranges of the copper pillar of Lin in the device of Jadhav as an obvious range for the copper pillar height. See paragraph 19 for criticality statement.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/F.R.D./ Examiner, Art Unit 2814
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814