DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 23, 2026 has been entered.
Status of Claims
Claims 1-9 are pending.
Claims 3, 6 are amended.
Claim 7-9 are new
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
Therefore, the wherein the first peripheral circuit element is electrically connected to the second peripheral circuit element through the first lower wiring structure in claim 7 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Therefore, the wherein the upper wiring layer is longer than each of the first and second lower wiring structures in claim 8 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Regarding claim 1. Claim 1 recites the limitation “a common source line positioned at the same level as the first dummy bit line and the second dummy bit line” in the claim language.
Regarding claim 6. Claim 6 recites the limitation “a common source line positioned at the same level as the first and the second main bit lines and the first and second dummy bit lines” in the claim language.
Regarding claim 7. Claim 7 recites the limitation “wherein the first peripheral circuit element is electrically connected to the second peripheral circuit element through the first lower wiring structure” in the claim language.
Regarding claim 8. Claim 8 recites the limitation “wherein the upper wiring layer is longer than each of the first and second lower wiring structures” in the claim language.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 7-9 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 7. Claim 7 recites the limitation “wherein the first peripheral circuit element is electrically connected to the second peripheral circuit element through the first lower wiring structure” in the claim language.
Applicant does not have written support in the originally filed specifications for wherein the upper wiring layer is longer than each of the first and second lower wiring structures.
Claims 8-9 are rejected for dependence upon a 112(a) rejected instance claim.
Regarding claim 8. Claim 8 recites the limitation “wherein the upper wiring layer is longer than each of the first and second lower wiring structures” in the claim language.
Applicant does not have written support in the originally filed specifications for wherein the upper wiring layer is longer than each of the first and second lower wiring structures.
Claim 9 rejected for dependence upon a 112(a) rejected instance claim.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 6-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1. Claim 1 recites the limitation "the same level" in the last paragraph of the claim language. There is insufficient antecedent basis for this limitation in the claim.
Claims 2-4, 7-9 are rejected for dependence upon a 112(b) rejected instance claim.
Regarding claim 3. Claim 3 recites the limitation "the upper wiring layer" in the last paragraph of the claim language. There is insufficient antecedent basis for this limitation in the claim.
Claims 2-4, 7-9 are rejected for dependence upon a 112(b) rejected instance claim.
Regarding claim 6. Claim 6 recites the limitation "the same level" in the last paragraph of the claim language. There is insufficient antecedent basis for this limitation in the claim
Regarding claim 6. Claim 6 recites the limitation "the first and second main bit lines" in the last paragraph of the claim language. There is insufficient antecedent basis for this limitation in the claim
Regarding claim 6. Claim 6 recites the limitation "the first and second dummy bit lines" in the last paragraph of the claim language. There is insufficient antecedent basis for this limitation in the claim.
Regarding claim 6. Claim 6 recites the limitation "positioned at the same level as the first and the second main bit lines and the first and second dummy bit lines; wherein the first dummy bit line is disposed between the first bit line and the common source line, and wherein the second dummy bit line is disposed between the second bit line and the common source line" in the claim language. There is insufficient antecedent basis for this limitation in the claim.
Regarding claim 6. Claim 6 recites the limitation “positioned at the same level as the first and the second main bit lines and the first and second dummy bit lines, wherein the first dummy bit line is disposed between the first bit line and the common source line, and wherein the second dummy bit line is disposed between the second bit line and the common source line” in the claim language.
It is unclear what applicant is attempting to claim as applicant has not claimed a structure that have the first and second main bit lines, nor the first and second dummy bit lines. Applicant has only positively claimed first and second main channel films and first and second channel films.
It is unclear to the examiner if the first and second main bit lines, and the first and second dummy bit lines refers to the same structure as the first and second main channel films and first and second channel films or if they are a different structure.
Regarding claim 7. Claim 7 recites the limitation "where the peripheral circuit elements comprise: a first peripheral circuit element, a second peripheral circuit element" in the first five lines of the claim language.
Claim 7 depends upon claim 2 which depends upon independent claim 1.
Independent claim 1 states where the peripheral circuit elements comprise: a first peripheral circuit element, a second peripheral circuit element.
It is unclear to the examiner if a first peripheral circuit element, a second peripheral circuit element in claim 7 is the same as a first peripheral circuit element, a second peripheral circuit element in claim 1 or different a first peripheral circuit element, a second peripheral circuit element.
Claims 8-9 are rejected for dependence upon a 112(b) rejected instance claim.
Claim Rejections - 35 USC § 102
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 5 is rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Shin et al (U.S. 2015/0129878).
Regarding claim 5. Shin et al discloses A semiconductor memory device with a three-dimensional (3D) structure (FIG. 1A-1C; [0140]), comprising:
a cell region (FIG. 1A, item I) arranged over a substrate (FIG. 1B, item 110), including a cell structure (FIG. 1B, items 191-198), wherein the cell structure (FIG. 1B, items 191-198) includes a plurality of cell gate conductive films (FIG. 1B, items 194, 196) and a plurality of insulation films (FIG. 1B, items 193, 195) alternately stacked over the substrate (FIG. 1B, item 110);
an upper wiring structure (FIG. 1B, item 230) arranged over the cell region (FIG. 1A, item I);
a peripheral circuit region disposed between the substrate and the cell region ([Abstract]);
main channel films (FIG. 1B, item 200) formed through the cell structure (FIG. 1B, items 191-198);
first (FIG. 1B, item 232) and second (annotated FIG. 1A, item 232 second dummy channel film) dummy channel films (FIG. 1A-1B, item 232) electrically coupled ([0007]) to the peripheral circuit region (FIG. 1B, item 120) through the cell structure (FIG. 1B, items 191-198); and
a fuse (FIG. 1B, item 230; [0072]) disposed over the cell region (FIG. 1A, item I) and coupled between the first (FIG. 1B, item 232) and second (annotated FIG. 1A, item 232 second dummy channel film) dummy channel films (FIG. 1A-1B, item 232), wherein the main channel films (FIG. 1B, item 200) and the first (FIG. 1B, item 120; FIG. 3B, item 254 left side) and second (annotated FIG. 1A, item 232 second dummy channel film) dummy channel films (FIG. 1A-1B, item 232) extend above ([0073]) an uppermost film (FIG. 1B, items 198) of the plurality of cell gate conductive films (FIG. 1B, items 194, 196 [0090]) and the plurality of insulation films (FIG. 1B, items 193, 195; [0089]) of the cell structure (FIG. 1B, items 191-198) relative to the substrate (FIG. 1B and 3B, item 110), and
wherein the upper wiring structure (FIG. 1B, item 230) comprises:
a first dummy bit line (annotated FIG. 1A, first dummy bit line; FIG. 1B, item 242) electrically coupled ([0073]) to the first dummy channel film (FIG. 1B, item 232);
a second dummy bit line (annotated FIG. 1A, second dummy bit line) electrically coupled ([0073]) to the second dummy channel film (annotated FIG. 1A, item 232 second dummy channel film); and an upper wiring layer (FIG. 1B, item 234) disposed over the first (annotated FIG. 1A, first dummy bit line) and second (annotated FIG. 1A, second dummy bit line) dummy bit lines, suitable for electrically coupling ([0072]) the first and second dummy bit lines (annotated FIG. 1A, first and second dummy bit lines).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al (U.S. 2015/0129878) and further in view of Cho et al (U.S. 2006/0186485).
Regarding claim 1. Shin et al discloses a semiconductor memory device with a three-dimensional (3D) structure (FIG. 1A-1C; FIG. 3A-3B; [0140]), comprising:
a cell region (FIG. 1A, item I; FIG. 3A, item V) arranged over a substrate (FIG. 1B and 3B, item 110), including a cell structure (FIG. 1B, items 191-198; FIG. 3A, items 342,348, [0090]) wherein the cell structure (FIG. 1B, items 191-198; FIG. 3A, items 342,348, [0090]) includes a plurality of cell gate conductive films (FIG. 1B, items 194, 196; FIG. 3A, item 348, [0090]) and a plurality of insulation films (FIG. 1B, items 193, 195; FIG. 3A, item 342 [0090]) alternately ([0089]-[0090]) stacked over the substrate (FIG. 1B and 3B, item 110);
a peripheral circuit region arranged between the substrate and the cell region ([Abstract]);
an upper wiring structure (FIG. 1B, item 230; FIG. 3B, item 230a) arranged over the cell region (FIG. 1A, item I; FIG. 3A, item V);
main channel films (FIG. 1B, item 200; FIG. 3B, items 346, 348) and dummy channel films (FIG. 1B, item 232; FIG. 3B, item 354)) formed through the cell structure (FIG. 1B, items 191-198; FIG. 3B, items 346, 348), wherein the dummy channel films (FIG. 1B, item 232; FIG. 3B, item 354)) are suitable for electrically coupling ([0072]) the upper wiring structure (FIG. 1B, item 230) and the peripheral circuit region (Abstract, i.e. peripheral circuit region on a substrate).
15wherein the main channel films (FIG. 1B, item 200; FIG. 3B, items 346, 348) and the dummy channel films (FIG. 1B, item 232) extend above an uppermost film (FIG. 1B, items 200 and 232 extend above item 198; FIG. 3B, items 342) of the plurality of cell gate conductive films (FIG. 1B, item 198 is upper most conductive film) and the plurality of insulation films (FIG. 1B, item 197 is upper most insulating film film) of the cell structure (FIG. 1B, items 191-198) relative to the substrate (FIG. 1B, item 110).
wherein the peripheral circuit region (Abstract, i.e. peripheral circuit region on a substrate) comprises:
peripheral circuit elements (FIG.1B, item 120; FIG. 3B, item 120); and
a lower wiring structure (FIG. 1B item 150; FIG. 3B item 150) suitable for electrically coupling ([0010]) the peripheral circuit elements (FIG.1B, item 120; FIG. 3B, item 120) and the dummy channel films (FIG. 1B, item 232; FIG. 3B, item 354), and
wherein the peripheral circuit elements (FIG.1B, item 120; FIG. 3B, item 120) comprise a first peripheral circuit element (FIG.1B, item 120; FIG. 3B, item 120 on left side) and a second peripheral circuit element suitable (annotated FIG. 1A, second peripheral circuit element; FIG. 3B, item 120 on right side) for receiving a signal outputted ([0007]) from the first peripheral circuit element FIG.1B, item 120; FIG. 3B, item 120), and
wherein the dummy channel films comprise:
a first dummy channel film (FIG. 1B, item 232; FIG. 1B, item first dummy channel film) suitable for electrically coupling ([0007]) the first peripheral circuit element (FIG. 3B, item 120 on left side) and the upper wiring structure (FIG. 1B, item 230; FIG. 3B, item 234); and a second dummy channel film (annotated FIG. 1A, item 232 second dummy channel film; FIG. 3B, item 354 on right) suitable for electrically coupling ([0007]) the second peripheral circuit element (FIG. 3B, item 120 on right side) and the upper wiring structure (FIG. 1B, item 230; FIG. 3B, item 234).
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Wherein the upper wiring structure (FIG. 1B, item 230; FIG. 3B, item 230a) comprises a first dummy bit line (annotated FIG. 1A, first dummy bit line; FIG. 1B, item 242; FIG. 3B, item 234 left side) electrically coupled (FIG. 3B, item 242 left side) to the first dummy channel film (FIG. 1b, item 232; FIG 3B, item 354 on left);
a second dummy bit line (annotated FIG. 1A, second dummy bit line; FIG. 3B, item 234 right side) electrically coupled (FIG. 3B, item 242 right side) to the second dummy channel film (annotated FIG. 1A, item 232 second dummy channel film, FIG. 3B, item 354 on right);
A common source line (FIG. 1A, item 222).
Shin et al fails to explicitly disclose a common source line positioned at the same level as the first dummy bit line and the second dummy bit line.
However Cho et al teaches a common source line positioned at the same level as the first dummy bit line and the second dummy bit line ([0012], i.e. the bit line contact plugs, the common source line, the peripheral gate interconnection contact plug, and the peripheral metal interconnection contact plugs may be composed of the same conductive layer formed through a same process).
Since Shin et al and Cho et al teach memory structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor memory devices as disclosed to modify Shin et al with the teachings of a common source line positioned at the same level as the first dummy bit line and the second dummy bit line as disclosed by Cho et al. The use of the bit line contact plugs, the common source line, the peripheral gate interconnection contact plug, and the peripheral metal interconnection contact plugs may be composed of the same conductive layer formed through a same process in Cho et al provides for the interconnection structure such as the plugs and the metal interconnections is simplified and thus the process of their formation is simplified (Cho et al, [Abstract]).
Regarding claim 2. Shin et al and Cho et al discloses all the limitations of the semiconductor memory device of claim 1 above.
Shin et al further discloses wherein the upper wiring structure (FIG. 1B, item 230; FIG. 3B, item 230a) comprises:
an upper wiring layer (FIG. 1B, item 234; FIG. 3B, item 234) disposed over the first (FIG. 1b, item 232; FIG. 3B, item 234 left side) and second (annotated FIG. 1A, second dummy bit line; FIG. 3B, item 234 right side) dummy bit lines (FIG. 3B, item 234), suitable for electrically coupling the first (FIG. 3B, item 234 left side) and second (annotated FIG. 1A, second dummy bit line; FIG. 3B, item 234 right side) dummy bit lines (FIG. 3B, item 234).
Regarding claim 3. Shin et al and Cho et al discloses all the limitations of the semiconductor memory device of claim 1 above.
Shin et al further discloses wherein the upper wiring layer ((FIG. 1A/1B, item 234; FIG. 3B, item 234) is extended in a direction ((FIG. 1A/1B, item Y; FIG. 3B, item X) perpendicular (FIG. 1A, item Z; FIG. 3B, item Z) to bit lines ([0009]) and the first (FIG. 3B, item 234 left side) and second (FIG. 3B, item 234 right side) dummy bit lines (FIG. 3B, item 234).
Regarding claim 4. Shin et al and Cho et al discloses all the limitations of the semiconductor memory device of claim 2 above.
Shin et al further discloses wherein the upper wiring layer (FIG. 1B, item 230; FIG. 3B, item 230a) comprises a fuse (FIG. 1B, item 230; FIG. 3B, item 234; [0072]).
Regarding claim 6. Shin et al discloses A semiconductor memory device with a three-dimensional (3D) structure (FIG. 1A-1C; FIG. 3A-3B; [0140]), comprising:
a cell region (FIG. 1A, item I; FIG. 3A, item V) arranged over a substrate (FIG. 1B and 3B, item 110), including a cell structure (FIG. 1B, items 191-198; FIG. 3B, items 346, 348),
a peripheral circuit region disposed between the substrate and the cell region ([Abstract]);
a first and second main channel films (FIG. 1B, item 200; FIG. 3B, items 346, 348) formed through the cell structure (FIG. 1B, items 191-198; FIG. 3B, items 346, 348);
first (FIG. 1B, item 232; FIG. 1B, item first dummy channel film) and second (annotated FIG. 1A, item 232 second dummy channel film; FIG. 3B, item 354 on right)) dummy channel films (FIG. 1B, item 232; FIG. 3B, item 254) electrically coupled ([0007]) to the peripheral circuit region (FIG. 3B, item 120) through the cell structure (FIG. 1B, items 191-198; FIG. 3B, items 346, 348);
a fuse disposed (FIG. 1A-1B, item 230; FIG. 3A-3B, item 234) over the cell region (FIG. 1A, item I; FIG. 3A, item V) and coupled ([0072]) between the first (FIG. 3B, item 254 left side) and second (FIG. 3B, item 254 right side) dummy channel films (FIG. 3B, item 254); and
a common source line (FIG. 1B, item 172 above 130, [0079]);
wherein the first dummy bit line (FIG. 1B, item 232; FIG. 3B, item 254 left side) is disposed between the first bit line (FIG. 1B, item 200) and the common source line (FIG. 1B, item 172 above 130, [0079]), and wherein the second dummy bit line (FIG. 3B, item 254) is disposed between the second bit line (FIG. 1B, item 200) and the common source line (FIG. 1B, item 172 above 130, [0079])
Shin et al fails to explicitly disclose a common source line positioned at the same level as the first dummy bit line and the second dummy bit line.
However Cho et al teaches a common source line positioned at the same level as the first and the second main bit lines and the first and second dummy bit lines
([0012], i.e. the bit line contact plugs, the common source line, the peripheral gate interconnection contact plug, and the peripheral metal interconnection contact plugs may be composed of the same conductive layer formed through a same process).
Since Shin et al and Cho et al teach memory structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor memory devices as disclosed to modify Shin et al with the teachings of a common source line positioned at the same level as the first and the second main bit lines and the first and second dummy bit lines as disclosed by Cho et al. The use of the bit line contact plugs, the common source line, the peripheral gate interconnection contact plug, and the peripheral metal interconnection contact plugs may be composed of the same conductive layer formed through a same process in Cho et al provides for the interconnection structure such as the plugs and the metal interconnections is simplified and thus the process of their formation is simplified (Cho et al, [Abstract]).
Regarding claim 7. Shin et al and Cho et al discloses all the limitations of the semiconductor memory device of claim 2 above.
Shin et al further discloses wherein the peripheral circuit elements (FIG.1B, item 120; FIG. 3B, item 120) comprise:
a first peripheral circuit element (annotated FIG. 1A, first peripheral circuit element; FIG.1B, item 120; FIG. 3B, item 120 on left side); and
a second peripheral circuit element (annotated FIG. 1A, second peripheral circuit element; FIG. 3B, item 120 on right side),
wherein the lower wiring structures (FIG. 1B item 150) comprise: a first lower wiring structure (annotated FIG. 1A, first lower wiring structure; FIG. 1B item 150, FIG. 3B, item 150 on left) electrically coupling ([0049]) the first peripheral circuit element annotated FIG. 1A, first peripheral circuit element; FIG.1B, item 120; FIG. 3B, item 120 on left side) and the first dummy channel film (FIG. 1B, item 232; FIG. 3B, item 254 left side); and a second lower wiring structure (annotated FIG. 1A, second lower wiring structure FIG. 3B, item 150 on right) electrically coupling ([0049]) the second peripheral circuit element (annotated FIG. 1A, second peripheral circuit element; FIG. 3B, item 120 on right side) and the second dummy channel film (annotated FIG. 1A, item 232 second dummy channel film; FIG. 3B, item 254 right side), wherein the first peripheral circuit element (annotated FIG. 1A, first peripheral circuit element; FIG.1B, item 120; FIG. 3B, item 120 on left side) is electrically connected ([0049]) to the second peripheral circuit element (annotated FIG. 1A, second peripheral circuit element; FIG. 3B, item 120 on right side) through the first lower wiring structure (annotated FIG. 1A, first lower wiring structure; FIG. 1B item 150, FIG. 3B, item 150 on left), the first dummy channel film (FIG. 1B, item 232; FIG. 3B, item 254 left side), the first dummy bit line (FIG. 1B, item 232; FIG. 3B, item 254 left side), the upper wiring layer (FIG. 1A, item 234, FIG. 3B, item 234), the second dummy bit line (annotated FIG. 1A, second dummy bit line; FIG. 3B, item 242 right side), the second dummy channel film (annotated FIG. 1A, item 232 second dummy channel film; FIG. 3B, item 254 right side), and the second lower wiring structure (annotated FIG. 1A, second lower wiring structure FIG. 3B, item 150 on right).
Regarding claim 8. Shin et al and Cho et al discloses all the limitations of the semiconductor memory device of claim 7 above.
Shin et al further discloses wherein the upper wiring layer (FIG. 1A, item 234, FIG. 3B, item 234) is longer (FIG. 1A, and 2B show item 234 or longer than item 150) than each of the first (annotated FIG. 1A, first lower wiring structure; FIG. 1B item 150, FIG. 3B, item 150 on left) and second (annotated FIG. 1A, second lower wiring structure FIG. 3B, item 150 on right) lower wiring structures (FIG. 1A, item 150, FIG. 1B, item 150)
Regarding claim 9. Shin et al and Cho et al discloses all the limitations of the semiconductor memory device of claim 8 above.
Shin et al further discloses wherein the first and second dummy bit lines comprise conductive material having a lower surface resistance than conductive material of the first and second lower wiring structures ([0010], i.e. the upper interconnection layer may include a material having a lower sheet resistance than a material of the lower interconnection layer).
Response to Arguments
Applicant's arguments filed January 23, 2026 have been fully considered but they are not persuasive.
Regarding claim 1.
On page 11 of applicant’s remarks, applicant appears to argue that Son et al fails to disclose the common source line is disposed at the same level as the first dummy bit line and the second dummy bit line.
Examiner respectfully points out that the combination of Shin et al and Cho et al discloses all the limitations of claim 1.
Regarding claim 5.
On page 13 of applicant’s remarks, applicant disagrees with applicant’s assertion. Applicant appears to argue shin fails to disclose the first dummy bit line and the second dummy bit line are separated from each other and are connected to each other through the upper wiring layer disposed above.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the first dummy bit line and the second dummy bit line are separated from each other and are connected to each other through the upper wiring layer disposed above) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Regarding claim 6.
On page 15 of applicant’s remarks, applicant disagrees with applicant’s assertion. Applicant appears to argue the prior art fails to disclose a dummy bit line is disposed between a common source line and a main bit line as recited in claim 6.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., a dummy bit line is disposed between a common source line and a main bit line) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Son et al (U.S. 2015/0041901) discloses semiconductor memory device.
Lim et al (U.S. 2016/0163732) discloses semiconductor devices.
Ahn et al (U.S. 2011/0241099) discloses semiconductor device including transistor and fuse circuit.
Owada (U.S. 2016/0064533) discloses method of manufacturing semiconductor device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT E BAUMAN whose telephone number is (469)295-9045. The examiner can normally be reached M-F, 9-5 CST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S.E.B./ Examiner, Art Unit 2815
/MONICA D HARRISON/ Primary Examiner, Art Unit 2815
Prosecution Insights