DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Species (c), (claims 1-9, 11, 13-18 and 20), in the reply
filed on 01/05/2026 is acknowledged. Non-elected claims 10,12, and 19 are withdrawn. Claims 1-20 are pending.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-9, 11, 13-18 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ),
second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, it recites the limitation “a first active pattern that extends in a first horizontal direction… …a first gate electrode that extends in a second horizontal direction…”. It is not clear a “first horizontal direction” and “second horizontal direction”. Therefore, it is indefinite. For the examination purpose, the limitation “a first active pattern that extends in a first horizontal direction… …a first gate electrode that extends in a second horizontal direction…” is interpreted as “a first active pattern that extends in a first direction… …a first gate electrode that extends in a second direction…”.
Regarding claims 2-9 and 11 those are rejected under 35 U.S.C. 112 (b), because of their dependency status from claim 1.
Regarding claim 13, it recites the limitation “a first active pattern that extends in a first horizontal direction… …a first gate electrode that extends in a second horizontal direction…”. It is not clear a “first horizontal direction” and “second horizontal direction”. Therefore, it is indefinite. For the examination purpose, the limitation “a first active pattern that extends in a first horizontal direction… …a first gate electrode that extends in a second horizontal direction…” is interpreted as “a first active pattern that extends in a first direction… …a first gate electrode that extends in a second direction…”.
Regarding claims 14-18 those are rejected under 35 U.S.C. 112 (b), because of their dependency status from claim 13.
Regarding claim 20, it recites the limitation “a first active pattern that extends in a first horizontal direction… …a first gate electrode that extends in a second horizontal direction…”. It is not clear a “first horizontal direction” and “second horizontal direction”. Therefore, it is indefinite. For the examination purpose, the limitation “a first active pattern that extends in a first horizontal direction… …a first gate electrode that extends in a second horizontal direction…” is interpreted as “a first active pattern that extends in a first direction… …a first gate electrode that extends in a second direction…”.
Then, first horizontal direction is interpretated as a first direction and second horizontal direction is interpretated as a second direction, this interpretation is applied to all examined claims of the invention.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 7-9 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20230395654 A1, hereinafter Lin) in view of Jeon et al. (US 20170110456 A1, hereinafter Jeon).
Re: Independent Claim 1, Lin discloses a semiconductor device (Fig. 3) comprising:
a substrate (102 substrate in [0022], Fig. 3);
a first active pattern (106-L fin structure at left side in [0023], Fig. 3-Annotated) that extends in a first direction (x-direction, Fig.3-Annotated) on the substrate (102);
a second active pattern (106-R fin structure at right side in [0023], Fig. 3-Annotated) that extends in the first direction (x-direction, Fig. 3-Annotated) on the substrate (102), wherein the second active pattern (106-R) is spaced apart from the first active pattern (106-L) in the first direction (x-direction, Fig. 3-Annotated);
PNG
media_image1.png
594
652
media_image1.png
Greyscale
Lin’s Figure 3-Annotated.
a first gate electrode (112-L gate structure at left side in [0024], Fig. 3-Annotated) that extends in a second direction (y-direction, Fig.3-Annotated) different from the first direction (x-direction, Fig.3-Annotated) on the first active pattern (106-L);
a second gate electrode (112-R gate structure at right side in [0024], Fig. 3-Annotated) that extends in the second direction (y-direction, Fig.3-Annotated) on the second active pattern (106-R);
a first trench (trench1 a trench to include layer 131 in [0021], Fig. 3-Annotated) that extends in the second direction (y-direction, Fig.3-Annotated) between the first gate electrode (112-L) and the second gate electrode (112-R), wherein the first trench (trench1) separates (Fig. 3-Annotated) the first active pattern (106-L) and the second active pattern (106-R), and at least part (Fig. 3-Annotated)of the first trench (trench1) is in the substrate (102);
an active cut (131 an insulating structure liner in [0021], Fig. 3-Annotated) that extends along sidewalls and a bottom surface of the first trench (trench1), wherein the active cut (131) is in contact with each of the first active pattern (106-L) and the second active pattern (106-R);
a second trench (trench2 a trench to include layer 130 in [0028], Fig. 3-Annotated) on the active cut (131) in the first trench (trench1); and
a material layer (130 insulating structure in [0028], Fig. 3-Annotated) in at least part of the second trench (trench2), wherein the material layer (130) includes an insulating material (in [0028], Fig. 3-Annotated), and wherein the material layer (130) is not in contact with each of the substrate (102), the first active pattern (106-L), and the second active pattern (106-R).
Lin does not expressly disclose a flowable material layer in at least part of the second trench, wherein the flowable material layer includes a flowable insulating material.
However, in the same semiconductor device field of endeavor, Jeon discloses a flowable material layer (143a first isolation layer in [0118], Fig. 24) in at least part of the second trench (trench a trench including 143a material in [0118], Fig. 24), wherein the flowable material layer (143a) includes a flowable insulating material ([0118], Fig. 24).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Jeon’s feature a flowable material layer in at least part of the second trench, wherein the flowable material layer includes a flowable insulating material to Lin’s device to provide a semiconductor device that has high integration and improved electrical characteristics ([0003], Jeon).
Re: Claim 7, Lin modified by Jeon discloses the semiconductor device of claim 1, further comprising: a third gate electrode (108-C nanostructured gate layers at both sides of structure 130 in [0024], Fig. 3-Annotated, Lin) on the first (106-L Fig. 3-Annotated, Lin) and second (106-R Fig. 3-Annotated, Lin) active patterns, wherein the third gate electrode (108-C Fig. 3-Annotated, Lin) extends in the second direction (y-direction, Fig.3-Annotated) between the first gate electrode (112-L Fig. 3-Annotated, Lin) and the second gate electrode (112-R Fig. 3-Annotated, Lin), and wherein the first trench (trench1 Fig. 3-Annotated, Lin) extends into the third gate electrode (108-C Fig. 3-Annotated, Lin) in a vertical direction (z-direction, Fig.3-Annotated, Lin), the vertical direction being perpendicular to the first (x-direction, Fig.3-Annotated, Lin) and second (y-direction, Fig.3-Annotated, Lin) directions.
Re: Claim 8, Lin modified by Jeon discloses the semiconductor device of claim 7, wherein sidewalls of the active cut (131, Lin) are in contact with the third gate electrode (108-C Fig. 3-Annotated, Lin).
Re: Claim 9, Lin modified by Jeon discloses the semiconductor device of claim 1, further comprising: a first plurality of nanosheets (109-L nanostructured channel layers at left side in [0023], Fig. 3-Annotated, Lin) spaced apart from one another in a vertical direction (z-direction, Fig.3-Annotated) on the first active pattern (106-L, Lin), wherein the first plurality of nanosheets (109-L, Lin) is at least partially surrounded by the first gate electrode (112-L Fig. 3-Annotated, Lin), and wherein the vertical direction (z-direction, Fig.3-Annotated) is perpendicular to the first (x-direction, Fig.3-Annotated, Lin) and second (y-direction, Fig.3-Annotated, Lin) directions; and a second plurality of nanosheets (109-R nanostructured channel layers at right side in [0023], Fig. 3-Annotated, Lin) spaced apart from one another in the vertical direction (z-direction, Fig.3-Annotated, Lin) on the second active pattern (106-R, Lin), wherein the second plurality of nanosheets (109-R, Lin) is at least partially surrounded by the second gate electrode (112-R, Fig. 3-Annotated, Lin).
Claim(s) 2-4 and 11 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lin in view of Jeon and further in view of Zang et al. (US 20200227323 A1, hereinafter Zang).
Re: Claim 2, Lin modified by Jeon discloses the semiconductor device of claim 1.
Lin modified by Jeon does not expressly disclose wherein a top surface of the flowable material layer is lower than a top surface of the active cut relative to the substrate.
PNG
media_image2.png
418
576
media_image2.png
Greyscale
Zang’s Figure 11A-Annotated.
However, in the same semiconductor device field of endeavor, Zang discloses a top surface of the material layer (228 fourth dielectric layer in [0032], Fig. 11A) is lower (Fig. 11A-Annotated) than the top surface of the active cut (226 second liner in [0032], Fig. 11A) relative to the substrate (202 substrate in [0018], Fig. 11A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Zang’s feature a top surface of the material layer is lower than the top surface of the active cut relative to the substrate to the combination of Lin and Jeon to obtain a top surface of the flowable material layer is lower than the top surface of the active cut relative to the substrate to reduce the parasitic capacitance by incorporation of low-k dielectric materials ([0002], Zang).
Re: Claim 3, Lin modified by Jeon discloses the semiconductor device of claim 1.
Lin modified by Jeon does not expressly disclose further comprising: an active cut capping pattern on the flowable material layer in the second trench, wherein the active cut capping pattern includes a material different from that of the flowable material layer.
However, in the same semiconductor device field of endeavor, Zang discloses an active cut capping pattern (230 capping layer made of SiN in [0032-0033], Fig. 11A) on the material layer (228 fourth dielectric layer in [0032], Fig. 11A) in the second trench (trench a trench including layer 228 in [0032], Fig. 11A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Zang’s feature an active cut capping pattern on the flowable material layer in the second trench to the combination of Lin and Jeon to obtain the active cut capping pattern includes a material different from that of the flowable material layer to reduce the parasitic capacitance by incorporation of low-k dielectric materials ([0002], Zang).
Re: Claim 4, Lin modified by Jeon and Zang discloses the semiconductor device of claim 3,
Lin modified by Jeon and Zang does not expressly disclose wherein a top surface of the active cut capping pattern is coplanar with a top surface of the active cut.
However, in the same semiconductor device field of endeavor, Zang discloses wherein a top surface of the active cut capping pattern (230 capping layer made of SiN in [0032-0033], Fig. 11A) is coplanar with a top surface of the active cut (226 second liner in [0032], Fig. 11A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Zang’s feature wherein a top surface of the active cut capping pattern is coplanar with a top surface of the active cut to the combination of Lin, Jeon and Zang to reduce the parasitic capacitance by incorporation of low-k dielectric materials ([0002], Zang).
Regarding claim 11, Lin modified by Jeon discloses the semiconductor device of claim 9,
Lin modified by Jeon does not disclose wherein a top surface of the flowable material layer is between a bottom surface of a lowermost nanosheet of the first plurality of nanosheets and a top surface of an uppermost nanosheet of the first plurality of nanosheets.
However, the Applicant has not presented persuasive evidence that the claimed
“top surface of the flowable material layer is between a bottom surface of a lowermost nanosheet of the first plurality of nanosheets and a top surface of an uppermost nanosheet of the first plurality of nanosheets” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed top surface of the flowable material layer is between a bottom surface of a lowermost nanosheet of the first plurality of nanosheets and a top surface of an uppermost nanosheet of the first plurality of nanosheets). Also, the applicant has not shown that the claimed “difference of top surface of the flowable material layer is between a bottom surface of a lowermost nanosheet of the first plurality of nanosheets and a top surface of an uppermost nanosheet of the first plurality of nanosheets” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Lin discloses “a top surface of a dielectric material 130 above the plurality of nanosheets, Fig. 3” and Zang discloses “a top surface of a dielectric layer 228 below a top gate layer 232, Fig. 11A”, therefore, the position of the top surface of the flowable material is a result effective variable. It has been held that is not inventive to discover the optimum position of the top surface of the flowable material by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a top surface of the flowable material layer is between a bottom surface of a lowermost nanosheet of the first plurality of nanosheets and a top surface of an uppermost nanosheet of the first plurality of nanosheets to reduce the parasitic capacitance by incorporation of low-k dielectric materials ([0002], Zang).
Claim(s) 5 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lin in view of Jeon in view of Zang and further in view of Yu et al. (US 20200152736 A1, hereinafter Yu).
Re: Claim 5, Lin modified by Jeon and Zang discloses the semiconductor device of claim 3,
Lin modified by Jeon and Zang does not expressly disclose further comprising: an airgap between a top surface of the flowable material layer and a bottom surface of the active cut capping pattern in the second trench.
PNG
media_image3.png
350
400
media_image3.png
Greyscale
Yu’s Figure 10A-Annotated.
However, in the same semiconductor device field of endeavor, Yu discloses further comprising: an airgap (182 air gap in [0038], Fig. 10A) between a top surface of the material layer (160 liner in [0037], Fig. 10A) and a bottom surface of the active cut capping pattern (170 sealing layer in [0038], Fig. 10A) in the second trench (162 gate cut isolation opening in [0037], Fig. 10A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Yu’s feature further comprising: an airgap between a top surface of the flowable material layer and a bottom surface of the active cut capping pattern in the second trench to the combination of Lin, Jeon and Zang to obtain an airgap between the top surface of the flowable material layer and a bottom surface of the active cut capping pattern in the active cut to create a gate cut isolation that provides an electrical isolation ([0003], Yu).
Claim(s) 6 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lin in view of Jeon and further in view of Chuang et al. (US 20220037315 A1, hereinafter Chuang)
Re: Claim 6, Lin modified by Jeon discloses the semiconductor device of claim 1,
Lin modified by Jeon does not expressly disclose further comprising: a gate capping pattern that extends in the second direction on a top surface of the first gate electrode, wherein a top surface of the active cut is coplanar with a top surface of the gate capping pattern.
PNG
media_image4.png
406
266
media_image4.png
Greyscale
Chuang’s Figure 10A-Annotated.
However, in the same semiconductor device field of endeavor, Chuang discloses a gate capping pattern (331 a material layer over gate 329-312 in [0036], Figs. 3A,10A) that extends in the second direction (y-direction, Figs. 3A,10A-Annotated) on a top surface of the first gate electrode (329-312 metal layers in [0037], Figs. 3A,10A), wherein a top surface of the active cut (1002 a isolation nitride layer in [0046], Figs. 3A,10A) is coplanar with a top surface (Figs. 3A,10A-Annotated) of the gate capping pattern (331).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Chuang’s feature a gate capping pattern that extends in the second direction on a top surface of the first gate electrode, wherein a top surface of the active cut is coplanar with a top surface of the gate capping pattern to the combination of Lin and Jeon to provide the desired scaling and increased density for multi-gate devices in advanced technology nodes ([0003], Chuang).
Claim(s) 13-15, 17 and 18 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20230395654 A1, hereinafter Lin) in view of Chuang et al. (US 20220037315 A1, hereinafter Chuang) in view of Jeon et al. (US 20170110456 A1, hereinafter Jeon) and further in view of Zang (US 20200227323 A1, hereinafter Zang).
Re: Independent Claim 13, Lin discloses a semiconductor device (Fig. 3) comprising:
a substrate (102 substrate in [0022], Fig. 3);
a first active pattern (106-L fin structure at left side in [0023], Fig. 3-Annotated) that extends in a first direction (x-direction, Fig.3-Annotated) on the substrate (102);
a second active pattern (106-R fin structure at right side in [0023], Fig. 3-Annotated) that extends in the first direction (x-direction, Fig. 3-Annotated) on the substrate (102), wherein the second active pattern (106-R) is spaced apart from the first active pattern (106-L) in the first direction (x-direction, Fig. 3-Annotated);
a first gate electrode (112-L gate structure at left side in [0024], Fig. 3-Annotated) that extends in a second direction (y-direction, Fig.3-Annotated) different from the first direction (x-direction, Fig.3-Annotated) on the first active pattern (106-L);
an active cut (131 an insulating structure liner in [0021], Fig. 3-Annotated) spaced apart from the first gate electrode (112-L) in the first direction (x-direction, Fig. 3-Annotated), wherein the active cut (131) separates the first active pattern (106-L) and the second active pattern (106-R), wherein the active cut (131) is in contact with each of the first active pattern (106-L) and the second active pattern (106-R), at least part of the active cut (131) is in the substrate (102);
a material layer (130 insulating structure in [0028], Fig. 3-Annotated) in the active cut (131), wherein the material layer (130) includes an insulating material (in [0028], Fig. 3-Annotated), and wherein the material layer (130) is not in contact with each of the substrate (102), the first active pattern (106-L), and the second active pattern (106-R).
Lin does not expressly disclose a gate capping pattern that extends in the second direction on a top surface of the first gate electrode; a top surface of the active cut is coplanar with a top surface of the gate capping pattern; a flowable material layer in the active cut, wherein the flowable material layer includes a flowable insulating material; and a top surface of the flowable material layer is lower than the top surface of the active cut relative to the substrate; and an active cut capping pattern on the flowable material layer in the active cut, wherein the active cut capping pattern includes a material different from that of the flowable material layer.
However, in the same semiconductor device field of endeavor, Chuang discloses a gate capping pattern (331 a material layer over gate 329-312 in [0036], Figs. 3A,10A) that extends in the second direction (y-direction, Figs. 3A,10A-Annotated) on a top surface of the first gate electrode (329-312 metal layers in [0037], Figs. 3A,10A) and a top surface of the active cut (1002 a isolation nitride layer in [0046], Figs. 3A,10A) is coplanar with a top surface (Figs. 3A,10A-Annotated) of the gate capping pattern (331).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Chuang’s feature a gate capping pattern that extends in the second direction on a top surface of the first gate electrode; a top surface of the active cut is coplanar with a top surface of the gate capping pattern to Lin’s device to provide the desired scaling and increased density for multi-gate devices in advanced technology nodes ([0003], Chuang).
Still, Lin modified by Chuang does not expressly disclose a flowable material layer in the active cut, wherein the flowable material layer includes a flowable insulating material; and a top surface of the flowable material layer is lower than the top surface of the active cut relative to the substrate; and an active cut capping pattern on the flowable material layer in the active cut, wherein the active cut capping pattern includes a material different from that of the flowable material layer.
However, in the same semiconductor device field of endeavor, Jeon discloses a flowable material layer (143a first isolation layer in [0118], Fig. 24) in the active cut (142 a capping layer in [0135], Fig. 24), wherein the flowable material layer (143a) includes a flowable insulating material (in [0118], Fig. 24).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Jeon’s feature a flowable material layer in the active cut, wherein the flowable material layer includes a flowable insulating material to the combination of Lin and Chuang to provide a semiconductor device that has high integration and improved electrical characteristics ([0003], Jeon).
Still, Lin modified by Chuang and Jeon does not expressly disclose a top surface of the flowable material layer is lower than the top surface of the active cut relative to the substrate; and an active cut capping pattern on the flowable material layer in the active cut, wherein the active cut capping pattern includes a material different from that of the flowable material layer.
However, in the same semiconductor device field of endeavor, Zang discloses a top surface of the material layer (228 fourth dielectric layer in [0032], Fig. 11A) is lower than the top surface of the active cut (226 second liner in [0032], Fig. 11A) relative to the substrate (202 substrate in [0018], Fig. 11A); and an active cut capping pattern (230 capping layer in [0032], Fig. 11A) on the material layer (228, Fig. 11A) in the active cut (226, Fig. 11A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Zang’s feature a top surface of the material layer is lower than the top surface of the active cut relative to the substrate; and an active cut capping pattern on the material layer in the active cut to the combination of Lin, Chuang and Jeon to obtain a top surface of the flowable material layer is lower than the top surface of the active cut relative to the substrate; and an active cut capping pattern on the flowable material layer in the active cut, wherein the active cut capping pattern includes a material different from that of the flowable material layer to reduce the parasitic capacitance by incorporation of low-k dielectric materials ([0002], Zang).
Re: Claim 14, Lin modified by Chuang, Jeon and Zang discloses the semiconductor device of claim 13,
Lin modified by Chuang, Jeon and Zang does not expressly disclose wherein a bottom surface of the active cut capping pattern is lower than a bottom surface of the gate capping pattern relative to the substrate.
However, in the same semiconductor device field of endeavor, Zang discloses a bottom surface of the active cut capping pattern (230 capping layer in [0032], Fig. 11A) is lower than a bottom surface of the gate capping pattern (232-top a top layer in the top gate structure 232 in [0034], Fig. 11A) relative to the substrate (202 substrate in [0018], Fig. 11A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Zang’s feature wherein a bottom surface of the active cut capping pattern is lower than a bottom surface of the gate capping pattern relative to the substrate to the combination of Lin, Chuang, Jeon and Zang to reduce the parasitic capacitance by incorporation of low-k dielectric materials ([0002], Zang).
Re: Claim 15, Lin modified by Chuang, Jeon and Zang discloses the semiconductor device of claim 13, wherein at least part of the flowable material layer (143a’s Jeon applied to 130’s Lin Fig. 3-Annotated, Lin) is in the substrate (102 Fig. 3-Annotated, Lin).
Re: Claim 17, Lin modified by Chuang, Jeon and Zang discloses the semiconductor device of claim 13, further comprising: a second gate electrode (112-R gate structure at right side in [0024], Fig. 3-Annotated, Lin) spaced apart from the first gate electrode (112-L Fig. 3-Annotated, Lin) in the first direction (x-direction, Fig. 3-Annotated, Lin), wherein the second gate electrode (112-R Fig. 3-Annotated, Lin) extends in the second direction (y-direction, Fig. 3-Annotated, Lin) on the first (106-L Fig. 3-Annotated, Lin) and second (106-R Fig. 3-Annotated, Lin) active patterns, and wherein the second gate electrode (112-R Fig. 3-Annotated, Lin) is in contact with sidewalls of the active cut (131 Fig. 3-Annotated, Lin) in the first direction (x-direction, Fig. 3-Annotated, Lin).
Re: Claim 18, Lin modified by Chuang, Jeon and Zang discloses the semiconductor device of claim 13, further comprising: a first plurality of nanosheets (109-L nanostructured channel layers at left side in [0023], Fig. 3-Annotated, Lin) spaced apart from one another in a vertical direction (z-direction, Fig. 3-Annotated, Lin) on the first active pattern (106-L Fig. 3-Annotated, Lin), wherein the first plurality of nanosheets (109-L Fig. 3-Annotated, Lin) is at least partially surrounded by the first gate electrode (112-L Fig. 3-Annotated, Lin), and wherein the vertical direction (z-direction, Fig. 3-Annotated, Lin) is perpendicular to the first (x-direction, Fig.3-Annotated, Lin) and second (y-direction, Fig.3-Annotated, Lin) directions; and a second plurality of nanosheets (109-C nanostructured channel layers at both sides of structure 130 in [0023], Fig. 3-Annotated, Lin) spaced apart from one another in the vertical direction (z-direction, Fig. 3-Annotated, Lin) on the first (106-L, Lin) and second (106-R, Lin) active patterns, wherein the second plurality of nanosheets (109-C Fig. 3-Annotated, Lin) is in contact with sidewalls of the active cut (131 Fig. 3-Annotated, Lin) in the first direction (x-direction, Fig. 3-Annotated, Lin).
Claim(s) 16 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lin in view of Chuang in view of Jeon in view of Zang and further in view of Yu et al. (US 20200152736 A1, hereinafter Yu).
Re: Claim 16, Lin modified by Chuang, Jeon and Zang discloses the semiconductor device of claim 13,
Lin modified by Chuang, Jeon and Zang does not expressly disclose further comprising: an airgap between a top surface of the flowable material layer and a bottom surface of the active cut capping pattern in the second trench.
However, in the same semiconductor device field of endeavor, Yu discloses further comprising: an airgap (182 air gap in [0038], Fig. 10A) between a top surface of the material layer (160 liner in [0037], Fig. 10A) and a bottom surface of the active cut capping pattern (170 sealing layer in [0038], Fig. 10A) in the second trench (162 gate cut isolation opening in [0037], Fig. 10A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Yu’s feature further comprising: an airgap between a top surface of the flowable material layer and a bottom surface of the active cut capping pattern in the second trench to the combination of Lin, Chuang, Jeon and Zang to obtain an airgap between the top surface of the flowable material layer and a bottom surface of the active cut capping pattern in the active cut to create a gate cut isolation that provides an electrical isolation ([0003], Yu).
Claim(s) 20 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20230395654 A1, hereinafter Lin) in view of Jeon et al. (US 20170110456 A1, hereinafter Jeon) and further in view of Zang (US 20200227323 A1, hereinafter Zang).
Re: Independent Claim 20, Lin discloses a semiconductor device (Fig. 3) comprising:
a substrate (102 substrate in [0022], Fig. 3);
a first active pattern (106-L fin structure at left side in [0023], Fig. 3-Annotated) that extends in a first direction (x-direction, Fig.3-Annotated) on the substrate (102);
a second active pattern (106-R fin structure at right side in [0023], Fig. 3-Annotated) that extends in the first direction (x-direction, Fig. 3-Annotated) on the substrate (102), wherein the second active pattern (106-R) is spaced apart from the first active pattern (106-L) in the first direction (x-direction, Fig. 3-Annotated);
a first plurality of nanosheets (109-L nanostructured channel layers at left side in [0023], Fig. 3-Annotated) spaced apart from one another in a vertical direction (z-direction, Fig.3-Annotated) perpendicular to the first direction (x-direction, Fig. 3-Annotated) on the first active pattern (106-L);
a second plurality of nanosheets (109-R nanostructured channel layers at right side in [0023], Fig. 3-Annotated) spaced apart from one another in the vertical direction (z-direction, Fig.3-Annotated) on the second active pattern (106-R);
a third plurality of nanosheets (109-C nanostructured channel layers at both sides of structure 130 in [0023], Fig. 3-Annotated) spaced apart from one another in the vertical direction (z-direction, Fig.3-Annotated) on the first (106-L) and second (106-R) active patterns;
a first gate electrode (112-L gate structure at left side in [0024], Fig. 3-Annotated) that extends in a second direction (y-direction, Fig.3-Annotated) different from the first direction (x-direction, Fig.3-Annotated) on the first active pattern (106-L), wherein the first gate electrode (112-L) at least partially surrounds the first plurality of nanosheets (109-L);
a second gate electrode (112-R gate structure at right side in [0024], Fig. 3-Annotated) that extends in the second direction (y-direction, Fig.3-Annotated) on the second active pattern (106-R), wherein the second gate electrode (112-R) at least partially surrounds the second plurality of nanosheets (109-R);
a third gate electrode (108-C nanostructured gate layers at both sides of structure 130 in [0024], Fig. 3-Annotated) that extends in the second direction (y-direction, Fig.3-Annotated) on the first (106-L) and second (106-R) active patterns, wherein the third gate electrode (108-C) at least partially surrounds the third plurality of nanosheets (109-C);
a first trench (trench1 a trench to include layer 131 in [0021], Fig. 3-Annotated) that extends into (Fig. 3-Annotated) the third gate electrode (108-C), the third plurality of nanosheets (109-C), and the substrate (108-C) in the vertical direction (z-direction, Fig.3-Annotated), wherein the first trench (trench1) extends in the second direction (y-direction, Fig.3-Annotated) between the first gate electrode (112-L) and the second gate electrode (112-R), and wherein the first trench (trench1) separates (Fig. 3-Annotated) the first active pattern (106-L) and the second active pattern (106-R);
an active cut (131 an insulating structure liner in [0021], Fig. 3-Annotated) that extends along sidewalls and a bottom surface of the first trench (trench1), wherein the active cut (131) is in contact with each of the first active pattern (106-L), the second active pattern (106-R), the third gate electrode (108-C), and the third plurality of nanosheets (109-C);
a second trench (trench2 a trench to include layer 130 in [0028], Fig. 3-Annotated) on the active cut (131) in the first trench (trench1);
a material layer (130 insulating structure in [0028], Fig. 3-Annotated) in at least part of the second trench (trench2), wherein the material layer (130) includes an insulating material (in [0028], Fig. 3-Annotated), and wherein the material layer (130) is not in contact with each of the substrate (102), the first active pattern (106-L), and the second active pattern (106-R).
Lin does not expressly disclose a flowable material layer in at least part of the second trench, wherein the flowable material layer includes a flowable insulating material; and an active cut capping pattern on the flowable material layer in the active cut, wherein the active cut capping pattern includes a material different from that of the flowable material layer.
However, in the same semiconductor device field of endeavor, Jeon discloses a flowable material layer (143a first isolation layer in [0118], Fig. 24) in at least part of the second trench (trench a trench including 143a material in [0118], Fig. 24), wherein the flowable material layer (143a) includes a flowable insulating material (in [0118], Fig. 24).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Jeon’s feature a flowable material layer in at least part of the second trench, wherein the flowable material layer includes a flowable insulating material to Lin’s device to provide a semiconductor device that has high integration and improved electrical characteristics ([0003], Jeon).
Still, Lin modified by Jeon does not expressly disclose an active cut capping pattern on the flowable material layer in the active cut, wherein the active cut capping pattern includes a material different from that of the flowable material layer.
However, in the same semiconductor device field of endeavor, Zang discloses an active cut capping pattern (230 capping layer in [0032], Fig. 11A) on the material layer (228 fourth dielectric layer in [0032], Fig. 11A) in the active cut (226 second liner in [0032], Fig. 11A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Zang’s feature an active cut capping pattern on the material layer in the active cut to the combination of Lin and Jeon to obtain an active cut capping pattern on the flowable material layer in the active cut, wherein the active cut capping pattern includes a material different from that of the flowable material layer to reduce the parasitic capacitance by incorporation of low-k dielectric materials ([0002], Zang).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Ko (US 20210343597 A1) teaches “FORMATION OF HYBRID ISOLATION REGIONS THROUGH RECESS AND RE-DEPOSITION”. This document is related to a semiconductor fin and its method, the semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. The method further includes etching a portion of the semiconductor fin to form a trench, filling the trench with a first dielectric material, wherein the first dielectric material has a first bandgap, and performing a recessing process to recess the first dielectric material. A recess is formed between opposing portions of the isolation regions. The recess is filled with a second dielectric material. The first dielectric material and the second dielectric material in combination form an additional isolation region. The second dielectric material has a second bandgap smaller than the first bandgap.
Yang et al. (US 20200373402 A1) teaches “SEMICONDUCTOR DEVICE”. This document is related to a semiconductor device having a gate-all-around structure includes a first fin pattern and a second fin pattern separated by a first trench and extending in a first direction, a first nanosheet on the first fin pattern, a second nanosheet on the second fin pattern, a first fin liner extending along at least a portion of a sidewall and a bottom surface of the first trench, a first field insulation layer disposed on the first fin liner and filling a portion of the first trench, and a first gate structure overlapping an end portion of the first fin pattern and including a first gate spacer. A height from the bottom surface of the first trench to a lower surface of the first gate spacer is greater than a height from the bottom surface of the first trench to an upper surface of the first field insulation layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898