DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 06/04/2026 has been entered. Applicant's amendment have overcome
the rejections to the Claims 112 (b), previously set forth in the Non-Final Office Action dated on 03/04/2026. Claim 6 is canceled. Claims 1-5 and 7-20 are pending.
Response to Arguments
Applicant’s arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Non-Final Reject" filed on 06/04/2026, related to “wherein the flowable material layer is not in contact with each of the substrate” and the arguments “FIG. 2 of Lin illustrates a "cross-sectional" view of the semiconductor device (reproduced below in part) including the relied-upon "y-direction." FIG. 2 shows that the relied-upon "material layer (130)" is in contact with the relied-upon "102 substrate." (See also FIGs. 1 and 19A-19B of Lin showing the relied-upon "y-direction")” have been fully considered. However, the Applicant’s arguments are not persuasive because Lin (US 20230395654 A1) reference discloses in Fig. 3, a liner 131 between the substrate and the material 130, in relation to the arguments, in the case of liner 131 is only formed in the x-direction (as suggested by Applicant), Fig. 2 corresponding to the cross-sectional view in y-direction, the liner 131 must be observed in the bottom surface of 130 but it is not showed. In addition, in paragraph [0021] is described “structure liner 131 (visible in FIG. 3).”, as a necessary clarification that this element is not showed in all figures, then although in Fig. 2 is not showed the liner 131, it is must be a result of a simplification of the figure 2.
In the relation with the Applicant’s amendments “a gate capping pattern that protrudes from the active cut in the first horizontal direction and is in contact with the active cut, wherein a top surface of the active cut is coplanar with a top surface of the gate capping pattern” are not persuasives and some of them are moot because do not apply to new ground of rejections with a new reference, US 20210217860 A1 to Ha, being used in the current rejection, see details below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 13-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph,
as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 13, it recites the limitation “a gate capping pattern that extends in the second horizontal direction on a top surface of the first gate electrode… …a gate capping pattern that protrudes from sidewalls of the active cut… …wherein a top surface of the active cut and a top surface of the active cut capping pattern are coplanar with a top surface of the gate capping pattern”. It is not clear what element correspond to “the gate capping pattern”. There are two different elements indicated as a gate capping pattern then, it is confusing as to what element corresponds to “the gate capping pattern”. Therefore, it is indefinite. For the examination purpose, the limitation “a gate capping pattern that extends in the second horizontal direction on a top surface of the first gate electrode… …a gate capping pattern that protrudes from sidewalls of the active cut… …wherein a top surface of the active cut and a top surface of the active cut capping pattern are coplanar with a top surface of the gate capping pattern” is interpreted as “a first gate capping pattern that extends in the second horizontal direction on a top surface of the first gate electrode… …a second gate capping pattern that protrudes from sidewalls of the active cut… …wherein a top surface of the active cut and a top surface of the active cut capping pattern are coplanar with a top surface of the second gate capping pattern”.
Regarding claims 14-19, those are rejected under 35 U.S.C. 112 (b), because of their dependency status from claim 13.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 7-9 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ha et al. (US 20210217860 A1, hereinafter Ha), in view of Lin et al. (US 20230395654 A1, hereinafter Lin, of the record) in view of Jeon et al. (US 20170110456 A1, hereinafter Jeon, of the record).
Re: Independent Claim 1, Ha discloses a semiconductor device (Fig. 2) comprising:
a substrate (100 substrate in [0021], Fig. 2);
a first active pattern (100-L fin structure AP1 at left side in [0021,0025], Fig. 2-Annotated) that extends in a first direction (D1 x-direction, Fig.2-Annotated) on the substrate (102);
a second active pattern (100-R fin structure AP1 at right side in [0021,0025], Fig. 2-Annotated) that extends in the first direction (D1 x-direction, Fig. 2-Annotated) on the substrate (100),
a first gate electrode (GE(G4)-L gate structure at left side in [0028], Fig. 2-Annotated) that extends in a second direction (D2 y-direction, in [0028]) different from the first direction (D1 x-direction, Fig.2-Annotated) on the first active pattern (100-L);
a second gate electrode (GE(G4)-R gate structure at right side in [0028], Fig. 2-Annotated) that extends in the second direction (D2 y-direction, in [0028]) on the second active pattern (100-R);
and a gate capping pattern (GP gate capping pattern in [0031], Fig. 2, Ha).
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Ha’s Figure 2-Annotated.
Ha does not expressly disclose wherein the second active pattern is spaced apart from the first active pattern in the first horizontal direction; a first trench that extends in the second horizontal direction between the first gate electrode and the second gate electrode, wherein the first trench separates the first active pattern and the second active pattern, and at least part of the first trench is in the substrate; an active cut that extends along sidewalls and a bottom surface of the first trench, wherein the active cut is in contact with each of the first active pattern and the second active pattern; a second trench on the active cut in the first trench; and a flowable material layer in at least part of the second trench, wherein the flowable material layer includes a flowable insulating material, and wherein the flowable material layer is not in contact with each of the substrate, the first active pattern, and the second active pattern; and a gate capping pattern that protrudes from the active cut in the first horizontal direction and is in contact with the active cut, wherein a top surface of the active cut is coplanar with a top surface of the gate capping pattern.
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Lin’s Figure 3-Annotated.
However, in the same semiconductor device field of endeavor, Lin discloses a first trench (trench1 a trench to include layer 131 in [0021], Fig. 3-Annotated) that extends in the second direction (y-direction, Fig.3-Annotated) between the first gate electrode (112-L) and the second gate electrode (112-R), wherein the first trench (trench1) separates (Fig. 3-Annotated) the first active pattern (106-L) and the second active pattern (106-R), and at least part (Fig. 3-Annotated)of the first trench (trench1) is in the substrate (102); an active cut (131 an insulating structure liner in [0021], Fig. 3-Annotated) that extends along sidewalls and a bottom surface of the first trench (trench1), wherein the active cut (131) is in contact with each of the first active pattern (106-L) and the second active pattern (106-R); a second trench (trench2 a trench to include layer 130 in [0028], Fig. 3-Annotated) on the active cut (131) in the first trench (trench1); and a material layer (130 insulating structure in [0028], Fig. 3-Annotated) in at least part of the second trench (trench2), wherein the material layer (130) includes an insulating material (in [0028], Fig. 3-Annotated), and wherein the material layer (130) is not in contact with (Fig. 3, [0021]) each of the substrate (102), the first active pattern (106-L), and the second active pattern (106-R).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Lin’s feature a first trench that extends in the second horizontal direction between the first gate electrode and the second gate electrode, wherein the first trench separates the first active pattern and the second active pattern, and at least part of the first trench is in the substrate; an active cut that extends along sidewalls and a bottom surface of the first trench, wherein the active cut is in contact with each of the first active pattern and the second active pattern; a second trench on the active cut in the first trench; and a flowable material layer in at least part of the second trench, wherein the flowable material layer includes a flowable insulating material, and wherein the flowable material layer is not in contact with each of the substrate, the first active pattern, and the second active pattern to Ha’s device to obtain wherein the second active pattern is spaced apart from the first active pattern in the first direction to prevent adjacent S/D regions from merging together, which can allow a higher density of transistors to be formed on the substrate ([0017], Lin).
The combination of Ha and Lin results in a gate capping pattern (GP gate capping pattern in [0031], Fig. 2, Ha) that protrudes (Lin’s 130-131 applied to Ha as showed in Fig. 2-Annotated-Ha) from the active cut (Lin’s 131, Fig. 3-Annotated) in the first horizontal direction (Fig. 2-Annotated-Ha) and is in contact with (Lin’s 130-131 applied to Ha as showed in Fig. 2-Annotated-Ha) the active cut (Lin’s 131, Fig. 3-Annotated), wherein a top surface of the active cut (Lin’s 131, Fig. 3-Annotated) is coplanar (Fig. 2-Annotated-Ha) with a top surface of the gate capping pattern (GP, Fig. 2, Ha).
Still, Ha modified by Lin does not expressly disclose a flowable material layer in at least part of the second trench, wherein the flowable material layer includes a flowable insulating material.
However, in the same semiconductor device field of endeavor, Jeon discloses a flowable material layer (143a first isolation layer in [0118], Fig. 24) in at least part of the second trench (trench a trench including 143a material in [0118], Fig. 24), wherein the flowable material layer (143a) includes a flowable insulating material ([0118], Fig. 24).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Jeon’s feature a flowable material layer in at least part of the second trench, wherein the flowable material layer includes a flowable insulating material to the combination of Ha and Lin to provide a semiconductor device that has high integration and improved electrical characteristics ([0003], Jeon).
Re: Claim 7, Ha modified by Lin and Jeon discloses the semiconductor device of claim 1, further comprising: a third gate electrode (GE(G3)-C gate structure in [0028], Fig. 2-Annotated, Ha) on the first (100-L Fig. 2-Annotated, Ha) and second (100-R Fig. 2-Annotated, Ha) active patterns, wherein the third gate electrode (GE(G3)-C Fig. 2-Annotated, Ha) extends in the second direction (D2 y-direction, in [0028], Ha) between the first gate electrode (GE(G4)-L Fig. 2-Annotated, Ha) and the second gate electrode (GE(G4)-R Fig. 2-Annotated, Ha), and wherein the first trench (trench1 Fig. 3-Annotated, Lin) extends into the third gate electrode (GE(G3)-C Fig. 2-Annotated, Ha) in a vertical direction (D3 z-direction, Fig.2-Annotated, Ha), the vertical direction being perpendicular to the first (D1 x-direction, Ha) and second (D2 y-direction, Ha) directions and wherein the gate capping pattern (GP Fig. 2-Annotated, Ha) is disposed on the third gate electrode (GE(G3)-C Fig. 2-Annotated, Ha).
Re: Claim 8, Ha modified by Lin and Jeon discloses the semiconductor device of claim 7, wherein sidewalls of the active cut (131, Lin) are in contact with the third gate electrode (GE(G3)-C Fig. 2-Annotated, Ha).
Re: Claim 9, Ha modified by Lin and Jeon discloses the semiconductor device of claim 1, further comprising: a first plurality of nanosheets (CP1,2,3-L semiconductor patterns as channel layers at left side in [0025], Fig. 2, Ha) spaced apart from one another in a vertical direction (D3 z-direction, Fig.2-Annotated, Ha) on the first active pattern (100-L, Ha), wherein the first plurality of nanosheets (CP1,2,3-L, Ha) is at least partially surrounded by the first gate electrode (GE(G4)-L Fig.2-Annotated, Ha), and wherein the vertical direction (D3 z-direction, Fig.2-Annotated, Ha) is perpendicular to the first (D1 x-direction, Ha) and second (D2 y-direction, Ha) directions; and a second plurality of nanosheets (CP1,2,3-R semiconductor patterns as channel layers at left right in [0025], Fig. 2, Ha) spaced apart from one another in the vertical direction (D3 z-direction, Fig.2-Annotated, Ha) on the second active pattern (100-R, Ha), wherein the second plurality of nanosheets (CP1,2,3-R, Ha) is at least partially surrounded by the second gate electrode (GE(G4)-R Fig.2-Annotated, Ha).
Claim(s) 2-4 and 11 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ha, in view of Lin, in view of Jeon and further in view of Zang et al. (US 20200227323 A1, hereinafter Zang, of the record).
Re: Claim 2, Ha modified by Lin and Jeon discloses the semiconductor device of claim 1.
Ha modified by Lin and Jeon does not expressly disclose wherein a top surface of the flowable material layer is lower than the top surface of the active cut relative to the substrate.
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Zang’s Figure 11A-Annotated.
However, in the same semiconductor device field of endeavor, Zang discloses a top surface of the material layer (228 fourth dielectric layer in [0032], Fig. 11A) is lower (Fig. 11A-Annotated) than the top surface of the active cut (226 second liner in [0032], Fig. 11A) relative to the substrate (202 substrate in [0018], Fig. 11A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Zang’s feature a top surface of the material layer is lower than the top surface of the active cut relative to the substrate to the combination of Ha, Lin and Jeon to obtain a top surface of the flowable material layer is lower than the top surface of the active cut relative to the substrate to reduce the parasitic capacitance by incorporation of low-k dielectric materials ([0002], Zang).
Re: Claim 3, Ha modified by Lin and Jeon discloses the semiconductor device of claim 1.
Ha modified by Lin and Jeon does not expressly disclose further comprising: an active cut capping pattern on the flowable material layer in the second trench, wherein the active cut capping pattern includes a material different from that of the flowable material layer.
However, in the same semiconductor device field of endeavor, Zang discloses an active cut capping pattern (230 capping layer made of SiN in [0032-0033], Fig. 11A) on the material layer (228 fourth dielectric layer in [0032], Fig. 11A) in the second trench (trench a trench including layer 228 in [0032], Fig. 11A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Zang’s feature an active cut capping pattern on the flowable material layer in the second trench to the combination of Ha, Lin and Jeon to obtain the active cut capping pattern includes a material different from that of the flowable material layer to reduce the parasitic capacitance by incorporation of low-k dielectric materials ([0002], Zang).
Re: Claim 4, Ha modified by Lin, Jeon and Zang discloses the semiconductor device of claim 3,
Ha modified by Lin, Jeon and Zang does not expressly disclose wherein a top surface of the active cut capping pattern is coplanar with the top surface of the active cut.
However, in the same semiconductor device field of endeavor, Zang discloses wherein a top surface of the active cut capping pattern (230 capping layer made of SiN in [0032-0033], Fig. 11A) is coplanar with a top surface of the active cut (226 second liner in [0032], Fig. 11A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Zang’s feature wherein a top surface of the active cut capping pattern is coplanar with the top surface of the active cut to the combination of Ha, Lin, Jeon and Zang to reduce the parasitic capacitance by incorporation of low-k dielectric materials ([0002], Zang).
Regarding claim 11, Ha modified by Lin and Jeon discloses the semiconductor device of claim 9,
Ha modified by Lin and Jeon does not disclose wherein a top surface of the flowable material layer is between a bottom surface of a lowermost nanosheet of the first plurality of nanosheets and a top surface of an uppermost nanosheet of the first plurality of nanosheets.
However, the Applicant has not presented persuasive evidence that the claimed
“top surface of the flowable material layer is between a bottom surface of a lowermost nanosheet of the first plurality of nanosheets and a top surface of an uppermost nanosheet of the first plurality of nanosheets” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed top surface of the flowable material layer is between a bottom surface of a lowermost nanosheet of the first plurality of nanosheets and a top surface of an uppermost nanosheet of the first plurality of nanosheets). Also, the applicant has not shown that the claimed “difference of top surface of the flowable material layer is between a bottom surface of a lowermost nanosheet of the first plurality of nanosheets and a top surface of an uppermost nanosheet of the first plurality of nanosheets” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Lin discloses “a top surface of a dielectric material 130 above the plurality of nanosheets, Fig. 3” and Zang discloses “a top surface of a dielectric layer 228 below a top gate layer 232, Fig. 11A”, therefore, the position of the top surface of the flowable material is a result effective variable. It has been held that is not inventive to discover the optimum position of the top surface of the flowable material by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a top surface of the flowable material layer is between a bottom surface of a lowermost nanosheet of the first plurality of nanosheets and a top surface of an uppermost nanosheet of the first plurality of nanosheets to reduce the parasitic capacitance by incorporation of low-k dielectric materials ([0002], Zang).
Claim(s) 5 and 16 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ha, in view of Lin, in view of Jeon in view of Zang and further in view of Yu et al. (US 20200152736 A1, hereinafter Yu, of the record).
Re: Claim 5, Ha modified by Lin, Jeon and Zang discloses the semiconductor device of claim 3,
Ha modified by Lin, Jeon and Zang does not expressly disclose further comprising: an airgap between a top surface of the flowable material layer and a bottom surface of the active cut capping pattern in the second trench.
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Yu’s Figure 10A-Annotated.
However, in the same semiconductor device field of endeavor, Yu discloses further comprising: an airgap (182 air gap in [0038], Fig. 10A) between a top surface of the material layer (160 liner in [0037], Fig. 10A) and a bottom surface of the active cut capping pattern (170 sealing layer in [0038], Fig. 10A) in the second trench (162 gate cut isolation opening in [0037], Fig. 10A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Yu’s feature further comprising: an airgap between a top surface of the flowable material layer and a bottom surface of the active cut capping pattern in the second trench to the combination of Ha, Lin, Jeon and Zang to obtain an airgap between the top surface of the flowable material layer and a bottom surface of the active cut capping pattern in the active cut to create a gate cut isolation that provides an electrical isolation ([0003], Yu).
Re: Claim 16, Ha modified by Lin, Jeon and Zang discloses the semiconductor device of claim 13,
Ha modified by Lin, Jeon and Zang does not expressly disclose further comprising: an airgap between a top surface of the flowable material layer and a bottom surface of the active cut capping pattern in the second trench.
However, in the same semiconductor device field of endeavor, Yu discloses further comprising: an airgap (182 air gap in [0038], Fig. 10A) between a top surface of the material layer (160 liner in [0037], Fig. 10A) and a bottom surface of the active cut capping pattern (170 sealing layer in [0038], Fig. 10A) in the second trench (162 gate cut isolation opening in [0037], Fig. 10A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Yu’s feature further comprising: an airgap between a top surface of the flowable material layer and a bottom surface of the active cut capping pattern in the second trench to the combination of Ha, Lin, Jeon and Zang to obtain an airgap between the top surface of the flowable material layer and a bottom surface of the active cut capping pattern in the active cut to create a gate cut isolation that provides an electrical isolation ([0003], Yu).
Claim(s) 13-15, 17 and 18 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ha, in view of Lin, in view of Jeon and further in view of Zang (US 20200227323 A1, hereinafter Zang).
Re: Independent Claim 13, Ha discloses a semiconductor device (Fig. 2) comprising:
a substrate (100 substrate in [0021], Fig. 2);
a first active pattern (100-L fin structure AP1 at left side in [0021,0025], Fig. 2-Annotated) that extends in a first direction (D1 x-direction, Fig.2-Annotated) on the substrate (102);
a second active pattern (100-R fin structure AP1 at right side in [0021,0025], Fig. 2-Annotated) that extends in the first direction (D1 x-direction, Fig. 2-Annotated) on the substrate (100),
a first gate electrode (GE(G4)-L gate structure at left side in [0028], Fig. 2-Annotated) that extends in a second direction (D2 y-direction, in [0028]) different from the first direction (D1 x-direction, Fig.2-Annotated) on the first active pattern (100-L);
a first gate capping pattern (GP gate capping pattern in [0031], Fig. 2, Ha) that extends in the second horizontal direction (D2 y-direction, in [0028]) on a top surface of the first gate electrode (GE(G4)-L); a second gate capping pattern (GP, above a third gate (GE(G3)-C Fig. 2-Annotated).
Ha does not expressly disclose an active cut spaced apart from the first gate electrode in the first horizontal direction, wherein the active cut separates the first active pattern and the second active pattern, wherein the active cut is in contact with each of the first active pattern and the second active pattern, at least part of the active cut is in the substrate, and a top surface of the active cut is coplanar with a top surface of the gate capping pattern; a flowable material layer in the active cut, wherein the flowable material layer includes a flowable insulating material, wherein the flowable material layer is not in contact with each of the substrate, the first active pattern, and the second active pattern, and a top surface of the flowable material layer is lower than the top surface of the active cut relative to the substrate; and an active cut capping pattern on the flowable material layer in the active cut, wherein the active cut capping pattern includes a material different from that of the flowable material layer; and a second gate capping pattern that protrudes from sidewalls of the active cut in the first horizontal direction and is in contact with the active cut, wherein a top surface of the active cut and a top surface of the active cut capping pattern are coplanar with a top surface of the second gate capping pattern.
However, in the same semiconductor device field of endeavor, Lin discloses an active cut (131 an insulating structure liner in [0021], Fig. 3-Annotated) spaced apart from the first gate electrode (112-L) in the first horizontal direction (x-direction, Fig. 3-Annotated), wherein the active cut (131) separates the first active pattern (106-L) and the second active pattern (106-R), wherein the active cut (131) is in contact with each of the first active pattern (106-L) and the second active pattern (106-R), at least part of the active cut (131) is in the substrate (102); a material layer (130 insulating structure in [0028], Fig. 3-Annotated) in the active cut (131), wherein the material layer (130) includes an insulating material (in [0028], Fig. 3-Annotated), and wherein the material layer (130) is not in contact with each of the substrate (102), the first active pattern (106-L), and the second active pattern (106-R).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Lin’s feature of an active cut spaced apart from the first gate electrode in the first horizontal direction, wherein the active cut separates the first active pattern and the second active pattern, wherein the active cut is in contact with each of the first active pattern and the second active pattern, at least part of the active cut is in the substrate, a material layer in the active cut, wherein the material layer includes an insulating material, wherein the material layer is not in contact with each of the substrate, the first active pattern, and the second active pattern to Ha’s device to obtain wherein the second active pattern is spaced apart from the first active pattern in the first horizontal direction and a top surface of the active cut is coplanar with a top surface of the gate capping pattern to prevent adjacent S/D regions from merging together, which can allow a higher density of transistors to be formed on the substrate ([0017], Lin).
The combination of Ha and Lin results in a second gate capping pattern (GP gate capping pattern in [0031], Fig. 2, Ha) that protrudes (Lin’s 130-131 applied to Ha as showed in Fig. 2-Annotated-Ha) from the sidewalls of the active cut (Lin’s 131, Fig. 3-Annotated) in the first horizontal direction (Fig. 2-Annotated-Ha) and is in contact with (Lin’s 130-131 applied to Ha as showed in Fig. 2-Annotated-Ha) the active cut (Lin’s 131, Fig. 3-Annotated), wherein a top surface of the active cut (Lin’s 131, Fig. 3-Annotated) is coplanar (Fig. 2-Annotated-Ha) with a top surface of the second gate capping pattern (GP, Fig. 2, Ha).
Still, Ha modified by Lin does not expressly disclose a flowable material layer in the active cut, wherein the flowable material layer includes a flowable insulating material; and a top surface of the flowable material layer is lower than the top surface of the active cut relative to the substrate; and an active cut capping pattern on the flowable material layer in the active cut, wherein the active cut capping pattern includes a material different from that of the flowable material layer.
However, in the same semiconductor device field of endeavor, Jeon discloses a flowable material layer (143a first isolation layer in [0118], Fig. 24) in the active cut (142 a capping layer in [0135], Fig. 24), wherein the flowable material layer (143a) includes a flowable insulating material (in [0118], Fig. 24).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Jeon’s feature a flowable material layer in the active cut, wherein the flowable material layer includes a flowable insulating material to the combination of Ha and Lin to provide a semiconductor device that has high integration and improved electrical characteristics ([0003], Jeon).
Still, Ha modified by Lin and Jeon does not expressly disclose a top surface of the flowable material layer is lower than the top surface of the active cut relative to the substrate; and an active cut capping pattern on the flowable material layer in the active cut, wherein the active cut capping pattern includes a material different from that of the flowable material layer.
However, in the same semiconductor device field of endeavor, Zang discloses a top surface of the material layer (228 fourth dielectric layer in [0032], Fig. 11A) is lower than the top surface of the active cut (226 second liner in [0032], Fig. 11A) relative to the substrate (202 substrate in [0018], Fig. 11A); and an active cut capping pattern (230 capping layer in [0032], Fig. 11A) on the material layer (228, Fig. 11A) in the active cut (226, Fig. 11A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Zang’s feature a top surface of the material layer is lower than the top surface of the active cut relative to the substrate; and an active cut capping pattern on the material layer in the active cut to the combination of Ha, Lin and Jeon to obtain a top surface of the flowable material layer is lower than the top surface of the active cut relative to the substrate; and an active cut capping pattern on the flowable material layer in the active cut, wherein the active cut capping pattern includes a material different from that of the flowable material layer to reduce the parasitic capacitance by incorporation of low-k dielectric materials ([0002], Zang).
Re: Claim 14, Ha modified by Lin, Jeon and Zang discloses the semiconductor device of claim 13,
Ha modified by Lin, Jeon and Zang does not expressly disclose wherein a bottom surface of the active cut capping pattern is lower than a bottom surface of the gate capping pattern relative to the substrate.
However, in the same semiconductor device field of endeavor, Zang discloses a bottom surface of the active cut capping pattern (230 capping layer in [0032], Fig. 11A) is lower than a bottom surface of the gate capping pattern (232-top a top layer in the top gate structure 232 in [0034], Fig. 11A) relative to the substrate (202 substrate in [0018], Fig. 11A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Zang’s feature wherein a bottom surface of the active cut capping pattern is lower than a bottom surface of the gate capping pattern relative to the substrate to the combination of Ha, Lin, Jeon and Zang to reduce the parasitic capacitance by incorporation of low-k dielectric materials ([0002], Zang).
Re: Claim 15, Ha modified by Lin, Jeon and Zang discloses the semiconductor device of claim 13, wherein at least part of the flowable material layer (143a’s Jeon applied to 130’s Lin Fig. 3-Annotated, Lin) is in the substrate (100 Fig. 2-Annotated, Ha).
Re: Claim 17, Ha modified by Lin, Jeon and Zang discloses the semiconductor device of claim 13, further comprising: a second gate electrode (GE(G3)-C gate structure in [0028], Fig. 2-Annotated, Ha) spaced apart from the first gate electrode (GE(G4)-L Fig. 2-Annotated, Ha) in the first direction (D1 x-direction, Fig.2-Annotated, Ha), wherein the second gate electrode (GE(G3)-C, Ha) extends in the second direction (D2 y-direction, in [0028], Ha) on the first (100-L Fig. 2-Annotated, Ha) and second (100-R Fig. 2-Annotated, Ha) active patterns, and wherein the second gate electrode (GE(G3)-C, Ha) is in contact with the sidewalls of the active cut (131 Fig. 3-Annotated, Lin) in the first direction (D1 x-direction, Fig.2-Annotated, Ha).
Re: Claim 18, Ha modified by Lin, Jeon and Zang discloses the semiconductor device of claim 13, further comprising: a first plurality of nanosheets (CP1,2,3-L semiconductor patterns as channel layers at left side in [0025], Fig. 2, Ha) spaced apart from one another in a vertical direction (D3 z-direction, Fig.2-Annotated, Ha) on the first active pattern (100-L, Ha), wherein the first plurality of nanosheets (CP1,2,3-L, Ha) is at least partially surrounded by the first gate electrode (GE(G4)-L Fig.2-Annotated, Ha), and wherein the vertical direction (D3 z-direction, Fig.2-Annotated, Ha) is perpendicular to the first (D1 x-direction, Ha) and second (D2 y-direction, Ha) directions; and a second plurality of nanosheets (CP1,2,3-R semiconductor patterns as channel layers at left right in [0025], Fig. 2, Ha) spaced apart from one another in the vertical direction (D3 z-direction, Fig.2-Annotated, Ha) on the first (100-L, Ha) and second (100-R, Ha) active patterns, wherein the second plurality of nanosheets (CP1,2,3-R, Ha) is in contact with sidewalls of the active cut (131 Fig. 3-Annotated, Lin) in the first horizontal direction (D1 x-direction, Ha).
Re: Independent Claim 20, Ha discloses a semiconductor device (Fig. 2) comprising:
a substrate (100 substrate in [0021], Fig. 2);
a first active pattern (100-L fin structure AP1 at left side in [0021,0025], Fig. 2-Annotated) that extends in a first direction (D1 x-direction, Fig.2-Annotated) on the substrate (102);
a second active pattern (100-R fin structure AP1 at right side in [0021,0025], Fig. 2-Annotated) that extends in the first direction (D1 x-direction, Fig. 2-Annotated) on the substrate (100),
a first plurality of nanosheets (CP1,2,3-L semiconductor patterns as channel layers at left side in [0025], Fig. 2) spaced apart from one another in a vertical direction (D3 z-direction, Fig.2-Annotated) perpendicular to the first direction (D1 x-direction, Fig.2-Annotated) on the first active pattern (100-L);
a second plurality of nanosheets (CP1,2,3-R semiconductor patterns as channel layers at right side in [0025], Fig. 2) spaced apart from one another in the vertical direction (D3 z-direction, Fig.2-Annotated) on the second active pattern (100-R);
a third plurality of nanosheets (CP1,2,3-C semiconductor patterns as channel layers between CP1,2,3-L and CP1,2,3-R in [0025], Fig. 2) spaced apart from one another in the vertical direction (D3 z-direction, Fig.2-Annotated) on the first (100-L) and second (100-R) active patterns;
a first gate electrode (GE(G4)-L gate structure at left side in [0028], Fig. 2-Annotated) that extends in a second direction (D2 y-direction, in [0028]) different from the first direction (D1 x-direction, Fig. 2-Annotated) on the first active pattern (100-L), wherein the first gate electrode (GE(G4)-L) at least partially surrounds the first plurality of nanosheets (CP1,2,3-L);
a second gate electrode (GE(G4)-R gate structure at right side in [0028], Fig. 2-Annotated) that extends in the second direction (D2 y-direction, in [0028]) on the second active pattern (100-R), wherein the second gate electrode (GE(G4)-R) at least partially surrounds the second plurality of nanosheets (CP1,2,3-R);
a third gate electrode (GE(G3)-C gate structure at the center in [0028], Fig. 2-Annotated) that extends in the second direction (D2 y-direction, in [0028]) on the first (100-L) and second (100-R) active patterns, wherein the third gate electrode (GE(G3)-C) at least partially surrounds the third plurality of nanosheets (CP1,2,3-C); a gate capping pattern (GP, above a third gate (GE(G3)-C Fig. 2-Annotated) on the third gate electrode (GE(G3)-C).
Ha does not expressly disclose a first trench that extends into the gate capping pattern, the third gate electrode, the third plurality of nanosheets, and the substrate in the vertical direction, wherein the first trench extends in the second horizontal direction between the first gate electrode and the second gate electrode, and wherein the first trench separates the first active pattern and the second active pattern; an active cut that extends along sidewalls and a bottom surface of the first trench, wherein the active cut is in contact with each of the first active pattern, the second active pattern, the gate capping pattern, the third gate electrode, and the third plurality of nanosheets; a second trench on the active cut in the first trench; a flowable material layer in at least part of the second trench, wherein the flowable material layer includes a flowable insulating material, and wherein the flowable material layer is not in contact with each of the substrate, the first active pattern, and the second active pattern; and an active cut capping pattern on the flowable material layer in the active cut, wherein the active cut capping pattern includes a material different from that of the flowable material layer.
However, in the same semiconductor device field of endeavor, Lin discloses a first trench (trench1 a trench to include layer 131 in [0021], Fig. 3-Annotated) that extends into (Fig. 3-Annotated) the third gate electrode (108-C), the third plurality of nanosheets (109-C), and the substrate (108-C) in the vertical direction (z-direction, Fig.3-Annotated), wherein the first trench (trench1) extends in the second direction (y-direction, Fig.3-Annotated) between the first gate electrode (112-L) and the second gate electrode (112-R), and wherein the first trench (trench1) separates (Fig. 3-Annotated) the first active pattern (106-L) and the second active pattern (106-R); an active cut (131 an insulating structure liner in [0021], Fig. 3-Annotated) that extends along sidewalls and a bottom surface of the first trench (trench1), wherein the active cut (131) is in contact with each of the first active pattern (106-L), the second active pattern (106-R), the third gate electrode (108-C), and the third plurality of nanosheets (109-C); a second trench (trench2 a trench to include layer 130 in [0028], Fig. 3-Annotated) on the active cut (131) in the first trench (trench1); a material layer (130 insulating structure in [0028], Fig. 3-Annotated) in at least part of the second trench (trench2), wherein the material layer (130) includes an insulating material (in [0028], Fig. 3-Annotated), and wherein the material layer (130) is not in contact with each of the substrate (102), the first active pattern (106-L), and the second active pattern (106-R).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Lin’s feature of a first trench that extends into the third gate electrode, the third plurality of nanosheets, and the substrate in the vertical direction, wherein the first trench extends in the second horizontal direction between the first gate electrode and the second gate electrode, and wherein the first trench separates the first active pattern and the second active pattern; an active cut that extends along sidewalls and a bottom surface of the first trench, wherein the active cut is in contact with each of the first active pattern, the second active pattern, the third gate electrode, and the third plurality of nanosheets; a second trench on the active cut in the first trench; a material layer in at least part of the second trench, wherein the material layer includes a insulating material, and wherein the material layer is not in contact with each of the substrate, the first active pattern, and the second active pattern to Ha’s device to obtain wherein the second active pattern is spaced apart from the first active pattern in the first direction; a first trench that extends into the gate capping pattern, the third gate electrode, the third plurality of nanosheets, wherein the active cut is in contact with each of the first active pattern, the second active pattern, the gate capping pattern, the third gate electrode, and the third plurality of nanosheets to prevent adjacent S/D regions from merging together, which can allow a higher density of transistors to be formed on the substrate ([0017], Lin).
Still, Ha modified by Lin does not expressly disclose a flowable material layer in at least part of the second trench, wherein the flowable material layer includes a flowable insulating material; and an active cut capping pattern on the flowable material layer in the active cut, wherein the active cut capping pattern includes a material different from that of the flowable material layer.
However, in the same semiconductor device field of endeavor, Jeon discloses a flowable material layer (143a first isolation layer in [0118], Fig. 24) in at least part of the second trench (trench a trench including 143a material in [0118], Fig. 24), wherein the flowable material layer (143a) includes a flowable insulating material (in [0118], Fig. 24).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Jeon’s feature a flowable material layer in at least part of the second trench, wherein the flowable material layer includes a flowable insulating material to Lin’s device to provide a semiconductor device that has high integration and improved electrical characteristics ([0003], Jeon).
Still, Ha modified by Lin and Jeon does not expressly disclose an active cut capping pattern on the flowable material layer in the active cut, wherein the active cut capping pattern includes a material different from that of the flowable material layer.
However, in the same semiconductor device field of endeavor, Zang discloses an active cut capping pattern (230 capping layer in [0032], Fig. 11A) on the material layer (228 fourth dielectric layer in [0032], Fig. 11A) in the active cut (226 second liner in [0032], Fig. 11A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Zang’s feature an active cut capping pattern on the material layer in the active cut to the combination of Ha, Lin and Jeon to obtain an active cut capping pattern on the flowable material layer in the active cut, wherein the active cut capping pattern includes a material different from that of the flowable material layer to reduce the parasitic capacitance by incorporation of low-k dielectric materials ([0002], Zang).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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