DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on July 31, 2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 8, 2023 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Devices With Improved Retention Property And Electronic Systems Including the Same
Election/Restrictions
Applicant’s election without traverse of Species I (Fig. 2B, claims 1-7, 10-14, and 18-20 in the reply filed on October 6, 2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsutsumi (US 2019/0252405). Claim 1, Tsutsumi discloses (Figs. 17G and annotated Fig. 18A below) a semiconductor device, comprising: a gate stack (32/46, insulating layers/electrically conductive layers, Para [0119]) that includes a first insulating pattern (IP1 which is 32), a second insulating pattern (IP2 which is 32) adjacent to the first insulating pattern (IP2 is vertically adjacent to IP1), a third insulating pattern (IP3 which is 32) adjacent to the second insulating pattern (IP3 is vertically adjacent to IP2), a first conductive pattern (CP1 which is 46) between the first and second insulating patterns (CP1 is between IP1 and IP2), and a second conductive pattern (CP2 which 46) between the second and third insulating patterns (CP2 is between IP2 and IP3); a channel layer (601, first semiconductor channel layer, Para [0088]) that extends in the gate stack (601 extends in 32/46); a tunnel insulating layer (56, tunneling dielectric layer, Para [0087]) on the channel layer (56 is on 601); and a first data storage pattern (Fig. 18A, 54 between IP1 and IP2, discrete charge trap silicon nitride, Para [0146], hereinafter “data1”) and a second data storage pattern (Fig. 18A, 54 between IP2 and IP3, discrete charge trap silicon nitride, Para [0146], hereinafter “data2”) on the tunnel insulating layer (data1 and data2 are on 56), wherein the first data storage pattern (data1) comprises (Fig. 17G) a first outer portion (542 of data1, second silicon nitride segment, Para [0111], hereinafter “out1”) between the first and second insulating patterns (out1 is between neighboring 32s which would be IP1 and IP2), and a first inner portion (541 of data1, first silicon nitride segment, Para [0111], hereinafter “in1”) on the first outer portion (in1 is on out1), wherein the second data storage pattern (data2) comprises (Fig. 17G) a second outer portion (542 of data2, second silicon nitride segment, Para [0111], hereinafter “out2”) between the second and third insulating patterns (out2 is between neighboring 32s which would be IP2 and IP3), and a second inner portion (541 of data2, first silicon nitride segment, Para [0111], hereinafter “in2”) on the second outer portion (in2 is on out2), and wherein a distance between (Fig. 1G, horizontal distance between 541 and 601, hereinafter “dist1”) each of the first and second inner portions (in1/in2) and the channel layer (601) is smaller than a distance (Fig. 1G, horizontal distance between 32 and 601, hereinafter “dist2”) between each of the first to third insulating patterns (32) and the channel layer (dist1 is smaller than dist2).
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Claim 2, Tsutsumi discloses (Figs. 17G and annotated Fig. 18A above) the semiconductor device of claim 1, wherein the first (in1) and second inner portions (in2) and the first (out1) and second outer portions (out2) comprise a nitride material (in1/in2 are 542 and out1/out2 are 541 which are silicon nitride segments, Para [0111]). Claim 3, Tsutsumi discloses (Figs. 17G and annotated Fig. 18A above) the semiconductor device of claim 1, wherein the first data storage pattern and the second data storage pattern are spaced apart from each other (as can be seen in annotated Fig. 18A above data1 and data2 are vertically spaced apart from each other). Claim(s) 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Higuchi (US Pat. No. 9,166,032). Claim 10, Higuchi discloses (Fig. 7C) a semiconductor device, comprising: a gate stack (10/15/35a, control gate/interlayer insulating film/first portion of insulating film , Col. 4, lines: 15-23, Col. 7, lines: 3-10, hereinafter “stack” ) that includes an insulating pattern (15/35a) and a conductive pattern (10) alternately stacked on top of each other (10 and 15/35a are alternately stacked on top of each other); a channel layer (20, channel body, Col. 2, lines: 35-40) that extends in the gate stack (20 extends in stack) ; a tunnel insulating layer (33, second insulating film functions as tunnel insulating film, Col. 3, line: 67, Col. 4, lines:1-2) on the channel layer (33 is on 20); a data storage pattern (30, conductive layer serves as charge storage layer, Col. 4, lines: 1-3) on the tunnel insulating layer (30 is on 33); and a blocking pattern (43, first layer of 40, which may function as block insulating film, fourth insulating film, Col. 4, lines: 1-4) on the data storage pattern (43 is on 30), wherein the data storage pattern comprises a first surface (left surface of 30) in contact with the blocking pattern (left surface of 30 is in contact with 43) and a second surface (top surface of 30) in contact with the insulating pattern (top surface of 30 is in contact with 15/35a), wherein the first surface of the data storage pattern has a curved shape (left surface of 30 has curved shape), and wherein the second surface of the data storage pattern has a flat shape (top surface of 30 has a flat shape).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Higuchi (US Pat. No. 9,166,032) as applied to claim 10 above, and further in view of Ishihara (US 2013/0069139). Claim 12, Higuchi discloses (Fig. 7C) the semiconductor device of claim 10, further comprising a layer (45, fifth insulating film may be silicon oxide, Col. 8, lines: 1-3) between the insulating pattern and the tunnel insulating layer (45 is between 15/35a and 33).
Higuchi does not explicitly disclose a deposition stop layer. However, Ishihara discloses that silicon oxide material may be used a an etch stop layer (Para [0100]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing
date of the claimed invention to apply the teachings of Ishihara, including the specific material of the
fifth insulating film to the teachings of Higuchi.
The motivation to do so is that the combination yields the predictable results of allowing for the
selection of a known material based on its suitability for the intended use as an etch stop layer as it can stop etching relative to other materials such as nitrides (Ishihara, Para [0100]).
Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also MPEP 2144.07.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Higuchi (US Pat. No. 9,166,032) as applied to claim 10 above, and further in view of Keller (US 2010/0163959).
Claim 14, Higuchi discloses (Fig. 7C) the semiconductor device of claim 10, further comprising a layer (47, second layer of 40 may be aluminum oxide, Col. 8, lines: 37-44) between the insulating pattern and the conductive pattern (47 is between 15/35a and 10). Higuchi does not explicitly disclose a deposition stop layer. However, Keller discloses that aluminum oxide may be used an etch stop film for floating gate devices (Para [0021]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing
date of the claimed invention to apply the teachings of Keller, including the specific material of the
etch stop film to the teachings of Higuchi.
The motivation to do so is that the combination yields the predictable results of allowing for the
selection of a known material based on its suitability for the intended use as an etch stop layer as it can stop etching relative to other materials such as other oxides (Keller, Para [0021]).
Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also MPEP 2144.07.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsutsumi (US 2019/0252405) in view of NAM (US 2013/0016561). Claim 19, Tsutsumi discloses (Figs. 17G and Fig. 18A) an electronic system, comprising: a main substrate (10, substrate, Para [0060]); a semiconductor device (55/32/46, memory stack structure/insulating layers/electrically conductive layers, Para [0106], [0119], hereinafter “device”) on the main substrate (device is on 10); wherein the semiconductor device (device) comprises: a gate stack (32/46, insulating layers/electrically conductive layers, Para [0119]) that includes an insulating pattern (32) and a conductive pattern (46) alternately stacked on top of each other (32 and 46 are alternately stacked on top of each other); a channel layer (601, first semiconductor channel layer, Para [0088]) that extends in the gate stack (601 extends in 32/46); a tunnel insulating layer (56, tunneling dielectric layer, Para [0087]) on the channel layer (56 is on 601); data storage patterns (54, charge storage elements, Para [0131]) on the tunnel insulating layer (54 is on 56); and blocking patterns (521, blocking dielectric layer, Para [0132]) on the data storage patterns, respectively (521 is on 54s), wherein the data storage patterns are spaced apart from each other (54s are vertically spaced apart from one another), wherein each of the data storage patterns (Fig. 17G, 54) comprises an outer portion (542, second silicon nitride segment, Para [0111]) in contact with a top surface of the insulating pattern (541 is in contact with top surface of 32), and an inner portion (541, first silicon nitride segment, Para [0111]) on the outer portion (541 is on 542), wherein a distance (horizontal distance between 541 and 601, hereinafter “dist1”) between the inner portion and the channel layer is smaller (dist1 is smaller than dist2) than a distance (horizontal distance between 32 and 601, hereinafter “dist2”) between the insulating pattern and the channel layer, and wherein the inner portion and the outer portion comprise a nitride material (541 and 542 are silicon nitride segments, Para [0111]).
Tsutsumi does not explicitly disclose a controller on the main substrate and electrically connected to the semiconductor device. However, NAM discloses (Fig. 1) a controller (170, control logic, Para [0139]) on a main substrate (170 would be formed on main substrate on which nonvolatile memory device 100 is formed, Para [0139] – [0140]) and electrically connected to a semiconductor device (170 is connected to cell arrays 110 for control logic, Para [0139]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the controller of NAM to the system of Tsutsumi as the controller generates commands for the erase operation for the nonvolatile memory device (NAM, Para [0027]). Claim 20, Tsutsumi in view of NAM discloses the electronic system of claim 19. Tsutsumi discloses (Fig. 17G) wherein the outer portion (542) overlaps with the insulating pattern (542 vertically overlaps with 32), and wherein the inner portion (541) overlaps with the tunnel insulating layer (541 laterally overlaps with 56).
Allowable Subject Matter
Claims 4-7, 11, 13, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The following is an examiner’s statement of reasons for allowance: the closest prior art of record, Tsutsumi (US 2019/0252405), NAM (US 2013/0016561), Higuchi (US Pat. No. 9,166,032), Ishihara (US 2013/0069139), Keller (US 2010/0163959), Lee (US 2015/0041882), Simsek-Ege (US 2016/0293623), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 4, wherein a largest width of the first outer portion in the first direction is smaller than a largest width of the first inner portion in the first direction.
Regarding Claim 5, wherein the channel layer comprises a protruding portion that extends toward a region between the first data storage pattern and the second data storage pattern.
Regarding Claim 6, wherein the channel layer has a second width in the first direction at a level in the second direction between the first and second data storage patterns, and wherein the second width is larger than the first width.
Regarding Claim 7, wherein the tunnel insulating layer is on top and bottom surfaces of the first inner portion and top and bottom surfaces of the second inner portion.
Regarding Claim 11, wherein the data storage pattern comprises a third surface that is in contact with the tunnel insulating layer and has a curved shape.
Regarding Claim 13, wherein the deposition stop layer comprises fluorine.
Regarding Claim 18, wherein the data storage pattern comprises an outer portion in contact with a top surface of the insulating pattern, and an inner portion in contact with a side surface of the insulating pattern.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee (US 2015/0041882) discloses (Fig. 3B) a channel layer 131 with protruding portions toward charge trap layer CTL. It does not disclose 131 is between different portions of CTL.
Simsek-Ege (US 2016/0293623) discloses (Fig. 8) a data storage pattern 44 with curved surfaces and an insulating layer 42c covering the top and bottom surfaces of 44. It does not disclose an inner and outer portion of 44 or a flat surface of 44.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
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/G.G.R/Examiner, Art Unit 2812