Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's amendments and arguments filed 12/3/2025 have been fully considered but they are not persuasive. Please see amendments addressed below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6, 8, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (20190088493).
PNG
media_image1.png
367
731
media_image1.png
Greyscale
Regarding claim 1, Watanabe teaches an semiconductor device comprising:
a semiconductor substrate (10; par. 32) including a first area (Rcell) and a second area (Rmark + Rteg) in a plane perpendicular to stacking direction (please see fig. 10 which shows, in the plane going from left to right in the page, that in said left to right plane, Rcell is a first area and Rmark + Rteg are a second area);
a plurality of memory cells (please see fig. 11) provided in the first area;
a mark (17 + 16 + STI) provided in the second area and having a first side surface and a second side surface that intersects with the first side surface (please note both 17 and 16 are rectangles and thus have 4 sides in the page plane); and
a plurality of patterns (90 + ST; please note that ST can also be under 17, as taught in par. 46) provided in the second area and provided on the plane along the first side surface and aling the second side surface (please see above).
Please note that multiple embodiments of prior art are used above. It would have been obvious to a PHOSITA, at the time said invention was made to utilize these embodiments in combination since are related to similar fields of endeavor.
Regarding claim 2, Watanabe teaches an semiconductor device according to claim 1, wherein the plurality of patterns are formed as a linear shape (please see figure above).
Regarding claim 3, Watanabe teaches an semiconductor device according to claim 1, wherein the plurality of patterns are formed as a matrix shape (please see figure above).
Regarding claim 4, Watanabe teaches an semiconductor device according to claim 1, wherein a width of each of the plurality of patterns is less than a width of the mark (please see figure above).
Furthermore, the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device
Regarding claim 6, Watanabe teaches an semiconductor device according to claim 1, wherein the plurality of patterns and the memory cells have the same stacked structure (please see figure above).
Regarding claim 8, Watanabe teaches an semiconductor device according to claim 1, wherein the mark includes an insulating film (“STI” are shallow trench isolation).
Regarding claim 10, Watanabe teaches an semiconductor device according to claim 1, wherein the mark includes one or more alignment marks.
Claim(s) 11-14 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (20190088493).
PNG
media_image1.png
367
731
media_image1.png
Greyscale
Regarding claim 11, Watanabe teaches an semiconductor device comprising:
[ a semiconductor substrate including a plurality of first areas and a second area a plane perpendicular to a stacking direction, the second area interposed between adjacent ones of the plurality of first areas;
a plurality of memory arrays provided in the first areas, respectively;
a mark provided in the second area and having a first side surface and a second side surface that intersects with the first side surface; and
a plurality of patterns provided in the second area and provided on the first side surface and the second side surface.] (please see rejection for claim 1 above)
Regarding claim 12, Watanabe teaches an semiconductor device according to claim 11, wherein the plurality of patterns are formed as a linear shape (please see rejection for claim 2).
Regarding claim 13, Watanabe teaches an semiconductor device according to claim 11, wherein the plurality of patterns are formed as a matrix shape (please see rejection for claim 3).
Regarding claim 14, Watanabe teaches an semiconductor device according to claim 11, wherein a width of each of the plurality of patterns is less than a width of the mark (please see rejection for claim 4).
Regarding claim 16, Watanabe teaches an semiconductor device according to claim 11, wherein the plurality of patterns and cells of the memory arrays have the same stacked structure (please see rejection for claim 6).
Allowable Subject Matter
Claim 5 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: a semiconductor device according to claim 1, wherein a width of each of the plurality of patterns is equal to or less than about 10 μm.
Claim 7 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: a semiconductor device according to claim 1, wherein a distance between the mark and the plurality of patterns is equal to or more than about 2.5 μm and equal to or less than about 4 μm.
Claim 9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: a semiconductor device according to claim 1, wherein the first area is a chip area and the second area is a kerf area interposed between the first area and another first area.
Claim 15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: a semiconductor device according to claim 11, wherein a width of each of the plurality of patterns is equal to or less than about 10 μm.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB E HENRY whose telephone number is (571)270-5370. The examiner can normally be reached Mon-Fri.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CALEB E HENRY/Primary Examiner, Art Unit 2818