DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement of RCE Filing
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114.
Applicant's submission filed on 04/16/26 has been entered.
The amendment filed on 04/16/26 has been entered.
Applicant cancelled Claims 1-11 and 14 and added new Claims 15-23.
Status of Claims
Claims 12-13 and 15-23 are examined on merits herein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Na et al. (US 2022/0310541) in view of Hou et al. (US 2022/0352104).
In re Claim 23, Na teaches a semiconductor memory device comprising (Figs. 2A, 3A, 3B; Annotated Portion of Fig. 2A):
a first gate stack – of chip 100 (paragraph 0023) - including a plurality of first conductive patterns 127 (paragraph 0034) stacked spaced apart in a first direction z;
a first channel layer 141 (as numbered in Fig. 3A, and CH1, as Annotated Fig. 2A – as being connected to plug 157a – shown in Figs. 2A and 3A, paragraphs 0040, 0048) extending through the first gate stack;
a first memory layer 143 (as in Fig. 3A, paragraph 0040) between the first channel layer 141 and the first gate stack 127;
a source bonding structure – including first and second bonding pads 166 and 263, accordingly (paragraphs 0052, 0068), source contact plugs 154 (paragraph 0047), and semiconductor layers 115, 215 (paragraphs 0042, 0062) - disposed over the first gate stack and including a first source layer 115 electrically connected to a second source layer 215 (paragraphs 0057, 0060, 0118);
a second gate stack – of chip 200 (paragraph 0023) - including a plurality of second conductive patterns 227 (paragraph 0056) stacked over the source bonding structure, the plurality of second conductive patterns 227 spaced apart in the first direction z;
a second channel layer 241 (Fig. 3B, paragraph 0059, channel 241 is shown under plugs 257a in Fig. 2A, paragraph 0067) extending through the second gate stack; and
a second memory layer 243 (Fig. 3B, paragraph 0059) between the second channel layer 241 and the second gate stack (of conductive patterns 227); wherein
the first source layer 115 includes a first semiconductor layer – as at least one of 115a through 115c (Fig. 3A) connected (paragraph 0042) to the first channel layer 141 and a first conductive layer at least abutting (or being inside) the first semiconductor layer 115: each plug 154 bonded to a corresponding bonding pad 166 shall have a corresponding pad abutting the first semiconductor layer 115 and corresponding to a respective bonding pad 166 – in order to enable connection of each plug 154 to the first semiconductor layer 115; wherein
the second source layer 215 includes a second semiconductor layer – as at least one of 215a through 215c (Fig. 3B) - connected to the second channel layer 241 (paragraph 0060) and a second conductive layer abutting the second semiconductor layer 215: each plug 154 bonded to a corresponding bonding pad 263 shall have a corresponding pad at least abutting (or being inside) the second semiconductor layer 215 and corresponding to a respective bonding pad 263 to enable connection of each plug 154 to the second semiconductor layer 215; wherein
the bonding conductive area between pads 166 and 263 is offset from the first channel layer 141 and the second channel layer 241: a virtual line VL passing through centers of bonding pads 166/263 does not coincide with venters of channel openings – ChO1 and ChO2 - as shown below in an Annotated Portion of Fig. 2A
Annotated Portion of Fig. 2A
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Na does not explicitly teach first and second conductive structures at least abutting (or being inside) the first and second source layers, respectively, and, accordingly, does not teach that these structures are metal structures. However, as it is explained above, the first and second conductive structures, respectively corresponding to first and second bonding pads 166 and 263, shall obviously exist in the Na semiconductor memory device, and, since Na teaches various metal elements, including metal pads 145 (paragraph 0041), it would have been obvious for one of ordinary skill in the art before the effective date of filing the application to create the first and second conductive structures (abutting the first and second source layers, respectively) as metal structures, in order to enable a material for these structures.
Since the above described first and second metal structures correspond to bonding pads 166 and 263, they shall also be offset from the first and second channels, similar to offsets between VL and ChO1 and ChO2.
Na does not teach that the first source layer is bonded to the second source layer, does not teach that the first metal structures are bonded to the second metal structures, e.g., Na does not teach that the source bonding structure includes a semiconductor bonding area between the first semiconductor layer and the second semiconductor layer and a metal bonding area between the first metal layer and the second metal layer.
However, one of ordinary skill in the art before the effective date of filing the application would understand that where it is desirable to reduce a height of the Na’ device, plugs 154 to the first and second metal layers, as well as bonding pads 166 and 263 should be removed, allowing the first and second source layers, with their first and second metal layers to be bonded together, for example, by a hybrid bonding, creating by that a source bonding structure comprising a metal bonding area and a semiconductor bonding area. Note that a hybrid bonding, including bonding of semiconductor layers is widely used in the art, see, for example, Wei et al. (US 2022/0367391) or Jeong et al. (US 2005/0093104) – which these artsd are provided to show a common knowledge in the art on a hybrid bonding, including semiconductors.
Hou teaches a semiconductor die 900 (Fig. 7, Abstract, paragraph 0055) comprised a bonding interface at a top of semiconductor layer 991, where bonding pads 996 are disposed in semiconductor layer 991 and where portions of semiconductor layer 991 and bonding pads 996 laterally alternate with each other.
Na and Hou teach analogous arts directed to a stack of electrically connected dies, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Na device in view of the Hou device, since devices are from the same field of endeavor, and the Hou’ device successfully operates.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Na device by creating a layer in a portion of each of the first and second semiconductor source layers facing to a created layer of an opposing source layer (of another memory die), each layer comprising bonding pads disposed inside a corresponding semiconductor layer with exposed top (or bottom, depending on a memory die position) surfaces and alternating with portions of a semiconductor material of a corresponding source layer – similar to layer 991 of Hou but not through the entire source layer – to avoid accidental contacts with gate lines, – and to bond facing portions of metal bonding pads of the first and second semiconductor source layers and interfacing parts of portions of the first and second source semiconductor layers, creating by that a source bonding structure in which a metal bonding area and semiconductor portions bonding areas would be disposed between remaining parts of the first source layer and the second source layer (e.g., being disposed within a semiconductor layer created by semiconductors of the first and second source layers), when it is desirable to create the semiconductor memory device comprised two bonded memories and a reduced height.
Allowable Subject Matter
Claims 12-13 and 15-22 are allowed.
Reason for Indicating Allowable Subject Matter
Re Claim 12: Although there are prior arts teaches memory stacks comprised three memory arrays with corresponding three sets of bit lines, as Claim 12 claims, (such as Xiao et al., US 2020/0194403), and although there are prior arts (including Oh et al. US 2021/0384160), teaching electrical connections between bit lines belonging to different memories, as Claim 12 also claims, the entirety of limitations of Claim 12 are a little bit complicated to render Claim 12 obvious.
Re Claims 13 and 15-22: Claims 13 and 15-22 are allowed due to dependency on Claim 12.
Response to Arguments
Applicant’ arguments (REMARKS, filed 04/13/26) have been fully considered.
Examiner agrees with the Applicant suggestion on allowability of Claims 12, 13, and 15-22, but views Claims 23 as obvious, and the current Office Action shows that Claim 23 can be easily rejected. Accordingly, the Examiner disagrees with allowability of the entire set of the amended claims.
Conclusion
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible). Examiner interviews are available. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Lynne Gurley can be reached on 571-272-1670.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300; a fax phone number of Galina Yushina is 571-270-8440.
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 04/17/26
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