DETAILED ACTION
Status of Claims
As of the amendment filed 3/3/26, no claims have been added or canceled, and claims 1, 2, 9-12, and 15-16 have been amended. Therefore, claims 1-20 remain pending, with claims 1, 9, and 15 being independent.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2023/0048536) in view of Yu (US 8143162).
As to claim 1, Lin teaches a method of forming a semiconductor structure (100), comprising:
forming a first dielectric layer (24) over a substrate (20, fig. 1, [0016]);
forming a first metal pattern (30) penetrating through the first dielectric layer (24, fig. 1, [0018]);
recessing a portion of the first metal pattern (fig. 2, [0019]);
forming a metal cap (32) on the recessed first metal pattern, wherein top surfaces of the metal cap (32) and the first dielectric layer (24) are levelled (fig. 2, [0019]);
siliciding a surface portion of the metal cap to form a metal silicide pattern (obvious, see below); forming a composite etch stop layer (23) on the first dielectric layer (24) and the metal silicide pattern (fig. 2, [0022]);
forming a second dielectric layer (36) on the composite etch stop layer (24, fig. 3, [0023]);
and forming a second metal pattern (66) penetrating through the second dielectric layer (36) and the composite etch stop layer (34) and landed on the metal silicide pattern (fig. 12, [0047]).
Lin does not teach siliciding a surface portion of the metal cap to form a metal silicide pattern. It is noted that the steps above are not required to be performed in order, thus the siliciding can be performed after the formation and etching of the second dielectric layer. At the stage shown in figures 6 and 7, the metal cap is thinned (32 of fig. 6) and regrown (56 of fig. 7, [0029] and [0031]). At this point in the process, siliciding the metal cap would have been obvious so as to improve the robustness of the metal cap (col. 4:44-48 of the Yu reference shows that a silicided metal cap is known in the art).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to silicide the metal cap for the reasons stated above.
As to claim 2, Yu further teaches siliciding the surface portion of the metal cap comprises: introducing a silicon-containing gas to contact the top surface of the metal cap (col. 4:60-67); and performing a plasma process to react silicon ions of the silicon-containing gas with metal of the surface portion of the metal cap (col. 5:1-5).
As to claim 3, Yu further teaches the silicon-containing gas comprises SiH4, Si(CH3)4, Si(CH3)4, Si(CH3)3H, Si(CH3)2H2, Si2H6, Si3H8 or a combination thereof (SiH4, col. 4:60-62).
As to claims 4 and 5, Yu does not explicitly teach a gas in the plasma process comprises NH3, N2, H2, Ar or a combination thereof; and the plasma process is performed at a temperature from 360oC to 450oC. However, using inert gases for plasma is known in the art and would have been obvious so as to not contaminate the deposition process. Furthermore, determining the temperature is a required process parameter. Optimizing it would have been obvious so as to fabricate a robust layer. If that leads to the range claimed, then that is the result of ordinary skill in the art and not innovation, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233.
As to claim 6, Yu further teaches before introducing the silicon-containing gas to contact the surface of the metal cap, performing a pre-heating and pre-cleaning process to the surface of the metal cap (col. 4:23-30).
As to claim 7, Yu further teaches the pre-heating and pre-cleaning process is performed at a temperature from 280oC to 350oC (obvious for the reasons stated in the rejection of claim 5) under a nitrogen-containing atmosphere (col. 4:28-29).
As to claim 8, Lin further teaches the first metal pattern comprises Cu ([0018]), and the metal cap comprises Co, Ni, Ti, W, Pt or a combination thereof ([0019]).
As to claims 9 and 15, Lin teaches a method of forming a semiconductor structure (100), comprising:
providing a first dielectric layer (24, [0016]);
forming a first metal pattern (30) in the first dielectric layer (24, [0018]);
recessing the first metal pattern (30) by removing an upper portion of the first metal pattern to form a recess in the first dielectric layer ([0019]);
forming a metal cap (32) filling up the recess and on the recessed first metal pattern ([0019]);
forming a metal silicide pattern over the recessed first metal pattern (see rejection of claim 1), wherein the first dielectric layer is disposed along opposite sidewalls of the first metal pattern and opposite sidewalls of the metal silicide pattern (explained below); and
forming a composite etch stop layer (34) on the first dielectric layer and in contact with the metal silicide pattern ([0022]).
Lin shows the dielectric layer (24) disposed along opposite sidewalls of the first metal pattern (30) and the metal cap (32, fig. 2). During the siliciding process, Yu shows the metal cap being consumed by the silicide layer (see figs. 6A and 6B). That is, the height of the metal cap does not change when its top surface is silicided. Thus, the dielectric layer would still be disposed along opposite sidewalls of the first metal pattern, the metal cap metal cap, and the silicide.
As to claim 10, Yu further teaches turning a portion of the metal cap into the metal silicide pattern with a remaining metal cap sandwiched between the first metal pattern and the metal silicide pattern (figs. 6A and 6B, col. 5:11-29).
As to claim 11, Lin further teaches depositing a metal cap material over the first dielectric layer filling the recess ([0019]) and performing a chemical mechanical planarization process to remove the metal cap material outside of the recess and above the first dielectric layer ([0019], “followed by an etching process to remove undesirable portions”, CMP is a well-known etching method in which to remove excess and undesirable portions of a material).
As to claim 12, Yu further teaches forming the metal silicide pattern comprises turning the whole metal cap into the metal silicide pattern (col. 5, line 11, fig. 6A is fully silicided).
As to claim 13, Yu further teaches the metal silicide pattern is formed by siliciding metal in the metal cap (col. 4:60-67).
As to claims 14 and 19, Lin further teaches a dielectric constant of the first dielectric layer (24) is lower than a dielectric constant of the lowermost etch stop layer (34) of the composite etch stop layer by about 10-40%.([0016] and [0022]).
The materials of the dielectric layer and the ESL are different from each other for etch selectivity purposes. Lin teaches the dielectric layer is PSG, BSGB, PSG, FSG, silicon oxide or the like ([0016]), while the bottom layer of a sample composite ESL layer is an aluminum oxide material ([0022]). Aluminum oxide is known to have a higher dielectric constant than doped silicon oxide. Determining the proper concentrations would have been obvious so as to optimize an etch selectivity of the dielectric layer with respect to the ESL layer. If that leads to a difference in dielectric constants between 10-40%, then that is the result of ordinary skill in the art and not innovation.
As to claim 16, Lin further teaches a top surface of the metal silicide pattern is flushed with the a surface of the first dielectric layer (fig. 2, see discussion in claim 9 about consumption of the metal cap when siliciding and how it doesn’t affect the height).
As to claim 17, Lin further teaches the metal cap comprises Co, Ni, Ti, W, Pt or a combination thereof ([0019]).
As to claim 18, Lin further teaches the composite etch stop layer comprises at least two of SiOC, SiCN, SiC, SiN, AIN, Al2O3 and a combination thereof ([0022]).
As to claim 20, Yu further teaches a sidewall of the metal silicide pattern is flushed with a sidewall of the first metal pattern (fig. 6B).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wu (US 2016/0343606). ([0034] of the Wu reference shows that a silicided metal cap is known in the art).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREN M KUSUMAKAR whose telephone number is (571)270-3520. The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST.
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/KAREN KUSUMAKAR/
Primary Examiner, Art Unit 2897
3/18/26