Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The formal drawings filed on 6/9/2023 have been approved by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “ MICROSTRIP EMBEDDED BY AN UNDERFILL ”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 8-10, 12, 15-17, and 19 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Cho et al. (US 10,804,217).
With respect to Claims 1, 8, and 15, Cho teaches a printed circuit board (i.e. carrier) and a semiconductor package coupled to the printed circuit board comprising a package substrate 120. A dielectric underfill layer 140 disposed above the package substrate, wherein the package substrate comprises an embedded microstrip layer 122 embedded in the dielectric underfill layer 140. A semiconductor device 104 or 136 embedded in the dielectric underfill layer 140 and electrically coupled to the embedded microstrip 122 of the package substrate 120. An electromagnetic interference absorber 162 or 172 above a top surface of the semiconductor device 104, wherein the semiconductor device is electrically coupled to the embedded microstrip layer 122 of the package substrate 120 (see col. 4 lines 1-67, col. 5 lines 167, col. 6 lines 1-67, and col. 7 lines 1-67; Figs. 3a, 3b ,5a, and 7f).
With respect to Claims 2, 9, and 16, Cho teaches the electromagnetic interference absorber 162 or 172 is in contact with the top surface of the semiconductor device 104 (see Figs. 3a, 3b ,5a, and 7f).
With respect to Claims 3, 10, and 17, Cho teaches wherein the electromagnetic interference absorber 162 or 172 is not in contact with the top surface of the semiconductor device 136 (see Figs. 3a, 3b ,5a, and 7f).
With respect to Claims 5, 12, and 19, Cho teaches the electromagnetic interference absorber is above a top surface of the package substrate 120 (see Figs. 3a, 3b ,5a, and 7f).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6, 7, 13, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 10,804,217) as applied to claims 1, 8, and 15 above, and further in view of Suwa et al. (US 2006/0192282).
With respect to Claims 6, 7, 13, and 20, Cho discloses die 104 that is a memory device) (see col. 3 lines 9-14). Cho fails to disclose the embedded microstrip layer is configured for high speed signal routing (i.e. DDR memory signal routing)with the semiconductor device.
However, Suwa discloses microstrip layer (i.e. wiring layer) is configured for high speed signal routing (i.e. DDR memory signal routing) with the semiconductor device (i.e. DDR SDRAM) (see paragraphs 3 and 83; Fig. 1). Thus, Cho and Suwa have substantially the same environment of memory chip mounted and electrically attached to a circuit board. Therefore, one skilled in the art before the effective filing date of the claimed invention to substitute the DDR SDRAM chip for the memory chip of Cho, since the microstrip layer would facilitate in providing a DDR signal between the package substrate via the microstrip layer to the memory device as taught by Suwa.
Allowable Subject Matter
9. Claims 4, 11, and 18 are objected to as being dependent upon a rejected
base claim, but would be allowable if rewritten in independent form including all of the
limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowance subject
matter: none of the prior art of record teaches or suggest the combination of
the electromagnetic interference absorber comprises graphene in claim 4.
The prior art made of record and not relied upon is cited primarily to show the
product of the instant invention.
Conclusion
10. Any inquiry concerning the communication or earlier communications from the
examiner should be directed to Alonzo Chambliss whose telephone number is (571)
272-1927.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's
supervisor, Jacob Y. Choi can be reached on (469) 295-9060. The fax phone number
for the organization where this application or proceeding is assigned is (571) 273-8300.
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AC/August 11, 2026 /Alonzo Chambliss/
Primary Examiner, Art Unit 2897
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