Prosecution Insights
Last updated: July 17, 2026
Application No. 18/332,074

POWER SEMICONDUCTOR MODULE ARRANGEMENT AND METHOD FOR FORMING THE SAME

Final Rejection §102§103§112
Filed
Jun 09, 2023
Priority
Jun 27, 2022 — EU 22181245.6
Examiner
HUTSON, NICHOLAS LELAND
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Infineon Technologies AG
OA Round
2 (Final)
60%
Grant Probability
Moderate
3-4
OA Rounds
3m
Est. Remaining
77%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allowance Rate
15 granted / 25 resolved
-8.0% vs TC avg
Strong +17% interview lift
Without
With
+16.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
11 currently pending
Career history
56
Total Applications
across all art units

Statute-Specific Performance

§103
84.5%
+44.5% vs TC avg
§102
14.1%
-25.9% vs TC avg
§112
0.7%
-39.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 25 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The scope of claim 4 is unclear because claim 4 is directed to “the power semiconductor module arrangement of claim 1”, but now the claim is claiming the heat sink, which is not part of the ‘power semiconductor module arrangement’ as part of the claim language. If elements that are not part of the semiconductor module arrangement are desired to be claimed and considered patentably distinct, Applicant should claim: “A semiconductor device comprising: a power semiconductor module arrangement comprising….; a heat sink mounted to and in direct contact with the lower surface of the power semiconductor module… (then the claim can further describe … the connection of how the lower surface of the module is connected to the heat sink). Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-6 and 8-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Berntson (US Publication 20220375817). Regarding claim 1, Berntson teaches a power semiconductor module arrangement comprising a power semiconductor module, wherein the power semiconductor module (Fig. 2 all elements of 100 except heat sink 160 are part of the ‘module’) comprises: a substrate (Fig. 2, 190, 105, and 120 , para 62); and a heat-conducting layer arranged on a lower surface of the power semiconductor module (Fig. 2, 150 is the heat conducting layer on the bottom surface of the module in the instance the module was flipped), wherein the lower surface of the power semiconductor module is a surface that is configured to be mounted to a heat sink (Fig. 2, heat sink 160 attached to module 100 on surface 150), wherein the heat-conducting layer comprises a metallic foam (Fig. 2, 152, para 65) and a layer of solid eutectic material (Fig. 2, 153/151, para 65-66 where the eutectic material is a gallium alloy liquid metal wetting agent that is a solid at room temperature as a typical Phase-Change Metal Alloy PCMA), wherein the metallic foam and the layer of solid eutectic material are separate layers (Fig. 2, 152 and 153/151 are separate layer), wherein the metallic foam is partly pressed into the layer of solid eutectic material such that the metallic foam is adhered to the layer of solid eutectic material (para 75), and wherein the layer of solid eutectic material is configured to liquify upon heating so as to fill cavities within the metallic foam (para 65-69 and 10). Regarding claim 2, Berntson teaches the limitations of claim 1 upon which claim 2 depends. Berntson teaches wherein the lower surface of the power semiconductor module is formed by a surface of the substrate (Fig. 2 surface of 120, para 62). Regarding claim 3, Berntson teaches the limitations of claim 1 upon which claim 3 depends. Berntson teaches wherein the power semiconductor module further comprises a base plate, wherein the substrate is arranged on a first surface of the base plate and the lower surface of the power semiconductor module is formed by a second surface of the base plate opposite the first surface (Fig. 2, baseplate 140, para 62, lower facing 190 and upper facing 160). Regarding claim 4, Berntson teaches the limitations of claim 1 upon which claim 4 depends. Berntson teaches further comprising [[a]] the heat sink mounted to the lower surface of the power semiconductor module (Fig. 2, 160 on the bottom surface of the module in the instance the module was flipped), wherein the heat-conducting layer forms a substance-to-substance bond between the power semiconductor module and the heat sink (Fig. 2, 150, including elements 151-153 form the substance-to-substance bond between all the elements of the module 100 [excluding 160] and 160). Regarding claim 5, Berntson teaches the limitations of claim 1 upon which claim 5 depends. Berntson teaches wherein the eutectic material is solid at temperatures below a threshold temperature, and is fluid at temperatures above the threshold temperature, and wherein the threshold temperature is between 60 and 90°C (para 16, "or mixtures thereof", understood to include Field's metal with a phase change temperature of 62 C). Regarding claim 6, Berntson teaches the limitations of claim 1 upon which claim 6 depends. Berntson teaches wherein the metallic foam is compressible (para 13, "compress the solid metal foam"). Regarding claim 8, Berntson teaches a method for producing a power semiconductor module arrangement, the method comprising: arranging a layer of solid eutectic material on a lower surface of a power semiconductor module, the lower surface of the power semiconductor module being configured to be mounted to a heat sink (Fig. 2, layer of 151 on surface of 150 to be mounted to 160, para 65-66 where the eutectic material is a gallium alloy liquid metal wetting agent that is a solid at room temperature as a typical Phase-Change Metal Alloy PCMA); and arranging a metallic foam on the layer of solid eutectic material (Fig. 2, 152 with layers 153 and 151), wherein the layer of solid eutectic material is configured to fill cavities within the metallic foam when heated (para 55). Regarding claim 9, Berntson teaches the limitations of claim 8 upon which claim 9 depends. Berntson teaches wherein the metallic foam is arranged on the layer of solid eutectic material after the layer of solid eutectic material is arranged on the lower surface of the power semiconductor module (para 65, Fig. 2, 132 arranged on 131 once applied on 120). Regarding claim 10, Berntson teaches the limitations of claim 8 upon which claim 10 depends. Berntson teaches wherein arranging the layer of solid eutectic material on the lower surface of the power semiconductor module comprises forming the layer of solid eutectic material using a dispensing process (para 14, "dispensing"). Regarding claim 11, Berntson teaches the limitations of claim 8 upon which claim 11 depends. Berntson teaches wherein arranging the layer of solid eutectic material on the lower surface of the power semiconductor module comprises forming the layer of solid eutectic material using a printing process (para 69, “There are various methods that can be employed to apply liquid metal wetting agents to the device thermal stack up. The liquid metal can be scrubbed, dispensed, or jetted onto the surface(s) of the foam(s), heat sink 160, package lid 140 and/or semiconductor die 120.” Where jetted is understood to be a 3D printing process). Regarding claim 12, Berntson teaches the limitations of claim 8 upon which claim 12 depends. Berntson teaches wherein arranging the metallic foam on the layer of solid eutectic material comprises pressing the metallic foam into the layer of solid eutectic material so that the metallic foam penetrates and adheres to the layer of solid eutectic material (para 22, "the TIM comprising a solid metal foam and a first liquid metal; and compressing the TIM to form the alloy from the TIM"). Regarding claim 13, Berntson teaches the limitations of claim 8 upon which claim 13 depends. Berntson teaches further comprising: heating the layer of solid eutectic material so that the solid eutectic material liquefies and soaks into the metallic foam (para 69, where it is understood that heating of the eutectic material is necessary for the dispensing process listed). Regarding claim 14, Berntson teaches the limitations of claim 13 upon which claim 14 depends. Berntson teaches wherein heating the layer of solid eutectic material comprises operating the power semiconductor module (para 22, "heat generating device such as a semiconductor die"). Regarding claim 15, Berntson teaches a method for producing a power semiconductor module arrangement, the method comprising: pressing a metallic foam into a layer of eutectic material (para 22, "the TIM comprising a solid metal foam and a first liquid metal; and compressing the TIM to form the alloy from the TIM"); heating the layer of eutectic material so that the eutectic material liquefies and soaks into the metallic foam so as to form a heat-conducting layer (para 69, where it is understood that heating of the eutectic material is necessary for the dispensing process listed); and attaching the heat-conducting layer to a lower surface of a power semiconductor module (Fig. 2, 150 attached to 120). Regarding claim 16, Berntson teaches the limitations of claim 15 upon which claim 16 depends. Berntson teaches before attaching the heat-conducting layer to the lower surface of the power semiconductor module, cooling the heat-conducting layer so that the eutectic material becomes solid (para 75). Regarding claim 17, Berntson teaches the limitations of claim 15 upon which claim 17 depends. Berntson teaches wherein attaching the heat-conducting layer to the lower surface of the power semiconductor module comprises tacking, hot rolling, or laminating the heat-conducting layer on the lower surface of the power semiconductor module (para 8, laminating with layers and compression). Regarding claim 18, Berntson teaches the limitations of claim 15 upon which claim 18 depends. Berntson teaches wherein attaching the heat-conducting layer to the lower surface of the power semiconductor module comprises: arranging the heat-conducting layer on the lower surface of the power semiconductor module (Fig. 2, 150 attached to 120); and cooling the heat-conducting layer so that the eutectic material becomes solid and adheres to the lower surface of the semiconductor module (para 75). Regarding claim 19, Berntson teaches the limitations of claim 18 upon which claim 19 depends. Berntson teaches further comprising: before arranging the heat-conducting layer on the lower surface of the power semiconductor module, heating the heat-conducting layer so that the eutectic material liquefies (para 69, where it is understood that heating of the eutectic material is necessary for the dispensing process listed). Regarding claim 20, Berntson teaches the limitations of claim 15 upon which claim 20 depends. Berntson teaches attaching a heat sink to the power semiconductor module, such that the heat- conducting layer is arranged between the power semiconductor module and the heat sink (Fig. 2, 160 attached to 100 such that 150 is between 120 and 160). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Berntson (US Publication 20220375817) in view of Park et al (US Publication 20220209167). Regarding claim 7, Berntson teaches the limitations of claim 1 upon which claim 7 depends. Berntson does not specifically teach wherein a thickness of the metallic foam in a vertical direction that is perpendicular to the lower surface of the power semiconductor module is between 50µm and 500µm. Park teaches wherein a thickness of the metallic foam in a vertical direction that is perpendicular to the lower surface of the power semiconductor module is between 50µm and 500µm (para 166, "a thickness of the metal foam 320 can be in a range of 20 μm to 200 μm"). It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Berntson to include the metallic foam thickness as taught by Park in order to improve the thermal dissipation properties of the device. Claims 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Berntson (US Publication 20220375817) in view of Kim et al (US Publication 20150168087). Regarding claim 21, Berntson teaches a power semiconductor module arrangement comprising a power semiconductor module, wherein the power semiconductor module comprises: a substrate (Fig. 2, between 120 and 105, para 62); and a heat-conducting layer arranged on a lower surface of the power semiconductor module (Fig. 2, 130), wherein the lower surface of the power semiconductor module is a surface that is configured to be mounted to a heat sink (Fig. 2, heat sink 160 attached to module 100), wherein the heat-conducting layer comprises a metallic foam (Fig. 2, 132, para 65) and a layer of eutectic material (Fig. 2, 133/131, para 65). wherein the layer of eutectic material is configured to liquify upon heating so as to fill cavities within the metallic foam (para 69, where it is understood that heating of the eutectic material is necessary for the dispensing process listed). Berntson does not specifically teach: wherein the metallic foam comprises at least one of aluminum, copper, steel, nickel, silver, gold, platinum, and palladium, and Kim teaches: wherein the metallic foam comprises at least one of aluminum, copper, steel, nickel, silver, gold, platinum, and palladium (Fig. 5, 82, para 30), and It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Berntson to include the metallic foam materials as taught by Kim in order to improve the thermal, manufacturing, and shipping and handling properties of the device. Regarding claim 22, Berntson teaches a power semiconductor module arrangement comprising a power semiconductor module, wherein the power semiconductor module comprises: a substrate (Fig. 2, between 120 and 105, para 62); and a heat-conducting layer arranged on a lower surface of the power semiconductor module (Fig. 2, 130), wherein the lower surface of the power semiconductor module is a surface that is configured to be mounted to a heat sink (Fig. 2, heat sink 160 attached to module 100), wherein the heat-conducting layer comprises a metallic foam (Fig. 2, 132, para 65) and a layer of eutectic material (Fig. 2, 133/131, para 65). Berntson does not specifically teach: wherein the layer of eutectic material is configured to liquify upon heating so as to form a liquified eutectic material that fill cavities within the metallic foam but does not alloy with the metallic foam. Kim teaches: wherein the layer of eutectic material is configured to liquify upon heating so as to form a liquified eutectic material that fill cavities within the metallic foam but does not alloy with the metallic foam (para 36, ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Berntson to include the eutectic material as taught by Kim in order to improve the thermal, manufacturing, and shipping and handling properties of the device. Response to Arguments Applicant's arguments filed 16 February 2026 have been fully considered but they are not persuasive. Regarding claims 1, 8, and 15 applicant argues that Berntson does not teach or render obvious a solid eutectic layer. Applicant cites Berntson, para 65, liquid metal wetting agents 131/133 and 151/153 as teaching the eutectic material is a liquid and not a solid. Liquid metal wetting agents are commonly stored, handled, and applied in solid form as solid preforms, blocks, or pastes. In the instant application para 28 the eutectic material is stated as comprising “51 weight % of indium, 32.5 weight % of bismuth, and 16.5 weight % of tin” also known as Field’s metal. Field’s metal is known to be in a semi-solid or paste state during pattern-dispensing or stencil printing, which is also the stated process of deposition in the instant application para 40. Also note that a new reference to Kim et al (US Publication 20150168087) was used to reject new claims 21 and 22. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS HUTSON whose telephone number is (571)270-1750. The examiner can normally be reached Mon-Fri 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at 571 272 2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NICHOLAS LELAND HUTSON/ Examiner, Art Unit 2818 /JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Jun 09, 2023
Application Filed
Dec 03, 2025
Non-Final Rejection mailed — §102, §103, §112
Feb 16, 2026
Response Filed
Jun 02, 2026
Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12685164
SEMICONDUCTOR PACKAGE AND COOLING SYSTEM THEREOF
3y 7m to grant Granted Jul 14, 2026
Patent 12520553
Forming Seams with Desirable Dimensions in Isolation Regions
3y 10m to grant Granted Jan 06, 2026
Patent 12512379
LOW-PROFILE SEALED SURFACE-MOUNT PACKAGE
3y 4m to grant Granted Dec 30, 2025
Patent 12422210
TECHNIQUES AND DEVICE STRUCTURES BASED UPON DIRECTIONAL DIELECTRIC DEPOSITION AND BOTTOM-UP FILL
3y 1m to grant Granted Sep 23, 2025
Patent 12419082
Field Effect Transistor Device
2y 10m to grant Granted Sep 16, 2025
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
60%
Grant Probability
77%
With Interview (+16.7%)
3y 4m (~3m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 25 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month