DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 20 is objected to because “wherein a portion of the mold layer or extends into the first dielectric layer and a portion of the second conductive patterns” is grammatically incorrect. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 8, 11-14, and 19 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Park (US 2019/0252306).
Regarding claim 1, Park discloses a semiconductor package (Figures 37A , 37B), comprising:
a package substrate (101);
a semiconductor chip (120) on the package substrate (101, see Figure 37A); and
a mold layer (140) on the package substrate (101) and the semiconductor chip (120, see Figure 37A),
wherein the package substrate (101) includes:
a body layer (10);
first conductive patterns (left half portion of conductive patterns 22a plus left half portion of adhesion promoter pattern 24a in Figure 37A, the conductive patterns 22a and adhesion promoter layer 24a are thermally conductive, 22a being formed of copper, see para. [0042], and the adhesion promoter layer 24a being formed of aluminum oxide, see para. [0044], thus 22a and 24a together are considered as conductive patterns since “conductive pattern” can also include thermally conductive patterns, not exclusively electrically conductive) and second conductive patterns (right half portion of conductive patterns 22a plus right half portion of adhesion promoter pattern 24a in Figure 37A, the conductive patterns 22a and adhesion promoter layer 24a are thermally conductive, 22a being formed of copper, see para. [0042], and the adhesion promoter layer 24a being formed of aluminum oxide, see para. [0044], thus 22a and 24a together are considered as conductive patterns since “conductive pattern” can also include thermally conductive patterns, not exclusively electrically conductive) on the body layer (10, see Figure 37A); and
a first dielectric layer (26a) on the second conductive patterns (right half of conductive patterns 22a/24a in Figure 37A, the first dielectric layer 26a is on a portion of the second conductive patterns) and at least one of the first conductive patterns (left half portion of conductive patterns 22a/24a in Figure 37A),
wherein a portion of the mold layer (140) extends into the first dielectric layer (26a) and a portion of the second conductive patterns (right half of conductive patterns 22a/24a, see Figure 37A which shows the mold layer extending through a portion of the second conductive patterns, the portion being the conductive pattern 22a connected to the bond wire 126) and contacts the body layer (10, see Figure 37B which shows direct physical contact between the body layer 10 and the mold layer 140); and
wherein at least some of the first conductive patterns (left half portion of 22a/24a) and at least some of the second conductive patterns (right half portion of 22a/24a) are in direct contact with both the first dielectric layer (26a) and the mold layer (140, Figure 37B shows side surfaces of the 24a portion of the 22a/24a first/second conductive patterns directly contacting the first dielectric layer 26a and the mold layer 140).
Regarding claim 2, Park discloses:
wherein an adhesive force between the body layer (10) and the mold layer (140) is greater than an adhesive force between the first dielectric layer (26a) and the mold layer (140).
Park discloses that the body layer 10 comprises a prepreg (see para. [0041]), the mold layer 140 comprises an epoxy material (see para. [0098]), and the first dielectric layer comprises an epoxy-containing layer (see para. [0043]). Paragraphs [0016], [0019], and [0035] of the instant specification disclose that the body layer 50 is a prepreg material, the molding layer MD is an epoxy molding compound, and the first dielectric layer is an epoxy-containing layer. Thus, since Applicant has disclosed the same materials for the body layer, the mold layer, and the first dielectric layer as Park’s body layer, mold layer, and first dielectric layer, respectively, Park’s adhesive force between the body layer and the mold layer would also be greater than an adhesive force between the first dielectric layer and the mold layer.
Regarding claim 3, Park discloses:
the body layer (10) includes a prepreg (see para. [0041]), and
the mold layer (140) includes an epoxy molding compound (see para. [0089]).
Regarding claim 8, Park discloses:
wherein the mold layer (140) contacts a sidewall of the first dielectric layer (26a, see Figure 37A) and a sidewall of the portion of the second conductive patterns (right potion of conductive patterns 22a/24a, see Figures 37A and 37B which show contact between a sidewall of a portion of the second conductive patterns).
Regarding claim 11, Park discloses:
the second conductive patterns (right portion of conductive patterns 22a/24a) have a network shape in a horizontal plane (Figure 37A shows a cross-sectional view of a horizontal plane, which shows the network pattern of the second conductive patterns).
Regarding claim 12, Park discloses a semiconductor package (Figures 37A, 37B), comprising:
a package substrate (101);
a semiconductor chip (120) on the package substrate (101, see Figure 37A); and
a mold layer (140) on the package substrate (101) and the semiconductor chip (120, see Figure 37A),
wherein the package substrate (101) includes:
a body layer (10);
first conductive patterns (left half portion of conductive patterns 22a plus left half portion of adhesion promoter pattern 24a in Figure 37A, the conductive patterns 22a and adhesion promoter layer 24a are thermally conductive, 22a being formed of copper, see para. [0042], and the adhesion promoter layer 24a being formed of aluminum oxide, see para. [0044], thus 22a and 24a together are considered as conductive patterns since “conductive pattern” can also include thermally conductive patterns, not exclusively electrically conductive) and second conductive patterns (right half portion of conductive patterns 22a plus right half portion of adhesion promoter pattern 24a in Figure 37A, the conductive patterns 22a and adhesion promoter layer 24a are thermally conductive, 22a being formed of copper, see para. [0042], and the adhesion promoter layer 24a being formed of aluminum oxide, see para. [0044], thus 22a and 24a together are considered as conductive patterns since “conductive pattern” can also include thermally conductive patterns, not exclusively electrically conductive) on the body layer (10, see Figure 37A); and
a first dielectric layer (26a) on the second conductive patterns (right half of conductive patterns 22a/24a in Figure 37A, the first dielectric layer 26a is on a portion of the second conductive patterns) and at least one of the first conductive patterns (left half portion of conductive patterns 22a/24a in Figure 37A),
wherein a portion of the mold layer (140) extends into the first dielectric layer (26a) and a portion of the second conductive patterns (right half of conductive patterns 22a/24a, see Figure 37A which shows the mold layer extending through a portion of the second conductive patterns, i.e. the central second conductive pattern connected to the bond wire 126) and contacts the body layer (10, see Figure 37B which shows direct physical contact between the body layer 10 and the mold layer 140), and
contacts a sidewall of the first dielectric layer (26a, see Figure 37A and 37B) and a sidewall of the portion of the second conductive patterns (right potion of conductive patterns 22a/24a, see Figures 37A and 37B which show contact between a sidewall of a portion of the second conductive patterns); and
wherein at least some of the first conductive patterns (left half portion of 22a/24a) and at least some of the second conductive patterns (right half portion of 22a/24a) are in direct contact with both the first dielectric layer (26a) and the mold layer (140, Figure 37B shows side surfaces of the 24a portion of the 22a/24a first/second conductive patterns directly contacting the first dielectric layer 26a and the mold layer 140).
Regarding claim 13, Park discloses:
wherein an adhesive force between the body layer (10) and the mold layer (140) is greater than an adhesive force between the first dielectric layer (26a) and the mold layer (140).
Park discloses that the body layer 10 comprises a prepreg (see para. [0041]), the mold layer 140 comprises an epoxy material (see para. [0098]), and the first dielectric layer comprises an epoxy-containing layer (see para. [0043]). Paragraphs [0016], [0019], and [0035] of the instant specification disclose that the body layer 50 is a prepreg material, the molding layer MD is an epoxy molding compound, and the first dielectric layer is an epoxy-containing layer. Thus, since Applicant has disclosed the same materials for the body layer, the mold layer, and the first dielectric layer as Park’s body layer, mold layer, and first dielectric layer, respectively, Park’s adhesive force between the body layer and the mold layer would also be greater than an adhesive force between the first dielectric layer and the mold layer.
Regarding claim 14, Park discloses:
the body layer (10) includes a prepreg (see para. [0041]), and
the mold layer (140) includes an epoxy molding compound (see para. [0089]).
Regarding claim 19, Park discloses:
wherein the second conductive patterns (right portion of conductive patterns 22a/24a) have a network shape in a horizontal plane (Figure 37A shows a cross-sectional view of a horizontal plane, which shows the network pattern of the second conductive patterns).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to claims 1 and 3 above and further in view of Kwon et al. (“Kwon” US 2020/0273830).
Regarding claim 4, Park does not disclose a plurality of filler particles in the mold layer.
However, Kwon discloses in Figures 1 and 4 a plurality of filler particles (f1) in a mold layer. (insulating material 103, see Figure 4)
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Kwon above into the teachings of Park for the purpose of improving durability of the package and reducing the possibility of thermal damage to the package (see Kwon, para. [0062]-[0063]).
Regarding claim 5, Park discloses a portion of the mold layer (140) is in each of a plurality of holes (holes defined by spaces between the conductive patterns 22a, through which the mold layer 140 extends) formed in the first dielectric layer (hole also extends through the dielectric layer 26a, see Figure 37A) and the portion of the second conductive patterns (right portion of conductive patterns 22a/24a, see Figure 37A, here the portion is the conductive patterns connected to the bond wire 126).
Park does not disclose that one or more of the plurality of filler particles are within each of the plurality of holes.
Kwon discloses in Figures 1 and 4 that one or more of the plurality of filler particles (f1) are within each of the holes (the holes are defined by spaces between the conductive traces 105 in Figures 1 and 4, see filler particles f1 within each of the holes).
Regarding claim 6, Park discloses that each of the plurality of holes (spaces between conductive traces 22a/24a through which the mold layer 140 extends) has a tetragonal, a polygonal, or a circular shaped cross section parallel to the package substrate (101, Figure 37A shows the cross section parallel to the package substrate’s front facing side, Figure 37A also shows polygonal shaped holes).
Park does not disclose filler particles, thus does not disclose a width of each of the plurality of holes is 2 times to 4 times a diameter of each of the plurality of filler particles.
Kwon discloses that a width of each of the plurality of holes (separation distance d2, see Figure 1 and para. [0072], is between 0.5 microns and 3 microns) is 2 times to 4 times a diameter of each of the plurality of filler particles (f1, with a diameter of about 0.1 microns to 10 microns, thus the range of the prior art and the claimed range overlap, Figure 4 also approximately shows this ratio of width/diameter).
Regarding claim 7, Park discloses wherein a space between each of the plurality of holes (here, a space between the holes is an arbitrarily chosen distance between the holes through which the mold layer 140 extends and contacts the body layer 10 which has the same width of the holes itself) is the same as the width of each of the plurality of the holes (width of the portion of the mold layer 140 that extends into the hole between the traces 22a/24a, see Figure 37B and annotated Figure 37B below).
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Regarding claim 9, Kwon discloses wherein some of the plurality of filler particles (f1) are distributed on the first dielectric layer (insulating layer 105, see Figure 4).
Claims 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to claim 14 above and further in view of Kwon et al. (“Kwon” US 2020/0273830).
Regarding claim 15, Park does not disclose a plurality of filler particles.
However, Kwon discloses in Figures 1 and 4 a plurality of filler particles (f1) in a mold layer. (insulating material 103, see Figure 4)
It would have been obvious to one having ordinary skill in the art to incorporate filler particles in a mold layer as taught by Kwon into the teachings of Park for the purpose of reducing potential thermal damage to the semiconductor package (Kwon, para. [0062]).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Kwon above into the teachings of Park for the purpose of improving durability of the package and reducing the possibility of thermal damage to the package (see Kwon, para. [0062]-[0063]).
Regarding claim 16, Park discloses that the portion of the mold layer (140) is in each of a plurality of holes formed in the first dielectric layer and the portion of the second conductive patterns (holes defined by spaces between second conductive patterns, right half portion of conductive patterns 22a/24a, the mold layer 140 extends into each of the plurality of holes).
Park does not disclose filler particles. However, Kwon discloses in Figures 1 and 4 that one or more of the plurality of filler particles (f1) are within each of the holes (the holes are defined by spaces between the conductive traces 105 in Figures 1 and 4, see filler particles f1 within each of the holes).
Regarding claim 17, Park discloses that each of the holes (spaces between second conductive patterns, right half portion of conductive patterns 22a/24a) has a tetragonal, a polygonal, or a circular shaped cross section parallel to the package substrate (101, Figure 37A shows the cross section parallel to the package substrate’s front facing side, Figure 37A also shows polygonal shaped holes).
Park does not disclose a width of each of the holes is 2 times to 4 times a diameter of ones of the plurality of filler particles.
Kwon discloses that a width of each of the plurality of holes (separation distance d2, see Figure 1 and para. [0072], is between 0.5 microns and 3 microns) is 2 times to 4 times a diameter of each of the plurality of filler particles (f1, with a diameter of about 0.1 microns to 10 microns, thus the range of the prior art and the claimed range overlap, Figure 4 also approximately shows this ratio of width/diameter).
Regarding claim 18, Park discloses: wherein an interval between the holes (here, the interval, which is interpreted as an intervening space, see Merriam-Webster dictionary definition of “interval”, between the holes is an arbitrarily chosen distance between the holes through which the mold layer 140 extends and contacts the body layer 10 which has the same width of the holes itself) is the same as a width of each of the holes (width of the portion of the mold layer 140 that extends into the hole between the traces 22a/24a, see Figure 37B and annotated Figure 37B below).
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Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2019/0252306) and Kwon et al. (“Kwon” US 2020/0273830).
Regarding claim 20, Park discloses a semiconductor package (Figures 37A, 37B), comprising:
a package substrate (101);
a semiconductor chip (120) on the package substrate (101, see Figure 37A); and
a mold layer (140) on the package substrate (101) and the semiconductor chip (120, see Figure 37A),
wherein the package substrate (101) includes:
a body layer (10);
first conductive patterns (left half portion of conductive patterns 22a plus left half portion of adhesion promoter pattern 24a in Figure 37A, the conductive patterns 22a and adhesion promoter layer 24a are thermally conductive, 22a being formed of copper, see para. [0042], and the adhesion promoter layer 24a being formed of aluminum oxide, see para. [0044], thus 22a and 24a together are considered as conductive patterns since “conductive pattern” can also include thermally conductive patterns, not exclusively electrically conductive) and second conductive patterns (right half portion of conductive patterns 22a plus right half portion of adhesion promoter pattern 24a in Figure 37A, the conductive patterns 22a and adhesion promoter layer 24a are thermally conductive, 22a being formed of copper, see para. [0042], and the adhesion promoter layer 24a being formed of aluminum oxide, see para. [0044], thus 22a and 24a together are considered as conductive patterns since “conductive pattern” can also include thermally conductive patterns, not exclusively electrically conductive) on the body layer (10, see Figure 37A);
a first dielectric layer (26a) that covers the second conductive patterns (right half portion of the conductive patterns 22a/24a, see Figure 37A which shows the first dielectric layer 26a covering at least a portion of the second conductive patterns) and at least one of the first conductive patterns (left half portion of the conductive patterns 22a/24a, see Figure 37A);
third conductive patterns (22b) on a bottom surface of the body layer (10, see Figure 37A); and
external terminals (130) bonded to the third conductive patterns (22b, bonded directly to the third conductive patterns 22b in Figure 37A, see also para. [0099]),
wherein a portion of the mold layer (140) or extends into the first dielectric layer (26a) and a portion of the second conductive patterns (right half portion of conductive patterns 22a/24a, see Figure 37A) and contacts the body layer (10, see Figures 37A and 37B) and is in a plurality of holes formed in the first dielectric layer (26a, see holes between conductive patterns 22a into which the mold layer at least partially extends into and occupies in Figures 37A and 37B, para. [0043]) and the portion of the second conductive patterns (right half portion of conductive patterns 22a/24a, see holes also extends through a portion of the second conductive patterns), and
wherein each of the plurality of holes has a tetragonal, a polygonal, or a circular shaped cross section parallel to the package substrate (101, Figure 37A shows the cross section parallel to the package substrate’s front facing side, Figure 37A also shows polygonal shaped holes),
wherein at least some of the first conductive patterns (left half portion of 22a/24a) and at least some of the second conductive patterns (right half portion of 22a/24a) are in direct contact with both the first dielectric layer (26a) and the mold layer (140, Figure 37B shows side surfaces of the 24a portion of the 22a/24a first/second conductive patterns directly contacting the first dielectric layer 26a and the mold layer 140).
Park does not disclose that the mold layer includes a plurality of filler particles, wherein one or more of the plurality of filler particles are within each of the holes, and that a width of each of the plurality of holes is 2 times to 4 times a diameter of each of the plurality of filler particles.
However, Kwon discloses in Figures 1 and 4 a mold layer (insulating layer 103) including a plurality of filler particles (f1), wherein one or more of the plurality of filler particles (f1) are within each of the holes (the holes are defined by spaces between the conductive traces 105 in Figures 1 and 4, see filler particles f1 within each of the holes), and that a width of each of the plurality of holes (separation distance d2, see Figure 1 and para. [0072], is between 0.5 microns and 3 microns) is 2 times to 4 times a diameter of each of the plurality of filler particles (f1, with a diameter of about 0.1 microns to 10 microns, thus the range of the prior art and the claimed range overlap, Figure 4 also approximately shows this ratio of width/diameter).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Kwon above into the teachings of Park for the purpose of improving durability of the package and reducing the possibility of thermal damage to the package (see Kwon, para. [0062]-[0063]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to claim 1 above, and further in view of Chen et al. (“Chen” US 2023/0395581).
Regarding claim 10, Park does not disclose that the first conductive patterns are supplied with a signal voltage, and the second conductive patterns are supplied with a ground voltage or a power voltage.
However, Chen discloses in Figure 5A first conductive patterns (118) and second conductive patterns (106) on a body layer (substrate core 110A), and that the first conductive patterns (118) are supplied with a signal voltage (disclosed in para. [0013]), and the second conductive patterns (106) are supplied with a ground voltage or a power voltage (para. [0010] discloses that the second conductive patterns 106 may be used for routing electrical signals, power, and/or ground lines).
All of the claimed elements are evidenced as known in Park except for the electrical line/reference with which each conductive pattern is associated. Chen discloses a finite number of options for electrical lines, namely signal, power, or ground. One of ordinary skill in the art would have recognized the finite number of predictable solutions for the type of electrical lines that could be associated with each conductive pattern as evidenced by Chen. Absent unexpected results, it would have been obvious to try each electrical line to yield a suitable routing configuration for the electrical component(s) in the semiconductor package. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
In the event that the Examiner has misconstrued Park as teaching the limitations of claims 2 and 13, which the Examiner does not concede, claims 2 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to claims 1 and 12 above, and further in view of Takeshima (US 2011/0291244).
Regarding claim 2, Takeshima discloses in Figure 1 a body layer (111), a mold layer (15), and a first dielectric layer (112), where an adhesive force between the body layer (111) and the mold layer (15) is greater than an adhesive force between the first dielectric layer (112) and the mold layer (15, see para. [0056] which discloses this relationship of adhesive strengths).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Takeshima above into the teachings of Park for the purpose of reducing the possibility of separation or delamination of the sealing resin and the insulating layer of the wiring substrate (Takeshima, para. [0056]).
Regarding claim 13, Takeshima discloses in Figure 1 a body layer (111), a mold layer (15), and a first dielectric layer (112), where an adhesive force between the body layer (111) and the mold layer (15) is greater than an adhesive force between the first dielectric layer (112) and the mold layer (15, see para. [0056] which discloses this relationship of adhesive strengths).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Takeshima above into the teachings of Park for the purpose of reducing the possibility of separation or delamination of the sealing resin and the insulating layer of the wiring substrate (Takeshima, para. [0056]).
Response to Arguments
Applicant’s arguments with respect to claims 1, 12, and 20 have been considered but are moot because the new ground of rejection does not rely on any interpretation of the reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s amendments regarding the 112(b) rejections of claims 6, 17, and 20, filed March 19 2026, have been fully considered and overcome the 112(b) rejection. The 112(b) rejection of claims 6, 17, and 20 has been withdrawn.
Applicant's arguments regarding the objection to claim 20 have been fully considered but they are not persuasive. Claim 20 has does not appear to have been amended to fix the grammatical errors.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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