Prosecution Insights
Last updated: April 19, 2026
Application No. 18/332,149

FULLY ALIGNED VIA INTEGRATION WITH SELECTIVE CATALYZED VAPOR PHASE GROWN MATERIALS

Non-Final OA §102§103
Filed
Jun 09, 2023
Examiner
PARKER, JOHN M
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
93%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allow Rate
763 granted / 831 resolved
+23.8% vs TC avg
Minimal +1% lift
Without
With
+0.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
24 currently pending
Career history
855
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
43.5%
+3.5% vs TC avg
§102
37.3%
-2.7% vs TC avg
§112
14.1%
-25.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 831 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-11 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Parikh et al. (US Pat. Pub. 2020/0144117). Regarding claim 1, Parikh teaches an electronic device, comprising: a first dielectric layer [fig. 9b, 104]; a metal patterned in the first dielectric layer [fig. 9b, 108]; a second dielectric layer deposited on the first dielectric layer [fig. 9b, 116]; and a metal via deposited in a channel in the second dielectric layer, the metal via being in contact with the patterned metal in the first dielectric layer [fig. 9b, 120], wherein the channel is formed by removing at least a portion of a nanowall formed on the metal in the first dielectric layer [fig. 9b, channel is formed through 116 as well as 114 which is being interpreted as nanowall, the act of removing a portion of 114 is considered a product by process limitation. A channel being present in a second dielectric layer and a nanowall is all that is required. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), see MPEP 2113]. Regarding claim 2, Parikh discloses the electronic device of claim 1, wherein the nanowall comprises a dielectric nanowall [paragraph [0055] teaches 114 is silicon dioxide among others, and it is 10nm or greater in thickness, paragraph [0025] of applicants specification teaches the layer labeled dielectric nanowall is silicon dioxide and is 5nm to 50nm thick]. Regarding claim 3, Parikh teaches the electronic device of claim 2, further comprising a third dielectric layer deposited on the second dielectric layer and the dielectric nanowall [fig. 9b, 125, paragraph [0080] teaches silicon nitride]. Regarding claim 4, Parikh discloses the electronics device of claim 3, further comprising a space etching in the third dielectric layer above the dielectric nanowall [fig. 10b, 125 has been etched]. Regarding claim 5, Parikh teaches the electronic device of claim 4, wherein the metal via is deposited in the space in the third dielectric layer [fig. 10b, 120 is in a space between 125 on either side]. Regarding claim 6, Parikh discloses the electronic device of claim 3, further comprising a metal layer deposited on the third dielectric layer [fig. 11b, 130]. Regarding claim 7, while Parikh teaches a layer interpreted as the nanowall, they fail to teach the nanowall is formed by VLS growth. However, this is a product by process limitation and the method by which a layer is formed is not given patentable weight, only the final product of the layer being present. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), see MPEP 2113. Regarding claim 8, Parikh teaches the electronic device of claim 2, wherein the nanowall comprises a semiconductor nanowall [paragraph [0055] teaches 114 is silicon dioxide among others, and it is 10nm or greater in thickness, paragraph [0027] of applicants specification teaches the layer labeled semiconductor nanowall is silicon dioxide and is 5nm to 50nm thick]. Regarding claim 9, Parikh discloses the electronic device of claim 8, wherein the semiconductor nanowall is Si-based or Ge-based [paragraph [0055] teaches silicon based materials, it is noted that no support appears present for germanium based nanowalls, at least where “semiconductor nanowalls” are disclosed in the invention]. Regarding claim 10, Parikh teaches the electronic device of claim 8, further comprising a dielectric material deposited in the channel [fig. 10b, 125]. Regarding claim 11, Parikh discloses the electronic device of claim 10, wherein the dielectric material comprises SiN [paragraph [0080], 125 is SiN]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Parikh as applied to claims 1-11 above, and further in view of Wada et al. (US Pat. Pub. 2012/0049370). Regarding claim 12, Parikh fails to teach a third dielectric layer deposited on the second dielectric layer and over the third dielectric material in the channel. However, Wada teaches an interconnect structure in which multiple levels of dielectric and wiring are formed on one another, including a first dielectric with a first metal, a second dielectric with a second metal and a third dielectric over a second dielectric [fig. 1, first dielectric 11, metal 12, second dielectric 14, second metal 16, third dielectric 24, third metal 26]. It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Wada into the method of Parikh by forming a third dielectric layer over the second dielectric layer and over the dielectric material in the channel. The ordinary artisan would have been motivated to modify Parikh in the manner set forth above for at least the purpose of utilizing known processes to allow connection to structures or device below while protecting what’s below with insulation. Regarding claim 13, Parikh in view of Wada teaches the electronic device of claim 12, further comprising a space etched in the third dielectric layer above the dielectric material [Wada, fig. 1, the metal 25 present in the dielectric 24 is over the metal layers below, a space etched for said metal would be present to connect to the layers of Parikh, it would also be above the dielectric material which is in the channel with the metal via]. Regarding claim 14, while Parikh in view of Wada teaches the metal via and the dielectric material, they fail to teach the specific order of the layers being formed. However, this is a product by process limitation and the method or order by which layers are formed is not given patentable weight, only the final product of the layers being present. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), see MPEP 2113. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M PARKER whose telephone number is (571)272-8794. The examiner can normally be reached M-F 7:30am - 3:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOHN M PARKER/Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Jun 09, 2023
Application Filed
Feb 06, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
93%
With Interview (+0.9%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 831 resolved cases by this examiner. Grant probability derived from career allow rate.

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