DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Prior rejection of Claim 4 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, is withdrawn in view of applicant’s amendments to claim 4.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-2, 4-7, 9 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Fukuchi et al. (US 2018/0331005 A1, of record), and further in view of Arai et al. (US 2017/0207180 A1, newly cited) and Chen et al. (US 2009/0091036 A1, newly cited).
Re Claim 1, Fukuchi teaches a semiconductor device (Fig. 21), comprising:
a semiconductor die (CHP1, Fig. 21, para [0075]) comprising a front side (bottom side of CHP1, Fig. 21), a rear side (top side of CHP1, Fig. 21) opposing the front side, and side faces (side faces of CHP1, Fig. 21), a first transistor device (transistor Q1, compare Figs. 9-10 and 21, para [0075]) comprising a first source pad (S1 + PE1A + “PLG1A”, see annotated Fig. 21 below, paras [0076], [0080] and [0103]) and a first gate pad (G1 + PE1B + “PLG1B”, see annotated Fig. 21 below, paras [0076], [0080] and [0103]) on the front side, and a second transistor device (transistor Q2, compare Figs. 9-10 and 21, para [0075]) comprising a second source pad (S2 + PE2A + “PLG2A”, see annotated Fig. 21 below, paras [0076], [0080] and [0103]) and a second gate pad (G2 + PE2B + “PLG2B”, see annotated Fig. 21 below, paras [0076], [0080] and [0103]) on the front side (bottom side of CHP1, Fig. 21),
wherein the first and second transistor devices (transistors Q1 and Q2) each have a drain that is electrically coupled to a common drain pad (common drain BE, Fig. 21, para [0075]) on the rear side of the semiconductor die (top side of CHP1, Fig. 21),
wherein the drain pad (common drain BE, Fig. 21) has an upper surface and side faces (see Fig. 21),
wherein at least a central portion of the upper surface of the drain pad (upper surface of common drain BE, Fig. 21) is covered by a first electrically insulating layer (insulating layer R1, Fig. 21, para [0104]).
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Fukuchi does not disclose a first pad finishing layer that extends over the rear side of the semiconductor die and is arranged between the rear side of the semiconductor die and the first electrically insulating layer, wherein the first pad finishing layer extends over the drain pad such that the first pad finishing layer is arranged between the drain pad and the first electrically insulating layer, and wherein the first pad finishing layer comprises NiV alloy.
Related art, Arai teaches a similar semiconductor device (Fig. 9) where the two transistors 30 and 31 have a common drain electrode on the rear side (22, Fig. 9, para [0068]) and furthermore an UBM layer (38, Fig. 9, paras [0082] – [0083]) is disposed on the drain electrode (22, Fig. 9), where the UBM layer can be made of nickel/gold alloy (para [0082]). Arai discloses that the UBM layer 38 serves as a connection between the drain region of the first transistor 30 and the second transistor 31, spread resistance of the drain electrode 22 can be reduced and power loss during operation of the semiconductor device can also be decreased (para [0083]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to add the UBM layer on the rear side of the die in the device of Fukuchi, specifically, on the rear side of the drain electrode (common drain BE, Fig. 21), as taught by Arai, such that it is between the drain electrode (common drain BE, Fig. 21) and the first electrically insulating layer (insulating layer R1, Fig. 21). Arai discloses that the UBM layer serves as a connection between the drain region of the first transistor and the second transistor, spread resistance of the drain electrode can be reduced and power loss during operation of the semiconductor device can also be decreased (para [0083], Arai) This UBM layer can be treated as the pad finishing layer, and the claim limitation does not preclude this treatment.
Fukuchi modified by Arai does not explicitly teach the pad finishing layer can be made of Ni/V alloy. Fukuchi discloses that the drain electrode (common drain BE, Fig. 21, Fukuchi) can be made of copper (para [0083], Fukuchi), while Arai discloses that the pad finishing layer (UBM layer 38, Fig. 9, Arai) can be made of nickel/gold alloy (para [0082], Arai).
Additional related art, Chen teaches that an UBM layer can be made of an alloy selected from a group of materials consisting of nickel, gold, palladium, titanium or vanadium (para [0018], Chen). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the UBM layer of the device of Fukuchi modified by Arai, such that the UBM layer is made of nickel/vanadium alloy instead of nickel/gold alloy. Chen teaches that the nickel/vanadium alloy or nickel/gold alloy are art-recognized alternate materials for the formation of an UBM layer. The substitution of a known material for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Re Claim 2, Fukuchi modified by Arai and Chen teaches the semiconductor device of claim 1, wherein the upper surface and side faces of the drain pad (common drain BE, Fig. 21, Fukuchi) are entirely covered by the first electrically insulating layer (insulating layer R1, see Fig. 21), or the side faces of the drain pad are uncovered and the central portion of the upper surface of the drain pad is covered by the first electrically insulating layer.
Re Claim 4, Fukuchi modified by Arai and Chen teaches the semiconductor device of claim 1, wherein the first electrically insulating layer is formed of epoxy (insulating layer R1 is made of epoxy resin, para [0145], Fukuchi) and wherein the first and second source pads, the drain pad and the first and second gate pads comprise copper (source pads, drain pad and gate pads can be made of copper, paras [0084] and [0107], Fukuchi).
Re Claim 5, Fukuchi modified by Arai and Chen teaches the semiconductor device of claim 1, further comprising:
a second layer (layer 2S, Fig. 21, para [0149], Fukuchi),
wherein the front side of the semiconductor die (bottom side of CHP1, Fig. 21, Fukuchi) and at least side faces of the first (S1 + PE1A + “PLG1A”) and second source pads (S2 + PE2A + “PLG2A”) and of the first (G1 + PE1B + “PLG1B”) and second gate pads (G2 + PE2B + “PLG2B”) are covered with the second layer (layer 2S, see Fig. 21, Fukuchi),
wherein at least a central portion of the first and second source pads and of the first and second gate pads is exposed from the second layer (see Fig. 21, Fukuchi).
Fukuchi does not explicitly say that the second layer (layer 2S, Fig. 21) is electrically insulating. However, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the layer 2S in Fig. 21 has to be electrically insulating, otherwise all the source and drain contacts will be electrically shorted, and the device will be non-functional.
Re Claim 6, Fukuchi modified by Arai and Chen teaches the semiconductor device of claim 5, further comprising:
a second pad finishing layer (layer PAS, Fig. 21, para [0080], Fukuchi) arranged between the front side of the semiconductor die (bottom side of CHP1, Fig. 21, Fukuchi) and the second electrically insulating layer (layer 2S, Fig. 21), and between at least side faces of the first (S1 + PE1A + “PLG1A”) and second source pads (S2 + PE2A + “PLG2A”) and of the (G1 + PE1B + “PLG1B”) and second gate pads (G2 + PE2B + “PLG2B”) and the second electrically insulating layer (layer 2S, Fig. 21, Fukuchi),
wherein at least the central portion of the first and second source pads and of the first and second gate pads is exposed from the second pad finishing layer (layer PAS, see Fig. 21, Fukuchi) and from the second electrically insulating layer (layer 2S, see Fig. 21, Fukuchi).
Re Claim 7, Fukuchi modified by Arai and Chen teaches the semiconductor device of claim 6, wherein the second electrically insulating layer is formed of epoxy or polyimide and/or the second pad finishing layer comprises one or more of Ni, a NiV alloy, an oxide and a nitride (layer PAS can be an oxide or nitride, para [0084], Fukuchi).
Re Claim 9, Fukuchi modified by Arai and Chen teaches a battery management system, comprising:
a battery protection circuit (Fig. 4, paras [0057] – [0061], Fukuchi); and
a battery protection switch, wherein the battery protection switch comprises the semiconductor device of claim 1 (CHP1, Figs. 4 and 21, paras [0050] – [0061], Fukuchi).
Re Claim 14, Fukuchi teaches a semiconductor device (Fig. 21), comprising:
a semiconductor die (CHP1, Fig. 21, para [0075]) comprising a front side (bottom side of CHP1, Fig. 21), a rear side (top side of CHP1, Fig. 21) opposing the front side, and side faces (side faces of CHP1, Fig. 21), at least one pad on the front side (source pad S1, Fig. 21, para [0076]) and/or at least one pad on the rear side (common drain BE, Fig. 21, para [0075]),
wherein the at least one pad on the front side and/or the at least one pad on the rear side (common drain BE, Fig. 21) is at least partially covered by an electrically insulating layer (insulating layer R1, Fig. 21, para [0104]).
Fukuchi does not disclose a first pad finishing layer that at least partially covers the drain pad on the rear side, and wherein the electrically insulating layer is arranged on the pad finishing layer, and that the pad finishing layer comprises a NiV alloy.
Related art, Arai teaches a similar semiconductor device (Fig. 9) where the two transistors 30 and 31 have a common drain electrode on the rear side (22, Fig. 9, para [0068]) and furthermore an UBM layer (38, Fig. 9, paras [0082] – [0083]) is disposed on the drain electrode (22, Fig. 9), where the UBM layer can be made of nickel/gold alloy (para [0082]). Arai discloses that the UBM layer 38 serves as a connection between the drain region of the first transistor 30 and the second transistor 31, spread resistance of the drain electrode 22 can be reduced and power loss during operation of the semiconductor device can also be decreased (para [0083]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to add the UBM layer on the rear side of the drain electrode (common drain BE, Fig. 21) in the device of Fukuchi, as taught by Arai, such that it is between the drain electrode (common drain BE, Fig. 21) and the first electrically insulating layer (insulating layer R1, Fig. 21). Arai discloses that the UBM layer serves as a connection between the drain region of the first transistor and the second transistor, spread resistance of the drain electrode can be reduced and power loss during operation of the semiconductor device can also be decreased (para [0083], Arai) This UBM layer can be treated as the pad finishing layer, and the claim limitation does not preclude this treatment.
Fukuchi modified by Arai does not explicitly teach the pad finishing layer can be made of Ni/V alloy. Fukuchi discloses that the drain electrode (common drain BE, Fig. 21, Fukuchi) can be made of copper (para [0083], Fukuchi), while Arai discloses that the pad finishing layer (UBM layer 38, Fig. 9, Arai) can be made of nickel/gold alloy (para [0082], Arai).
Additional related art, Chen teaches that an UBM layer can be made of an alloy selected from a group of materials consisting of nickel, gold, palladium, titanium or vanadium (para [0018], Chen). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the UBM layer of the device of Fukuchi modified by Arai, such that the UBM layer is made of nickel/vanadium alloy instead of nickel/gold alloy. Chen teaches that the nickel/vanadium alloy or nickel/gold alloy are art-recognized alternate materials for the formation of an UBM layer. The substitution of a known material for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Re Claim 15, Fukuchi modified by Arai and Chen teaches the semiconductor device of claim 14, wherein the electrically insulating layer is formed of epoxy (insulating layer R1 is made of epoxy resin, para [0145], Fukuchi), and wherein the pads comprise copper (source pads, drain pad and gate pads can be made of copper, paras [0084] and [0107], Fukuchi).
Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over Fukuchi et al. (US 2018/0331005 A1, of record), Arai et al. (US 2017/0207180 A1, newly cited) and Chen et al. (US 2009/0091036 A1, newly cited), as applied to claim 1 above and further in view of Ho et al. (US 2022/0344228 A1, of record).
Re Claim 8, Fukuchi modified by Arai and Chen teaches the semiconductor device of claim 1, but does not disclose a product marking formed in an outer surface of the first electrically insulating layer.
In a related semiconductor art, Ho teaches that a product mark can be formed on the outer surface of the insulating protective layer by a laser processing process or a lithographic process (para [0047]), which will allow the manufacturer to track the device and facilitate quick identification if needed.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to form a product mark on the outer surface of the insulating protecting layer of the device of Fukuchi as taught by Ho, as that will allow the manufacturer to track the device and facilitate quick identification if needed.
Rejection 2
Claim Rejections - 35 USC § 102
Claim 14 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fu et al. (US 2013/0341785 A1, newly cited).
Re Claim 14, Fu teaches a semiconductor device (Fig. 2), comprising:
a semiconductor die (15, Figs. 1-2, para [0026]) comprising a front side (top side of 15, Figs. 1-2), a rear side opposing the front side (bottom side of 15, Figs. 1-2), and side faces (side walls of 15, Figs. 1-2), at least one pad (60/75, Fig. 2, para [0030]) on the front side (top side of 15, Fig. 2) and/or at least one pad on the rear side,
wherein the at least one pad (pads 60/75, Fig. 2, para [0030]) on the front side (top side of 15, Fig. 2) and/or the at least one pad on the rear side is at least partially covered (see Fig. 2) by a pad finishing layer (UBM layers 55/70, Fig. 2, para [0032]) and by an electrically insulating layer (130, Fig. 2, para [0032]) arranged on the pad finishing layer (55/70, Fig. 2),
wherein the pad finishing layer comprises a NiV alloy (UBM layer 55/70 can comprise of a nickel-vanadium alloy layer, para [0033]).
Claim Rejections - 35 USC § 103
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Fu et al. (US 2013/0341785 A1, newly cited), as applied to claim 14 above and further in view of Lin et al. (US 2007/0026631 A1, newly cited).
Re Claim 15, Fu teaches the semiconductor device of claim 14, wherein the pads comprise copper (pads 60/75 can comprise of copper, para [0030]).
Fu does not explicitly disclose that the electrically insulating layer is formed of epoxy. Fu discloses that the protective insulating layer 130 (Fig. 2) can be made of a variety of insulating materials like polyimide, benzocyclobutene or other insulating materials such as silicon nitride (para [0032]).
Related art Lin teaches a similar protective insulating layer (368, Fig. 14, para [0055]), where the protective insulating layer can be made of polyimide, benzo-cyclo-butene (BCB), parylene-based material or epoxy-based material (para [0055]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the protective insulating layer of the device of Fu, such that the protective insulating layer is made of epoxy instead of polyimide. Lin teaches that epoxy, polyimide or benzo-cyclo-butene (BCB) are art-recognized alternate materials for the formation of a protective insulating layer. The substitution of a known material for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Response to Arguments
Applicant’s arguments with respect to claims 1 and 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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