DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 6-7, 15-17, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. Pub. No. US 20230178553 A1 to Xie et al. (hereinafter “Xie”).
Regarding claim 1, Xie teaches a semiconductor structure (figs. 61A, B, and C) comprising:
a first stacked field effect transistor (FET) cell (first cell annotated below) comprising a second FET (second FET annotated below, separation occurring at the dielectric isolation layers 217) stacked over (vertically over) a first FET (first FET below);
a second stacked FET cell (as annotated below) located adjacent (laterally adjacent in fig. 61A) to the first stacked FET cell (first cell) and comprising a fourth FET (fourth FET annotated below, separation occurring at the dielectric isolation layers 217) stacked over (vertically over) a third FET (third FET below);
a first backside source/drain contact structure (256 left in fig. 61A) [0171] located beneath (vertically below) the first stacked FET cell (first cell) and contacting a source/drain region (238 of first FET; fig. 61A) [0182] of the first FET (first FET);
a second backside source/drain contact structure (256 right in fig. 61A) located beneath (vertically below) the second stacked FET cell (second cell) and contacting a source/drain region (238 of third FET; fig. 61A) [0182] of the third FET (third FET); and
an angled (angled because the sidewalls are not orthogonal to the contact 256) cut region (region of sidewalls of 254; fig. 61A) [0171] laterally separating (being disposed between) the first backside source/drain contact structure (left 256) from the second backside source/drain contact structure (right 256).
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Annotated fig. 61A from Xie
Regarding claim 2, Xie teaches the semiconductor structure of claim 1, wherein the angled cut region (sidewalls of 254) is filled with a backside interlayer dielectric material (material of ILD 254; fig. 61a) [0171]-[0174].
Regarding claim 4, Xie teaches the semiconductor structure of claim 1, wherein the first backside source/drain contact structure (256 left) comprises a first portion having a first critical dimension (width near vertical top of left 256), and a second portion having a second critical dimension (width near vertical bottom of left 256), wherein the first critical dimension is less than the second critical dimension (256 is narrower at the top than at the bottom in fig. 61A).
Regarding claim 6, Xie teaches the semiconductor structure of claim 1, wherein the second backside source/drain contact structure (right 256) comprises a first portion having a first critical dimension (width of a top portion of right 256), and a second portion having a second critical dimension (width of a bottom portion of right 256), wherein the first critical dimension is greater than the second critical dimension (the width of the top of right 256 is less than the bottom).
Regarding claim 7, Xie teaches the semiconductor structure of claim 6, wherein the second portion (bottom portion) of the second backside source/drain contact (right 256) is in contact (electrical contact) with the source/drain region (238) of the third FET (third FET).
Regarding claim 15, Xie teaches the semiconductor structure of claim 1, wherein the first FET (first FET), the second FET (second FET), the third FET (third FET) and the fourth FET (fourth FET) are each nanosheet FETs (comprising nanosheets) [0181].
Regarding claim 16, Xie teaches the semiconductor structure of claim 1, further comprising a bottom dielectric isolation layer (spacer dielectric material 234S; fig. 61A) [0181] located beneath the first FET (first FET) and the third FET (third FET), and a device isolation layer (217; fig. 61A) [0141] separating the second FET (second FET) from the first FET (first FET) and the fourth FET (fourth FET) from the third FET (third FET).
Regarding claim 17, Xie teaches the semiconductor structure of claim 1, wherein the first backside source/drain contact structure (left 256) has an angled sidewall (sidewall which is not orthogonal) facing an angled sidewall (non-orthogonal) of second backside source/drain contact structure (right 256).
Regarding claim 19, Xie teaches the semiconductor structure of claim 1, wherein the first FET (first FET) and the second FET (second FET) share a common gate structure (structure of gate electrode 251 in the first cell; fig. 61A) [0169], and the third FET (third FET) and the fourth FET (fourth FET) share a common gate structure (structure of gate electrode 251 in the second cell; fig. 61A) [0169].
Allowable Subject Matter
Claims 3, 5, 8-14, 18, and 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, it is not found a reference which reasonably reads on claim 3. The closest reference is Xie but reading on claim 3 would require the inclusion of element 232 in the interpretation of the backside interlayer dielectric material which would be untenable.
Regarding claim 5, it is not found a reference which reasonably reads on claim 5. In specific, it is not found a reference with an initial backside BEOL structure i.e., a separate backside BEOL structure.
Regarding claim 8, it is not found a reference which reasonably reads on claim 8. In specific, it is not found a reference with an additional frontside BEOL structure i.e., having two frontside BEOL structures. Claims 9-14 comprise allowable subject matter only because of their dependence on claim 8.
Regarding claim 18, it is not found a reference which reasonably reads on claim 18. In specific, it is not found a reference with a perpendicular sidewall opposite the angled sidewall.
Regarding claim 20, it is not found a reference which reasonably reads on claim 20. In specific, it is not found a reference with a bilayer sacrificial material structure meeting all the limitations of claim 20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN EDWARD CUTLER whose telephone number is (703)756-5415. The examiner can normally be reached Monday-Friday 7:30 am - 5:00 pm Eastern Time.
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/ETHAN EDWARD CUTLER/Examiner, Art Unit 2892
/NORMAN D RICHARDS/ Supervisory Patent Examiner, Art Unit 2892
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