Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by kang et al., US 2021/0066304.
Regarding claim 1, Kang discloses (figs. 1, 2A-2B and related text) a semiconductor device (100A/100B) comprising: a bit line structure (30) on a substrate (10), the bit line structure including a conductive structure (31/33/35) and an insulation structure (37) stacked in a vertical direction substantially perpendicular to an upper surface of the substrate (10); and a first spacer (41) and a second spacer (44) stacked in a horizontal direction on a sidewall of the bit line structure (30), wherein the horizontal direction is substantially parallel to the upper surface of the substrate (10), the conductive structure includes a nitrogen-containing conductive portion (33, TiN therefore includes nitrogen containing conductive portion) at a lateral portion thereof (side surface of 33), and the first spacer (31) contacts the nitrogen-containing conductive portion (33, side surface of 33).
Regarding claim 2, Kang discloses the conductive structure (30) includes a first conductive pattern (31), a barrier pattern (33), and a second conductive (35) pattern sequentially stacked in the vertical direction, and the first conductive pattern (31), the barrier pattern (33) and the second conductive pattern (35) include doped polysilicon [0023], a metal silicon nitride (TiN, [0023]) and a metal active(W, [0023]) respectively.
Regarding claim 5, Kang discloses the first spacer (41) includes an oxide ([0048]), and the second spacer (44) includes a nitride ([0049]).
Regarding claim 6, kang discloses an isolation pattern (15) on the substrate (10), the isolation pattern (15) exposing an active pattern (Source (S) and Drain (D) regions) of the substrate and covering a sidewall of the active pattern (fig. 2A); and a conductive filling pattern (fig. 5, 31) between the active pattern (fig. 5) and the bit line structure (30), the conductive filling pattern including a conductive material (31).
Regarding claim 7, Kang discloses the conductive filling pattern (fig. 5, 31) contacts an upper surface of a central portion of the active pattern (S region, fig. 5).
Regarding claim 8, kang discloses an insulating filling pattern (40) covering a sidewall of the conductive filling pattern (fig. 5).
Regarding claim 9, kang discloses a conductive pad structure (51, fig. 2B) on the active pattern (S, D regions) and the isolation pattern (15) , wherein the conductive pad structure overlaps at least a portion of the conductive filling pattern (31, contact the source region, fig. 2B) in the horizontal direction (fig. 2B).
Regarding claim 10, kang discloses a third spacer (61) contacting the sidewall of the bit line structure (30), an upper surface of the first spacer (41), and an upper surface of the second spacer (44), wherein the third spacer includes a nitride (62, can be TiN, [0028]).
Regarding claim 11, Kang discloses (figs. 1, 2A-2B and related text) a semiconductor device (110A, 100B) comprising: a bit line structure (30) on a substrate, the bit line structure having a first conductive pattern including a metal (33); a first spacer (41) contacting a sidewall of the bit line structure (30), the first spacer including an oxide ([0048]); and a second spacer (44) contacting an outer sidewall of the first spacer (41, note the claim does not require direct contact), the second spacer including a nitride ([0049]), wherein the first conductive pattern includes a first nitrogen-containing portion (sidewall of 33 has nitrogen containing since 33 is made of TiN) at a lateral portion contacting the first spacer, and the first nitrogen-containing portion includes nitrogen (33 is made of TiN).
Claim(s) 14-16 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al., US 20190206873.
Regarding claim 14, Kim discloses a semiconductor device (figs. 1-27 and related text) comprising: an active pattern (105) on a substrate(100); an isolation pattern (110) on the substrate, the isolation pattern (110) covering a sidewall of the active pattern(105); a gate structure (160) extending in a first direction, the first direction being substantially parallel to an upper surface of the substrate (100), and the gate structure being buried in an upper portion of the active pattern (105) and an upper portion of the isolation pattern (110); a bit line structure (305) on a central portion of the active pattern (105) and the isolation pattern (110), the bit line structure extending in a second direction (fig. 27), the second direction being substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction, and the bit line structure (305) including a conductive structure (265/275/285) and an insulation structure (295) stacked in a vertical direction, the vertical direction being substantially perpendicular to the upper surface of the substrate (100, fig. 27); a first spacer (340) and a second spacer (375) stacked in the first direction on a sidewall of the bit line structure (305); a contact plug (440) structure on each of opposite end portions of the active pattern; and a capacitor (560) on the contact plug structure (440), wherein the conductive structure has a nitrogen-containing conductive portion (270, [0028]) at a lateral portion thereof, the nitrogen-containing conductive portion includes nitrogen (270 can be TiN), and the first spacer (340) contacts the nitrogen-containing conductive portion (fig. 27, note the claim does not require direct contact).
Regarding claim 15, Kim discloses a conductive filling pattern (140) between the central portion of the active pattern (105) and the bit line structure (305).
Regarding claim 16, Kim discloses an insulating filling pattern (130) covering a sidewall of the conductive filling pattern (160).
Regarding claim 20, Kim discloses the first spacer (340) includes an oxide ([0037]), and the second spacer (375) includes a nitride ([0042]).
Allowable Subject Matter
Claims 3-4, 12-13 and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL A GEBREMARIAM whose telephone number is (571)272-1653. The examiner can normally be reached 8:30-4PM.
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/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811