DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to the claims rejected in the previous Office action have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 7, 8, and 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yu-Lien Huang et al. (US 10050149 B1; hereinafter Huang) in view of Changhwa Kim et al. (US 20180083002 A1; hereinafter Kim).
Regarding Claim 1, Huang discloses a semiconductor device (Fig. 2) comprising:
an active pattern (active portion of substrate 102; C3:L45-L60) extending in a first direction (left/right);
a gate structure (209; C7:L4-L25) including a gate electrode (122/124; C5:L47-L48), a gate spacer (110; C6:L22-L35), and a gate capping pattern (120; C6:L36-L61) on the active pattern, the gate electrode (122/124) extending in a second direction different from the first direction (as shown in view of Fig. 1);
a source/drain pattern (103/106/205/207; C7:L4-L25) on the active pattern; and
a source/drain etch stop film (226; C7:L4-L25) on an upper surface of the source/drain pattern (103/106/205/207) and extending along a sidewall of the gate spacer (side of 110) (as shown in Fig. 2),
wherein the gate capping pattern (120) is on an upper surface of the gate electrode (top of 122/124) and an upper surface of the gate spacer (top of 110) (as shown in Fig. 2),
a sidewall of the gate capping pattern (either sidewall of 120) is free of the source/drain etch stop film (226), the sidewall of the gate capping pattern being beyond the gate electrode (122/124) in the first direction (left/right) (as shown in Fig. 2),
Huang is silent regarding wherein:
the gate capping pattern including a lower gate capping pattern and an upper gate capping pattern on the lower gate capping pattern;
an upper surface of the lower gate capping pattern includes a first inclined surface and a second inclined surface connected to each other, and
a distance, in the first direction, between the first inclined surface and the second inclined surface increases as a distance from the upper surface of the gate electrode increases.
In the same field of endeavor, Kim teaches a similar semiconductor device (Fig. 2A) comprising: a gate pattern (GL; ¶0030) disposed on an active pattern (FA; ¶0029) and including gate spacers (162; ¶0034) and a complex gate capping pattern (180; ¶0035); wherein the gate capping pattern (180) includes a lower gate capping pattern (182) and an upper gate capping pattern (182D/184) on the lower gate capping pattern (182) (as shown in Fig. 2A);
an upper surface of the lower gate capping pattern (top curved surface of 182) includes a first inclined surface (left side of curved top surface) and a second inclined surface (right side of curved top surface) connected to each other (as shown in Fig. 2A wherein the inclined curved surfaces are connected), and
a distance, in the first direction (left/right), between the first inclined surface and the second inclined surface increases as a distance from the upper surface of the gate electrode (GL) increases (as shown in Fig. 2A, a distance between the left and right inclined curved surfaces increases in a direction z away from GL).
Huang discloses in (C6:L36-L61) that the gate capping pattern (120) may have a stack of multiple layers with different materials and dimensions from each other, and are within the scope of the disclosure. Kim teaches the complex gate capping pattern (180) including multiple layers/materials is suitable as a gate capping pattern. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the gate capping pattern of Kim for the gate capping pattern of Huang because of the art-recognized suitability for the intended purpose of being a gate capping pattern on a gate electrode (MPEP 2144.07), and/or in order to prevent short circuiting between conductive plugs (Kim; ¶0044, ¶0164).
This would result in the lower gate capping pattern (Kim; 182) on the upper surface of the gate electrode; a sidewall of the lower gate capping pattern (Kim; 182) free of the source/drain etch stop film (since the entire gate capping pattern 120 of Huang is free of the source/drain etch stop film); and the sidewall of the lower gate capping pattern (Kim; 182) being beyond the gate electrode in the first direction (since the entire gate capping pattern 120 of Huang has sidewalls beyond the gate electrode in the first direction).
Regarding Claim 5, modified Huang teaches the semiconductor device of claim 1, further comprising a source/drain contact (228; C7:L4-L25) that is on and connected to the source/drain pattern (103/106/205/207) (as shown in Haung Fig. 2), wherein the source/drain contact (228) is in contact with the source/drain etch stop film (226), the lower gate capping pattern and the upper gate capping pattern (as modified by Kim, Huang’s S/D contact 228 would be contacting the upper and lower gate capping patterns as there are no intermediate layers or liners between the S/D contact 228 and the gate capping pattern).
Regarding Claim 7, modified Huang teaches the semiconductor device of claim 1, wherein a width of the upper gate capping pattern (Kim; 182D/184 as modified being substituted into 120 of Huang) in the first direction (left/right) is equal to or smaller than a width of the lower gate capping pattern (182 as modified being substituted into 120 of Huang) in the first direction (as shown in Kim Fig. 2A and Huang Fig. 2).
Regarding Claim 8, modified Huang teaches the semiconductor device of claim 1, wherein the upper gate capping pattern (Kim; 182D/184) includes an upper surface of the gate capping pattern (180) (as shown in Kim Fig. 2A).
Regarding Claim 10, Huang discloses a semiconductor device (Fig. 2) comprising:
an active pattern (active portion of substrate 102; C3:L45-L60) extended in a first direction (left/right);
a gate structure (209; C7:L4-L25) including a gate electrode (122/124; C5:L47-L48), a gate spacer (110; C6:L22-L35), and a gate capping pattern (120; C6:L36-L61) on the active pattern, the gate electrode (122/124) extending in a second direction different from the first direction (as shown in view of Fig. 1);
a source/drain pattern (103/106/205/207; C7:L4-L25) on the active pattern; and
a source/drain etch stop film (226; C7:L4-L25) on an upper surface of the source/drain pattern (103/106/205/207) and extending along a sidewall of the gate spacer (side of 110) (as shown in Fig. 2),
wherein the gate capping pattern (120) is in contact with an upper surface of the gate electrode (top of 122/124) and an upper surface of the gate spacer (top of 110) (as shown in Fig. 2).
Huang is silent regarding wherein:
the gate capping pattern including a lower gate capping pattern and an upper gate capping pattern on the lower gate capping pattern;
an upper surface of the lower gate capping pattern includes a first inclined surface and a second inclined surface directly connected to each other, and
the first inclined surface of the upper surface of the lower gate capping pattern and the second inclined surface of the upper surface of the lower gate capping pattern are in contact with the upper gate capping pattern.
In the same field of endeavor, Kim teaches a similar semiconductor device (Fig. 2A) comprising: a gate pattern (GL; ¶0030) disposed on an active pattern (FA; ¶0029) and including gate spacers (162; ¶0034) and a complex gate capping pattern (180; ¶0035); wherein the gate capping pattern (180) includes a lower gate capping pattern (182) and an upper gate capping pattern (182D/184) on the lower gate capping pattern (182) (as shown in Fig. 2A);
an upper surface of the lower gate capping pattern (top curved surface of 182) includes a first inclined surface (left side of curved top surface) and a second inclined surface (right side of curved top surface) directly connected to each other (as shown in Fig. 2A wherein the inclined curved surfaces are directly connected to each other), and
a distance, in the first direction (left/right), between the first inclined surface and the second inclined surface diverge in a direction away from the gate electrode (GL) (as shown in Fig. 2A, a distance between the left and right inclined curved surfaces diverge in a direction z away from GL),
the first inclined surface of the upper surface of the lower gate capping pattern and the second inclined surface of the upper surface of the lower gate capping pattern are in contact with the upper gate capping pattern (182D/184) (as shown in Fig. 2A).
Huang discloses in (C6:L36-L61) that the gate capping pattern (120) may have a stack of multiple layers with different materials and dimensions from each other, and are within the scope of the disclosure. Kim teaches the complex gate capping pattern (180) including multiple layers/materials is suitable as a gate capping pattern. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the gate capping pattern of Kim for the gate capping pattern of Huang because of the art-recognized suitability for the intended purpose of being a gate capping pattern on a gate electrode (MPEP 2144.07), and/or in order to prevent short circuiting between conductive plugs (Kim; ¶0044, ¶0164).
This would result in the lower gate capping pattern (Kim; 182) in contact with the upper surface of the gate electrode; a sidewall of the lower gate capping pattern (Kim; 182) free of the source/drain etch stop film (since the entire gate capping pattern 120 of Huang is free of the source/drain etch stop film); and the sidewall of the lower gate capping pattern (Kim; 182) being beyond the gate electrode in the first direction (since the entire gate capping pattern 120 of Huang has sidewalls beyond the gate electrode in the first direction).
Regarding Claim 11, modified Huang teaches the semiconductor device of claim 10, wherein the first inclined surface and the second inclined surface diverge in a direction away from the upper surface of the gate electrode (as modified by and shown in Fig. 2A of Kim).
Regarding Claim 12, modified Huang teaches the semiconductor device of claim 10, wherein an upper surface of the gate capping pattern (Huang; top of 120 which is modified to include the complex gate capping pattern of Kim) is free of the source/drain etch stop film (Huang; 226; Fig. 2).
Regarding Claim 13, modified Huang teaches the semiconductor device of claim 10, wherein a width of the upper gate capping pattern (Kim; 182D/184 as modified being substituted into 120 of Huang) in the first direction (left/right) is equal to a width of the lower gate capping pattern (Kim; 182 as modified being substituted into 120 of Huang) in the first direction (Kim; Fig. 2A and Huang Fig. 2).
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yu-Lien Huang et al. (US 10050149 B1; hereinafter Huang) in view of Changhwa Kim et al. (US 20180083002 A1; hereinafter Kim) and Keun Hee Bai et al. (US 20190295889 A1; hereinafter Bai).
Regarding Claim 4, modified Huang teaches the semiconductor device of claim 1, but is silent regarding wherein the upper gate capping pattern (as modified by Kim; 182D/184) further includes a cavity or a seam.
In the same field of endeavor, Bai teaches a similar semiconductor device including a cavity (Bai; Fig 10; V; ¶0107) that may be formed in arbitrary locations in the gate capping pattern (140; ¶0107).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the cavity of Bai in the lower and/or upper gate capping patterns of modified Huang in order to reduce parasitic capacitance between the gate electrode and adjacent contact (Bai; ¶0107).
Regarding Claim 14, modified Huang teaches the semiconductor device of claim 10, but is silent regarding wherein the upper gate capping pattern (Kim; 182D/184) further includes a cavity or a seam.
In the same field of endeavor, Bai teaches a similar semiconductor device including a cavity (Bai; Fig 10; V; ¶0107) that may be formed in arbitrary locations in the gate capping pattern (140; ¶0107).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the cavity of Bai in the lower and/or upper gate capping patterns of modified Huang in order to reduce parasitic capacitance between the gate electrode and adjacent contact (Bai; ¶0107).
Claims 16, 17, and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Yu-Lien Huang et al. (US 10050149 B1; hereinafter Huang) in view of Changhwa Kim et al. (US 20180083002 A1; hereinafter Kim), Keun Hee Bai et al. (US 20190295889 A1; hereinafter Bai), and Chung-Liang Cheng et al. (US 20220254927 A1; hereinafter Cheng).
Regarding Claim 16, Huang discloses a semiconductor device comprising:
an active pattern (active portion of substrate 102; C3:L45-L60) extending in a first direction (left/right); a second direction (up/down);
a gate structure (209; C7:L4-L25) including a gate electrode (122/124; C5:L47-L48), a gate spacer (110; C6:L22-L35), and a gate capping pattern (120; C6:L36-L61) on the active pattern, the gate electrode (122/124) extending in a third direction (in/out as shown in view of Fig. 1),
a source/drain pattern (103/106/205/207; C7:L4-L25) on the active pattern;
a source/drain contact (228/229; C7:L4-L25) that is on and connected to the source/drain pattern (103/106/205/207); and
a source/drain etch stop film (226; C7:L4-L25) on an upper surface of the source/drain pattern (103/106/205/207) and extending along a sidewall of the gate spacer (side of 110), the sidewall of the gate spacer facing the source/drain contact (228/229) (as shown in Fig. 2),
wherein the gate capping pattern (120) is in contact with an upper surface of the gate electrode (top of 122/124) and an upper surface of the gate spacer (top of 110) (as shown in Fig. 2).
Huang is silent regarding wherein:
the gate capping pattern including a lower gate capping pattern and an upper gate capping pattern on the lower gate capping pattern;
the lower gate capping pattern has a first portion closest to the source/drain contact in the first direction and the upper gate capping pattern has a second portion aligned with the first portion of the lower gate capping pattern in the second direction, and
the upper gate capping pattern defines an upper surface of the gate capping pattern.
In the same field of endeavor, Kim teaches a similar semiconductor device (Fig. 2A) comprising: a gate pattern (GL; ¶0030) disposed on an active pattern (FA; ¶0029) and including gate spacers (162; ¶0034) and a gate capping pattern (180; ¶0035); wherein the gate capping pattern (180) includes a lower gate capping pattern (182) and an upper gate capping pattern (182D/184) on the lower gate capping pattern (182) (as shown in Fig. 2A), and a source/drain contact (CP1; ¶0042);
an upper surface of the lower gate capping pattern (top curved surface of 182) includes a first inclined surface (left side of curved top surface) and a second inclined surface (right side of curved top surface) connected to each other (as shown in Fig. 2A wherein the inclined curved surfaces are connected), and
a distance, in the first direction (left/right), between the first inclined surface and the second inclined surface increases as a distance from the upper surface of the gate electrode (GL) increases (as shown in Fig. 2A, a distance between the left and right inclined curved surfaces increases in a direction z away from GL),
the lower gate capping pattern (182) has a first portion closest to the source/drain contact (CP1) in the first direction (left/right) and the upper gate capping pattern (182D/184) has a second portion aligned with the first portion of the lower gate capping pattern in a second direction (up/down) (as shown in Fig. 2A; wherein the sidewalls of the upper and lower gate capping patterns are portions that are aligned up/down),
the upper gate capping pattern (182D/184) defines an upper surface of the gate capping pattern (top of 180 as shown in Fig. 2A).
Huang discloses in (C6:L36-L61) that the gate capping pattern (120) may have a stack of multiple layers with different materials and dimensions from each other, and are within the scope of the disclosure. Kim teaches the complex gate capping pattern (180) including multiple layers/materials is suitable as a gate capping pattern. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the gate capping pattern of Kim for the gate capping pattern of Huang because of the art-recognized suitability for the intended purpose of being a gate capping pattern on a gate electrode (MPEP 2144.07), and/or in order to prevent short circuiting between conductive plugs (Kim; ¶0044, ¶0164).
This would result in the lower gate capping pattern (Kim; 182) in contact with the upper surface of the gate electrode; a sidewall of the lower gate capping pattern (Kim; 182) free of the source/drain etch stop film (since the entire gate capping pattern 120 of Huang is free of the source/drain etch stop film); and the sidewall of the lower gate capping pattern (Kim; 182) being beyond the gate electrode in the first direction (since the entire gate capping pattern 120 of Huang has sidewalls beyond the gate electrode in the first direction).
Modified Huang is silent regarding wherein the active pattern includes a bottom pattern extending in the first direction (left/right) and a plurality of sheet patterns spaced apart from the bottom pattern in the second direction (up/down).
In the same field of endeavor, Cheng teaches a similar semiconductor device (Fig. 1D and Fig. 1G) wherein a gate all around (GAA) transistor (Fig. 1G) includes a bottom pattern (106; ¶0021) and plurality of sheet patterns (121, ¶0047) spaced apart from the bottom pattern in an up/down direction, which is an alternative to the fin-type transistor of Fig. 1D (Cheng; ¶0047) (and that of Huang).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the GAA active pattern of Cheng for the fin-type active pattern of Huang in order to achieve improved gate control of the GAA design, while also being applicable alternatives (Cheng; ¶0047)
Modified Huang is silent regarding the upper gate capping pattern includes a first cavity or a first seam.
In the same field of endeavor, Bai teaches a similar semiconductor device including a cavity (Bai; Fig 10; V; ¶0107) that may be formed in arbitrary locations in the gate capping pattern (140; ¶0107).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the cavity of Bai in the lower and/or upper gate capping patterns of modified Huang in order to reduce parasitic capacitance between the gate electrode and adjacent contact (Bai; ¶0107).
Regarding Claim 17, modified Huang teaches the semiconductor device of claim 16, wherein the upper surface of the gate capping pattern (Huang 120 modified to include the complex gate capping pattern of Kim) is free of the source/drain etch stop film (Huang; 226; as shown in Fig. 2).
Regarding Claim 19, modified Huang teaches the semiconductor device of claim 16, wherein an upper surface of the lower gate capping pattern includes a first inclined surface (Kim; left side of curved top surface of 182) and a second inclined surface (Kim; right side of curved top surface of 182) connected to each other (as shown in Kim Fig. 2A wherein the inclined curved surfaces are connected), and the first inclined surface of the upper surface of the lower gate capping pattern and the second inclined surface of the upper surface of the lower gate capping pattern are in contact with the upper gate capping pattern (182D/184 as shown in Kim Fig. 2A).
Regarding Claim 20, modified Huang teaches the semiconductor device of claim 19, wherein the first inclined surface and the second inclined surface diverge in a direction away from the upper surface of the gate electrode (as modified by and as shown in Kim Fig. 2A).
Regarding Claim 21, modified Huang teaches the semiconductor device of claim 16, wherein the first portion of the lower gate capping pattern (edge of 182 close to the S/D contact as modified into 120 of Huang) and the second portion of the upper gate capping pattern (edge of 182D/184 close to the S/D contact as modified into 120 of Huang) are disposed, in the first direction (left/right), between the source/drain contact (Huang; 228) and the sidewall of the gate spacer (Huang; 110) (as shown/modified in Huang Fig. 2; wherein the first and second portions of the gate capping pattern are at the edge of Huang’s 120 closest to the source/drain contact 228, and the portions are disposed at a location between the S/D contact and the gate spacer 110 due to the space created by the etch stop film 226 lining sidewalls of the S/D contact; commensurate in scope with the instant application Fig. 9).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN PRIDEMORE whose telephone number is (703)756-4640. The examiner can normally be reached Monday - Friday 8:00am - 4:00pm EST.
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898