DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action (Third Non-Final Action) is in response to Amendment filed on April 28, 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 5 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by More (US 2023/0326989, Provisional Application filed on Apr. 7, 2022).
Regarding claim 1, More discloses for a semiconductor structure comprising that
first source drain regions (first epitaxial-grown doped layer 252a of S/D feature 252, Fig. 14A) and second source drain regions (second epitaxial-grown doped layer 252b, Fig. 14A) arranged above a backside dielectric layer (above shallow trench isolation (STI) feature 220, Fig. 14A), because Applicants do not specifically claim what structural or geometrical relationships between the first and second source drain regions have, and/or what it looks like, the Source/Drain feature 252 by More comprises the first, second and third epitaxial-grown doped layers 252a, 252b and 252c (Fig. 14A, 14D), and the first and second epitaxial-grown doped layers 252a and 252b can correspond to the claimed first and second source drain regions, respectively. Also, because Applicants do not specifically claim what the backside dielectric layer is made of and/or what dimensions the backside dielectric layer have, the shallow trench isolation (STI) features 220 by More is formed by filling the trenches 214 (Fig. 4B) with a dielectric layer ([0024]), and since the STI feature 220 by More is positioned below the S/D feature 252 (Fig. 14A, 14D), therefore, the STI feature can correspond to the claimed backside dielectric layer; and
a buffer layer (buffer semiconductor region 254, Fig. 14A, 14D) physically separating at least one of the second source drain regions (252b, Fig. 14A, 14D) from the backside dielectric layer (220, Fig. 14A, 14D), because the second epitaxial-grown doped layer 252b, which corresponds to the second source drain region in the claimed invention, does not contact the STI feature 220 (Fig. 14A, 14D), and therefore, it is physically separated from the STI feature 220 by the buffer semiconductor region 254,
wherein at least one of the first source drain regions (252a, Fig. 14A, 14D) is in direct contact with the backside dielectric layer (220, Fig. 14A, 14D), because More further discloses that “the first epitaxial-grown doped layer 252a makes contact with the buffer semiconductor region 254” ([0048], Fig. 14A, 14D),
wherein the buffer layer (254, Fig. 14A, 14D) and the first source drain regions (252a, Fig. 14A, 14D) comprises silicon germanium, because “the S/D feature 252 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material” (emphasis added, [0048]) and “the buffer semiconductor region 254 includes a different semiconductor material than the substrate 202, such as silicon germanium (SiGe)” (emphasis added, [0040]).
Regarding claim 2, More further discloses for the semiconductor structure according to claim 1 that the first source drain regions (252a, Fig. 14A, 14D) are made from silicon germanium based epitaxy, and the second source drain regions (252b, Fig. 14A, 14D) are made from silicon based epitaxy, because “S/D feature 252 are formed in the S/D recesses 246. By way of example, epitaxial growth of the S/D feature 252 may be performed by vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and/or other suitable processes” ([0047]).
Regarding claim 5, More further discloses for the semiconductor structure according to claim 1 that a width of the buffer layer (width of 254, Fig. 14D) is substantially equal to a width of at least one of the second source drain regions (252b, Fig. 14D).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-9, 12, 14-15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over by More (US 2023/0326989, Provisional Application filed on Apr. 7, 2022).
Regarding claim 8, More further discloses for a semiconductor structure comprising that
first source drain regions (252a, Fig. 14A, 14D) and second source drain regions (252b, Fig. 14A, 14D) arranged above a backside dielectric layer (above 220, Fig. 14A, 14D);
a buffer layer (254, Fig. 14A, 14D) physically separating at least one of the second source drain regions (252b, Fig. 14A, 14D) from the backside dielectric layer (220, Fig. 14A, 14D),
wherein at least one of the first source drain regions (252a, Fig. 14A, 14D) is in direct contact with the backside dielectric layer (220, Fig. 14A, 14D),
wherein the buffer layer (254, Fig. 14A, 14D) and the first source drain regions (252a, Fig. 14A, 14D) comprise silicon germanium, because “the S/D feature 252 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material” (emphasis added, [0048]) and “the buffer semiconductor region 254 includes a different semiconductor material than the substrate 202, such as silicon germanium (SiGe)” (emphasis added, [0040]).
More does not explicitly disclose that a bottom dielectric isolation layer physically separating nanosheet stacks from the backside dielectric layer.
However, More further disclose that the mesa 203 is formed between the epitaxial layers 206/208 and the STI feature 220, which correspond to the claimed nanosheet stacks and backside dielectric layer, respectively, and therefore, the mesa 203 is physically separating the epitaxial layers 206/208 from the STI feature 220 (Fig. 14C-D). More further discloses that “the substantially undoped mesa 203 remains as a high resistance path in suppressing substrate leakage” ([0042]), and one of ordinary skill in the art would have recognized that the mesa 203 by More can provide electrical isolation functionality between the stack of epitaxial layers 206/208 and the STI feature 220. Examiner notes that Applicants do not specifically claim what a bottom dielectric isolation layer is made of, where it is positioned, and/or what it looks like.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an electrical isolation structure between a nanosheet stack and dielectric layers, as disclosed by More, in order to improve the overall device performance.
Regarding claim 9, More further discloses for the semiconductor structure according to claim 8 that the first source drain regions (252a, Fig. 14A, 14D) are made from silicon germanium based epitaxy; and the second source drain regions (252b, Fig. 14A, 14D) are made from silicon based epitaxy, because “S/D feature 252 are formed in the S/D recesses 246. By way of example, epitaxial growth of the S/D feature 252 may be performed by vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and/or other suitable processes” ([0047]).
Regarding claim 12, More further discloses for the semiconductor structure according to claim 8 that a width of the buffer layer (width of 254, Fig. 14D) is substantially equal to a width of at least one of the second source drain regions (252b, Fig. 14D).
Regarding claim 14, More further discloses for a semiconductor structure comprising that first source drain regions (252a, Fig. 14A, 14D) between a first set of adjacent nanosheet channels (stack of epitaxial layers 208, Fig. 14A, 14D);
second source drain regions (252b, Fig. 14A, 14D) between a (second) set of adjacent nanosheet channels (stack of epitaxial layers 208, Fig. 14A, 14D);
a backside dielectric layer (220, Fig. 14A, 14D) arranged below all of the first source drain regions (below all of 252a, Fig. 14A, 14D) and the second source drain regions (below all of 252a, Fig. 14A, 14D); and
a buffer layer (254, Fig. 14A, 14D) physically separating at least one of the second source drain regions (252b, Fig. 14A, 14D) from the backside dielectric layer (220, Fig. 14A, 14D),
wherein at least one of the first source drain regions (252a, Fig. 14A, 14D) is in direct contact with the backside dielectric layer (220, Fig. 14A, 14D),
wherein the buffer layer (254, Fig. 14A, 14D) and the first source drain regions (252a, Fig. 14A, 14D) comprises silicon germanium, because “the S/D feature 252 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material” (emphasis added, [0048]) and “the buffer semiconductor region 254 includes a different semiconductor material than the substrate 202, such as silicon germanium (SiGe)” (emphasis added, [0040]).
More does not explicitly disclose that second source drain regions between a second set of adjacent nanosheet channels.
However, More teaches a semiconductor integrated circuit (IC) structure including multiple nanosheet channel structures and corresponding source/drain regions arranged in a highly integrated manner, therefore, one of ordinary skill in the art would understand that such semiconductor IC structures commonly include repeated nanosheet and source/drain arrangements across an array. Therefore, one would recognize that another source/drain region, different from the specifically identified source/drain region in More, may serve as the claimed second source drain regions and be positioned between another set of adjacent nanosheet channels, as claimed.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a plurality of source/drain regions and corresponding nanosheet channels arranged in the claimed manner, as such configurations were well understood and conventional in the semiconductor art.
Regarding claim 15, More further discloses for the semiconductor structure according to claim 14 that the first source drain regions (252a, Fig. 14A, 14D) are made from silicon germanium based epitaxy, and the second source drain regions (252b, Fig. 14A, 14D) are made from silicon based epitaxy, because “S/D feature 252 are formed in the S/D recesses 246. By way of example, epitaxial growth of the S/D feature 252 may be performed by vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and/or other suitable processes” ([0047]).
Regarding claim 18, More further discloses for the semiconductor structure according to claim 14 that a width of the buffer layer (width of 254, Fig. 14D) is substantially equal to a width of at least one of the second source drain regions (252b, Fig. 14D).
Allowable Subject Matter
Claims 4, 6-7, 11, 13, 17, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, because the prior art cited in this Office Action does not teach the claimed limitations, “the backside dielectric layer is made from a different dielectric material than shallow trench isolation regions” recited in claims 4, 11 and 17, “a first contact embedded in the backside dielectric layer”, “a second contact embedded in the backside dielectric layer” recited in claims 6-7, 13 and 19-20.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 8 and 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WOO K LEE whose telephone number is (571)270-5816. The examiner can normally be reached Monday - Friday, 8:30 am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAY C KIM/Primary Examiner, Art Unit 2815
/WOO K LEE/Examiner, Art Unit 2815
Prosecution Insights