DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action (Second Non-Final Rejection) is in response to Amendment filed on December 12, 2025.
Claim Objections
Claims 2, 9 and 15 are objected to because of the following informalities:
In claims 2, 9 and 15, “geranium” should be amended with “germanium”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-5, 8-9, 11-12, 14-15, and 17-18 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Huang et al. (US 2022/0352326, hereinafter Huang).
Regarding claim 1, Huang discloses for a semiconductor structure comprising that
first source drain regions (drain feature 232D, Fig. 38) and second source drain regions (source feature 232S, Fig. 38) arranged above a backside dielectric layer (backside dielectric layer 260, Fig. 38); and
a buffer layer (silicide layer 266, Fig. 38, labeled in Fig. 25) physically separating at least one of the second source drain regions (at least one of 232S, Fig. 38) from the backside dielectric layer (260, Fig. 38), because Applicants do not specifically claim what a buffer layer is made of and/or what material’s composition a buffer layer has, the silicide layer 266 is disposed directly on the source features 232S and it physically separates the source feature 232S from the backside dielectric layer 260 (Fig. 25, 38), therefore, the silicide layer 266 can correspond to the buffer layer in the claimed invention,
wherein at least one of the first source drain regions (232D, Fig. 38) is in direct contact with the backside dielectric layer (260, Fig. 38).
Regarding claim 2, Huang further discloses for the semiconductor structure according to claim 1 that the first source drain regions (232D, Fig. 38) are made from silicon geranium based epitaxy, because “exemplary p-type source/drain features may include germanium, gallium-doped silicon germanium, boron-doped silicon germanium, or other suitable material and may be in-situ doped during the epitaxial process by introducing a p-type dopant, such as boron or gallium, or ex-situ doped using a junction implant process” (emphasis added, [0028]); and
the second source drain regions (232S, Fig. 38) are made from silicon based epitaxy, because “exemplary n-type source/drain features may include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable material and may be in-situ doped during the epitaxial process by introducing an n-type dopant, such as phosphorus, arsenic, or antimony, or ex-situ doped using a junction implant process” (emphasis added, [0028]).
Regarding claim 4, Huang further discloses for the semiconductor structure according to claim 1 that the backside dielectric layer (260, Fig. 38) is made from a different dielectric material than shallow trench isolation regions (isolation structure 204 or shallow isolation structure (STI) feature 204, Fig. 2, [0022]), because Huang discloses that “the dielectric layer 260 may have a composition similar to that of the bottom ILD layer 236” ([0041]) and “the bottom ILD layer 236 may include materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials” ([0029]). Huang further discloses that “the isolation structure 204 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and/or other suitable materials” ([0022]), therefore, the backside dielectric 260 and the isolation structure 204 by Huang can be selected from different dielectric materials, as an example, tetraethylorthosilicate (TEOS) oxide for the backside dielectric 260 and silicon oxynitride for the isolation structure 204 can be selected.
Regarding claim 5, Huang further discloses for the semiconductor structure according to claim 1 that a width of the buffer layer (266, Fig. 38 and labeled in Fig. 25) is substantially equal to a width of at least one of the second source drain regions (232S, Fig. 38), because as shown in Fig. 38 of Huang, a width of the source feature 232S is substantially equal to a width the silicide layer 266 in a cross-section.
Regarding claim 8, Huang further discloses for a semiconductor structure comprising that
first source drain regions (drain feature 232D, Fig. 38) and second source drain regions (source feature 232S, Fig. 38) arranged above a backside dielectric layer (backside dielectric layer 260, Fig. 38);
a buffer layer (silicide layer 266, Fig. 38, labeled in Fig. 25) physically separating at least one of the second source drain regions (232S, Fig. 38) from the backside dielectric layer (260, Fig. 38),
wherein at least one of the first source drain regions (232D, Fig. 38) is in direct contact with the backside dielectric layer (260, Fig. 38); and
a bottom dielectric isolation layer (bottom gate dielectric layer 212’, Fig. 38) physically separating nanosheet stacks (channel layers 208, Fig. 38) from the backside dielectric layer (260, Fig. 38), because Applicants do not specifically claim what a bottom dielectric isolation layer is made of, where it is positioned, and/or what it looks like, the bottom gate dielectric layer 212’ by Huang physically separates a stack of channel layers 208 from the backside dielectric 160 (Fig. 38).
Regarding claim 9, Huang further discloses for the semiconductor structure according to claim 8 that the first source drain regions are made from silicon geranium based epitaxy; and the second source drain regions are made from silicon based epitaxy, as the same reasons discussed in claim 2 above.
Regarding claim 11, Huang further discloses for the semiconductor structure according to claim 8 that the backside dielectric layer is made from a different dielectric material than shallow trench isolation regions, as the same reasons discussed in claim 4 above.
Regarding claim 12, Huang further discloses for the semiconductor structure according to claim 8 that a width of the buffer layer is substantially equal to a width of at least one of the second source drain regions, as the same reasons discussed in claim 5 above.
Regarding claim 14, Huang further discloses for a semiconductor structure comprising that first source drain regions (drain feature 232D, Fig. 38) between a first set of adjacent nanosheet channels (adjacent stack of channel layers 208 in the first device region 400A, Fig. 38);
second source drain regions (source feature 232S, Fig. 38) between a second set of adjacent nanosheet channels (adjacent stack of channel layers 208 in the second device region 400B, Fig. 38);
a backside dielectric layer (backside dielectric 260, Fig. 38) arranged below all of the first source drain regions (below all of 232D, Fig. 38) and the second source drain regions (below all of 232S, Fig. 38); and
a buffer layer (silicide layer 266, Fig. 38, labeled in Fig. 25) physically separating at least one of the second source drain regions (232S, Fig. 38) from the backside dielectric layer (260, Fig. 38),
wherein at least one of the first source drain regions (232D, Fig. 38) is in direct contact with the backside dielectric layer (260, Fig. 38).
Regarding claim 15, Huang further discloses for the semiconductor structure according to claim 14 that the first source drain regions are made from silicon geranium based epitaxy; and the second source drain regions are made from silicon based epitaxy, as the same reasons discussed in claim 2 above.
Regarding claim 17, Huang further discloses for the semiconductor structure according to claim 14 that the backside dielectric layer is made from a different dielectric material than shallow trench isolation regions, as the same reasons discussed in claim 4 above.
Regarding claim 18, Huang further discloses for the semiconductor structure according to claim 14 that a width of the buffer layer is substantially equal to a width of at least one of the second source drain regions, as the same reasons discussed in claim 5 above.
Allowable Subject Matter
Claims 3, 6-7, 10, 13, 16 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 8 and 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/WOO K LEE/Examiner, Art Unit 2815