DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 16 and 17 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 20220285388 (Cui et al).
As to claim 16, Cui discloses a method of manufacturing a semiconductor memory device (Figs. 3-10B), the method comprising:
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alternately stacking a first layer (42) and a second layer (32) in a first direction to form a stack (Fig. 3); partly removing the stack along the first direction to form an opening (49) through the stack in the first direction (Fig. 4A), a first surface provided on the first layer and facing on the opening, and a second surface provided on the second layer and facing on the opening (Fig. 5C); forming a protective film (41) onto the first surface ([0076] and Fig. 5D); forming an insulation (33) extending in a second direction intersecting with the first direction from the second surface toward the opening (Fig. 5E), the insulation being not formed on the protection film ([0077], note that the deposition of the insulation is an area-selective deposition in which the insulation is deposited/grown on the insulating surfaces and the growth is suppressed (and therefore unwanted) on the surface 41); removing the protective film (Fig. 9B); forming a memory layer (52+54+56) onto the first surface and the insulation (Fig. 5G); forming a semiconductor layer (60C) onto an opposite side of the memory layer from the first surface and onto an opposite side of the memory layer from the insulation in the second direction ([0091] and Fig. 5H); and removing the first layer to form a space and forming a third layer (46) in the space (Figs. 8B-10B).
Concerning claim 17, Cui discloses wherein the insulation and the memory layer define an interface therebetween in a cross-section along the first direction, the cross-section including the stack (Fig. 10B), the semiconductor layer, the memory layer and the insulation, the interface having a first point (P1 in the annotated Fig. 10B above) and a second point (P2 in the annotated Fig. 10B above), the first point overlapping with a middle portion in the first direction of the insulating layer, the second point overlapping with an end portion in the first direction of the insulating layer (annotated Fig. 10B above), wherein the second point is closer to the insulating layer in the second direction than the first point is (note that the insulation has a curved profile and that the first point the farthest point of the insulation from the insulating layer and then the distance decreases as you move toward the second point) , and wherein the interface curves from the first point to the second point to protrude toward the semiconductor layer (annotated Fig. 10B above shows the curved profile of the insulation).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5, 6, 10-15, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220285388 (Cui et al) in view of US 20170271527 (Higuchi et al).
Concerning claim 1, Cui discloses a semiconductor memory device comprising (Fig. 10B):
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a stack having an insulating layer (32) and a conductive layer (46B), the insulating layer and the conductive layer being stacked alternately in a first direction (annotated Fig. 10B above); a semiconductor layer (60C) provided through the insulating layer and the conductive layer ([0091] and Fig. 10B); a memory layer (52+54+56) provided between the stack and the semiconductor layer in a second direction intersecting with the first direction (Fig. 10B); and an insulation (33) extending from the insulating layer toward the semiconductor layer in the second direction (Fig. 10B), wherein the insulation and the memory layer define an interface therebetween in a cross-section along the first direction, the cross-section including the stack (Fig. 10B), the semiconductor layer, the memory layer and the insulation, the interface having a first point (P1 in the annotated Fig. 10B above) and a second point (P2 in the annotated Fig. 10B above), the first point overlapping with a middle portion in the first direction of the insulating layer, the second point overlapping with an end portion in the first direction of the insulating layer (annotated Fig. 10B above), wherein the second point is closer to the insulating layer in the second direction than the first point is (note that the insulation has a curved profile and that the first point the farthest point of the insulation from the insulating layer and then the distance decreases as you move toward the second point) , and wherein the interface curves from the first point to the second point to protrude toward the semiconductor layer (annotated Fig. 10B above shows the curved profile of the insulation), wherein the memory layer has: a block insulation film (52) provided between the conductive layer and the semiconductor layer and between the insulation and the semiconductor layer ([0083]); a tunnel insulation film (56) provided between the block insulation film and the semiconductor layer ([0086]), and a charge storage film (54) provided between the block insulation film and the tunnel insulation film ([0084]), and wherein the charge storage film has: a first region overlapping with the conductive layer in the second direction (Fig. 10B); and a second region overlapping with the insulation in the second direction (Fig. 10B),
Cui does not disclose wherein the second region is smaller in thickness in the second direction than the first region and an interface between the semiconductor layer and the tunnel insulation film linearly extends in the first direction in the cross-section . However, Higuchi discloses a semiconductor memory device configuration (Figs. 5 and 13- 17) where a second region of a charge storage film (40) overlapping with an insulating regions (15) has a thickness that is smaller than a thickness a first region of a charge storage film overlapping with a conductive layer (14A) ([0016], [0062], and [0095]-[0097]). Higuchi also discloses that the interface between the semiconductor layer (20) and the tunnel insulation film linearly extends in the first direction in the cross-section (Fig. 16) and that such configuration yields to the amount of electrons that pass though the charge-storing film and reach the blocking insulation film can being reduced. This is because the amount of electrons trapped by the charge-storing film increases. This configuration suppresses a deterioration of the blocking insulation film 50 caused by repeated passage of electrons ([0097]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the thickness of the charge storage layer in the first and second region of Cui such that the second region is smaller in thickness in the second direction than the first region in order to suppress a deterioration of the blocking insulation film caused by repeated passage of electrons as discloses by Higuchi.
Considering claim 6, Cui discloses a semiconductor memory device comprising (Figs. 10A and 10B):
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a stack having a first insulating layer (32), a first conductive layer (46B), a second insulating layer (32), and a second conductive layer (46B), the first conductive layer being stacked on the first insulating layer in a first direction, the second insulating layer being stacked on the first conductive layer in the first direction, and the second conductive layer being stacked on the second insulating layer in the first direction (Figs. 10A and 10B, note that layers 32 and 46 are formed in an alternating fashion with layer 46B being the topmost layer of this stacked configuration); a semiconductor layer (60C) provided through the first and second insulating layers and the first and second conductive layers ([0091] and Figs. 10A and 10B): a memory layer (52+54+56) provided between the stack and the semiconductor layer in a second direction intersecting with the first direction (Fig. 10B); a first insulation (33) extending from the first insulating layer toward the semiconductor layer in the second direction; and a second insulation (33) extending from the second insulating layer toward the semiconductor layer in the second direction (Figs. 10A and 10B, note that the insulation is formed on the ends of the insulating pattern in an alternating fashion with both first and second insulations having the same reference number), wherein the first insulation and the memory layer define a first interface therebetween in a cross-section along the first direction (Fig. 10B), the cross-section including the stack, the semiconductor layer, the memory layer and the first and second insulations (Fig. 10B), the first interface having a first point (P1 in the annotated Fig. 10B above) and a second point (P2 in the annotated Fig. 10B above), the first point overlapping with a middle portion in the first direction of the first insulating layer, the second point overlapping with an end portion in the first direction of the first insulating layer (annotated Fig. 10B above), wherein the second insulation and the memory layer define a second interface therebetween in the cross-section, the second interface having a fourth point and a fifth point, the fourth point overlapping with a middle portion in the first direction of the second insulating layer, the fifth point overlapping with an end portion in the first direction of the second insulating layer (Figs. 10A and 10B, note that layers 32 and 46 are formed in an alternating fashion with layer 46B being the topmost layer of this stacked configuration and the insulation is formed on the ends of the insulating pattern in an alternating fashion with both first and second insulations having the same reference number therefore the first and second points are the same as the fourth and fifth points as one moves down the alternating stack shown in Fig. 10A), wherein the second point is closer to the first insulating layer in the second direction than the first point is (note that the insulation has a curved profile and that the first point the farthest point of the insulation from the insulating layer and then the distance decreases as you move toward the second point), wherein the fifth point is closer to the second insulating layer in the second direction than the fourth point is (note that it has been established that the first and fourth and second and fifth points are equivalent and that the insulation has a curved profile and that the first point the farthest point of the insulation from the insulating layer and then the distance decreases as you move toward the second point), wherein the first interface curves from the first point to the second point to protrude toward the semiconductor layer (annotated Fig. 10B above shows the curved profile of the insulation), and wherein the second interface curves from the fourth point to the fifth point to protrude toward the semiconductor layer (annotated Fig. 10B above shows the curved profile of the insulation), wherein the memory layer has: a block insulation film (52) provided between the conductive layer and the semiconductor layer and between the insulation and the semiconductor layer ([0083]); a tunnel insulation film (56) provided between the block insulation film and the semiconductor layer ([0086]), and a charge storage film (54) provided between the block insulation film and the tunnel insulation film ([0084]), and wherein the charge storage film has: a first region overlapping with the conductive layer in the second direction (Fig. 10B); and a second region overlapping with the insulation in the second direction (Fig. 10B), a third region overlapping with the second conductive layer in the second direction; and a fourth region overlapping with the second insulation in the second direction (Fig. 10B, note that it has been established that these structures are duplications of one another and that the first region and third region are the same and the second region and fourth region are the same and therefore the same rejection applies).
Cui does not disclose wherein the second region is smaller in thickness in the second direction than the first region, wherein the fourth region is smaller in thickness in the second direction than the third region ,and an interface between the semiconductor layer and the tunnel insulation film linearly extends in the first direction in the cross-section . However, Higuchi discloses a semiconductor memory device configuration (Figs. 5 and 13- 17) where a second region of a charge storage film (40) overlapping with an insulating regions (15) has a thickness that is smaller than a thickness a first region of a charge storage film overlapping with a conductive layer (14A) ([0016], [0062], and [0095]-[0097], note that like Cui the configuration is formed in an alternating fashion and therefore the first and third and the second and fourth are the same as they are duplicated for each portion in the stacked configuration). Higuchi also discloses that the interface between the semiconductor layer (20) and the tunnel insulation film linearly extends in the first direction in the cross-section (Fig. 16) and that such configuration yields to the amount of electrons that pass though the charge-storing film and reach the blocking insulation film can being reduced. This is because the amount of electrons trapped by the charge-storing film increases. This configuration suppresses a deterioration of the blocking insulation film 50 caused by repeated passage of electrons ([0097]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the thickness of the charge storage layer in the first and second region of Cui such that the second region is smaller in thickness in the second direction than the first region in order to suppress a deterioration of the blocking insulation film caused by repeated passage of electrons as discloses by Higuchi.
Continuing to claims 5 and 10, Cui in view of Higuchi discloses wherein the interface further has a third point (Cui P3 in the annotated Fig. 10B above) overlapping with a middle portion in the first direction of the conductive layer, and wherein a distance (Cui D1 in the annotated Fig. 10B above) between the first point and the third point in the second direction is not less than 0.5 nm nor more than 5 nm (Cui [0083] and [0116], note that the distance D1 coincides with the thickness of portion of the memory layer 52 which can range from 1nm to 20nm with the examiner relying on the lower end of the range for examination purposes. Therefore the distance D1 is 1nm and the limitation is satisfied) and wherein the first interface further has a third point (Cui P3 in the annotated Fig. 10B above) overlapping with a middle portion in the first direction of the first conductive layer, wherein the second interface further has a sixth point (Cui P3 in the annotated Fig. 10B above, note that in Fig.10A layers 32 and 46 are formed in an alternating fashion with layer 46B being the topmost layer of this stacked configuration and the insulation is formed on the ends of the insulating pattern in an alternating fashion with both first and second insulations having the same reference number therefore the first, second, and third points are the same as the fourth, fifth, and sixth points respectively as one moves down the alternating stack shown in Fig. 10A) overlapping with a middle portion in the first direction of the second conductive layer, wherein a distance between the first point and the third point in the second direction is not less than 0.5 nm nor more than 5 nm, and wherein a distance (Cui D1 in annotated Fig. 10B above) between the fourth point and the sixth point in the second direction is not less than 0.5 nm nor more than 5 nm (Cui [0083] and [0116], note it has been established that the first, second, and third points are the same as the fourth, fifth, and sixth points respectively as one moves down the alternating stack shown in Fig. 10A and the distance D1 (having the same reference number as the previously recited D1) coincides with the thickness of portion of the memory layer 52 which can range from 1nm to 20nm with the examiner relying on the lower end of the range for examination purposes. Therefore the distance D1 is 1nm and the limitation is satisfied.)
Referring to claim 11, Cui in view of Higuchi discloses wherein each of the first and second insulating layers contains silicon and oxygen (Cui [0053]).
Regarding claim 12, Cui in view of Higuchi discloses wherein the first insulation do not be in contact with each of the first and the second conductive layers (Cui Fig. 10B, it is noted that a blocking insulation layer 44 is formed to surround the conductive layer 46 (46A and 46B) and therefore the first insulation is not in contact with the conductive layer, but is instead in direct physical contact with the blocking layer 44), and wherein the second insulation do not be in contact with each of the first and the second conductive layers (Cui Fig. 10B note that this layer is a duplication of the first insulation and it is noted that a blocking insulation layer 44 is formed to surround the conductive layer 46 (Cui 46A and 46B) and therefore the first insulation is not in contact with the conductive layer, but is instead in direct physical contact with the blocking layer 44).
Pertaining to claim 13, Cui in view of Higuchi discloses wherein the memory layer does not be in contact with each of the first and second insulating layers (Cui Fig. 10B and [0115], it is noted that the block insulation layer (Cui 52) of the memory layer is not in direct physical contact with the insulating layers 32 and are instead in contact with the insulation).
Continuing to claim 14, Cui in view of Higuchi discloses wherein the block insulation film is in contact with each of the first and second insulations (Cui Fig. 10B and [0115]), note that the block insulation film (Cui 52) of the memory layer (Cui 52) is in direct physical contact with the first and second insulations).
Referring to claim 15, Cui in view of Higuchi discloses wherein the block insulation film is in contact with each of the first and second conductive layers (Cui [0115], it is noted that when a block insulation film (Cui 52) is provided the block insulating film (Cui 44) which surrounds the conductive layer may be omitted. Therefore the examiner is relying on this disclosure as meeting the limitation of the block insulation film is in contact with each of the first and second conductive layers).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220285388 (Cui et al) as applied to claim 16 above, and further in view of US 20170271527 (Higuchi et al).
Regarding claim 18, Cui discloses wherein the memory layer has: a block insulation film (52) provided between the first surface and the semiconductor layer and between the insulation and the semiconductor layer ([0083]); a tunnel insulation film (56) provided between the block insulation film and the semiconductor layer ([0086]), and a charge storage film (54) provided between the block insulation film and the tunnel insulation film ([0084]), and wherein the charge storage film has: a first region overlapping with the third layer in the second direction (Fig. 10B); and a second region overlapping with the insulation in the second direction (Fig. 10B).
Cui does not disclose wherein the second region is smaller in thickness in the second direction than the first region and an interface between the semiconductor layer and the tunnel insulation film linearly extends in the first direction in the cross-section . However, Higuchi discloses a semiconductor memory device configuration (Figs. 5 and 13- 17) where a second region of a charge storage film (40) overlapping with an insulating regions (15) has a thickness that is smaller than a thickness a first region of a charge storage film overlapping with a conductive layer (14A) ([0016], [0062], and [0095]-[0097]). Higuchi also discloses that the interface between the semiconductor layer (20) and the tunnel insulation film linearly extends in the first direction in the cross-section (Fig. 16) and that such configuration yields to the amount of electrons that pass though the charge-storing film and reach the blocking insulation film can being reduced. This is because the amount of electrons trapped by the charge-storing film increases. This configuration suppresses a deterioration of the blocking insulation film 50 caused by repeated passage of electrons ([0097]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the thickness of the charge storage layer in the first and second region of Cui such that the second region is smaller in thickness in the second direction than the first region in order to suppress a deterioration of the blocking insulation film caused by repeated passage of electrons as discloses by Higuchi.
Claim(s) 3, 4, 8, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220285388 (Cui et al) in view of US 20170271527 (Higuchi et al) as applied to claims 1 and 6 above, and further in view of US 20210343728 (Surthi et al).
Pertaining to claims 3 and 8 (with these claims being similar in scope), Cui in view of Higuchi discloses wherein the insulation contains silicon, oxygen, and carbon (Cui [0053] and [0079], it is noted that the material of the insulation may be an organosilicate glass which contains silicon, carbon, and oxygen), . . . wherein each of the first and second insulations contains silicon, oxygen, and carbon (Cui [0053] and [0079], it is noted that the material of the insulation may be an organosilicate glass which contains silicon, carbon, and oxygen), . . .and wherein the first layer contains silicon and nitrogen (Cui [0074]), wherein the second layer contains silicon and oxygen (Cui [0074]), wherein the insulation contains silicon, oxygen, and carbon (Cui [0053] and [0079], it is noted that the material of the insulation may be an organosilicate glass which contains silicon, carbon, and oxygen).
Cui in view of Higuchi does not disclose that a concentration of the carbon in the insulation is higher than a concentration of carbon in the insulating layer, and wherein a concentration of the carbon in the first insulation is higher than a concentration of carbon in the first insulating layer, and wherein a concentration of the carbon in second first insulation is higher than a concentration of carbon in the second insulating layer, or wherein a concentration of the carbon in the insulation is higher than a concentration of carbon in the first layer. However, Surthi discloses a semiconductor memory device configuration (Figs. 9- 13) in which an insulation (22) made of SiOC ([0044]) is formed over an insulating layer (60) made of silicon dioxide ([0036]), a second layer (62) made of silicon nitride ([0036]) where the concentration of carbon in the insulation is within the range of 4 at% to about 20 at% ([0044]). Surthi discloses that this configuration and concentration function as an etch-stop in subsequent processing and allow for selective etching ([0042]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the insulation of Cui such that the concentration of carbon in the insulating layer is higher than the concentration of carbon in the first and second insulating layers as disclosed by Surthi in order to allow the insulation to act as an etch stop in subsequent processing of the device and allow for selective etching.
As to claims 4 and 9 (with these claims being similar in scope), Cui in view of Higuchi and Surthi discloses wherein the concentration of the carbon in the insulation is not less than 1 at.% nor more than 20 at.% (Surthi [0044]), and wherein the insulation has a thickness of not less than 0.5 nm nor more than 5 nm in the second direction (Cui [0079], it is noted that the thickness of feature 33 is disclosed to be from 2 nm to 22 nm and the examiner ins relying on the lower end of the range for examination purposes. Therefore the thickness of the insulation is 2 nm and the limitation is satisfied), wherein the concentration of the carbon in the first insulation is not less than 1 at.% nor more than 20 at.% (Surthi [0044), wherein the concentration of the carbon in the second insulation is not less than 1 at.% nor more than 20 at.% (Surthi [0044], it is noted the second insulation is a duplication of the first insulation), wherein the first insulation has a thickness of not less than 0.5 nm nor more than 5 nm in the second direction (Cui [0079], it is noted that the thickness of feature 33 is disclosed to be from 2 nm to 22 nm and the examiner ins relying on the lower end of the range for examination purposes. Therefore the thickness of the insulation is 2 nm and the limitation is satisfied), and wherein the second insulation has a thickness of not less than 0.5 nm nor more than 5 nm in the second direction (Cui [0079], it is noted that the second insulation is a duplication of the first insulation and that the thickness of feature 33 is disclosed to be from 2 nm to 22 nm and the examiner ins relying on the lower end of the range for examination purposes. Therefore the thickness of the insulation is 2 nm and the limitation is satisfied), and wherein the concentration of the carbon in the insulation is not less than 1 at.% nor more than 20 at.% (Surthi [0044]), and wherein the insulation has a thickness of not less than 2 nm nor more than 7 nm in the second direction (Cui [0079], it is noted that the thickness of feature 33 is disclosed to be from 2 nm to 22 nm and the examiner ins relying on the lower end of the range for examination purposes. Therefore the thickness of the insulation is 2 nm and the limitation is satisfied).
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220285388 (Cui et al) in view of US 20210343728 (Surthi et al).
Pertaining to claim 19, Cui discloses wherein the insulation contains silicon, oxygen, and carbon ([0053] and [0079], it is noted that the material of the insulation may be an organosilicate glass which contains silicon, carbon, and oxygen), . . . wherein each of the first and second insulations contains silicon, oxygen, and carbon ([0053] and [0079], it is noted that the material of the insulation may be an organosilicate glass which contains silicon, carbon, and oxygen), . . .and wherein the first layer contains silicon and nitrogen ([0074]), wherein the second layer contains silicon and oxygen ([0074]), wherein the insulation contains silicon, oxygen, and carbon ([0053] and [0079], it is noted that the material of the insulation may be an organosilicate glass which contains silicon, carbon, and oxygen).
Cui does not disclose that a concentration of the carbon in the insulation is higher than a concentration of carbon in the insulating layer, and wherein a concentration of the carbon in the first insulation is higher than a concentration of carbon in the first insulating layer, and wherein a concentration of the carbon in second first insulation is higher than a concentration of carbon in the second insulating layer, or wherein a concentration of the carbon in the insulation is higher than a concentration of carbon in the first layer. However, Surthi discloses a semiconductor memory device configuration (Figs. 9- 13) in which an insulation (22) made of SiOC ([0044]) is formed over an insulating layer (60) made of silicon dioxide ([0036]), a second layer (62) made of silicon nitride ([0036]) where the concentration of carbon in the insulation is within the range of 4 at% to about 20 at% ([0044]). Surthi discloses that this configuration and concentration function as an etch-stop in subsequent processing and allow for selective etching ([0042]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the insulation of Cui such that the concentration of carbon in the insulating layer is higher than the concentration of carbon in the first and second insulating layers as disclosed by Surthi in order to allow the insulation to act as an etch stop in subsequent processing of the device and allow for selective etching.
As to claim 20, Cui in view of Surthi discloses wherein the concentration of the carbon in the insulation is not less than 1 at.% nor more than 20 at.% (Surthi [0044]), and wherein the insulation has a thickness of not less than 0.5 nm nor more than 5 nm in the second direction (Cui [0079], it is noted that the thickness of feature 33 is disclosed to be from 2 nm to 22 nm and the examiner ins relying on the lower end of the range for examination purposes. Therefore the thickness of the insulation is 2 nm and the limitation is satisfied), wherein the concentration of the carbon in the first insulation is not less than 1 at.% nor more than 20 at.% (Surthi [0044), wherein the concentration of the carbon in the second insulation is not less than 1 at.% nor more than 20 at.% (Surthi [0044], it is noted the second insulation is a duplication of the first insulation), wherein the first insulation has a thickness of not less than 0.5 nm nor more than 5 nm in the second direction (Cui [0079], it is noted that the thickness of feature 33 is disclosed to be from 2 nm to 22 nm and the examiner ins relying on the lower end of the range for examination purposes. Therefore the thickness of the insulation is 2 nm and the limitation is satisfied), and wherein the second insulation has a thickness of not less than 0.5 nm nor more than 5 nm in the second direction (Cui [0079], it is noted that the second insulation is a duplication of the first insulation and that the thickness of feature 33 is disclosed to be from 2 nm to 22 nm and the examiner ins relying on the lower end of the range for examination purposes. Therefore the thickness of the insulation is 2 nm and the limitation is satisfied), and wherein the concentration of the carbon in the insulation is not less than 1 at.% nor more than 20 at.% (Surthi [0044]), and wherein the insulation has a thickness of not less than 2 nm nor more than 7 nm in the second direction (Cui [0079], it is noted that the thickness of feature 33 is disclosed to be from 2 nm to 22 nm and the examiner ins relying on the lower end of the range for examination purposes. Therefore the thickness of the insulation is 2 nm and the limitation is satisfied).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 6 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 12/03/25 have been fully considered but they are not persuasive. In [0077] Cui discloses that the deposition of the insulation is an area-selective deposition in which the insulation is deposited/grown on the insulating surfaces and the growth is suppressed (and therefore unwanted) on the surface 41. Therefore the examiner believes that the limitation of the insulation not being formed on the protective film is satisfied because the growth of the insulation is suppressed and the rejection stands.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VALERIE N NEWTON/Examiner, Art Unit 2897 03/04/26
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897