Prosecution Insights
Last updated: April 19, 2026
Application No. 18/332,813

MEMORY DEVICE

Final Rejection §102
Filed
Jun 12, 2023
Examiner
NEWTON, VALERIE N
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Kioxia Corporation
OA Round
2 (Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
2y 7m
To Grant
90%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
761 granted / 905 resolved
+16.1% vs TC avg
Moderate +6% lift
Without
With
+5.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
41 currently pending
Career history
946
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
57.1%
+17.1% vs TC avg
§102
29.3%
-10.7% vs TC avg
§112
7.5%
-32.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 905 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20210020657 (Song). Concerning claim 1, Song discloses a memory device comprising (Figs. 2 and 3A-3D): PNG media_image1.png 502 524 media_image1.png Greyscale a plurality of first conductors (EL) aligned in a first direction (D3) separately from each other (Fig. 3C and [0031]-[0032]); a memory pillar (VS) that penetrates the plurality of first conductors in the first direction and includes a semiconductor (VP) and a film (VI) that surrounds the semiconductor (Fig. 3C and [0038]-[0039]); and a first member (CSP + SP + RR +SS) that penetrates the plurality of first conductors in the first direction (Fig. 3A) and has a first portion (rectangular region in annotated Fig. 3D above) and a plurality of second portions (circled region in annotated Fig. 3D above) the first portion extending in a second direction (D1) intersecting with the first direction, the plurality of second portions being aligned spaced apart in the second direction on an upper surface of the first portion (Fig. 3D), a length of each of the plurality of second portions in a third direction intersecting with the first direction and the second direction being shorter than a length of the first portion in the third direction (Figs. 3A-3D), wherein the first member further includes a bridge (SP) that is positioned on the upper surface of the first portion and between two neighboring ones of the plurality of second portions and extends on the upper surface of the first portion across both ends of the first portion (Fig. 3D). Considering claim 13, Song discloses a memory device comprising: PNG media_image1.png 502 524 media_image1.png Greyscale a plurality of first conductors (EL) aligned in a first direction (D3) separately from each other (Fig. 3C and [0031]-[0032]); a memory pillar (VS) that penetrates the plurality of first conductors in the first direction and includes a semiconductor (VP) and a film (VI) that surrounds the semiconductor (Fig. 3C and [0038]-[0039]); and a first member (CSP + SP + RR +SS) that penetrates the plurality of first conductors in the first direction (Fig. 3A) and has a first portion (rectangular region in annotated Fig. 3D above) and a plurality of second portions (circled region in annotated Fig. 3D above), the first portion extending in a second direction (D1) intersecting with the first direction, the plurality of second portions being aligned spaced apart in the second direction on an upper surface of the first portion (Fig. 3D), a length of each of the plurality of second portions in a third direction intersecting with the first direction and the second direction being shorter than a length of the first portion in the third direction (Figs. 3A-3D), and the first portion and the second portions being continuous (Fig. 3D). Continuing to claim 2, Song discloses wherein the first member comprises a plurality of the bridges (Fig. 3D, note that the structures SP are formed between the circled regions and alternate in the second direction D1), and the plurality of the bridges and the plurality of second portions are aligned to alternate with each other one at a time in the second direction (Fig. 3D, note that the structures SP are formed between the circled regions and alternate in the second direction D1). Referring to claims 3 and 14 (with these claims being similar in scope), Song discloses wherein the first portion spans continuously in the first direction and the second direction (annotated Fig. 3D rectangular region). Regarding claim 4, Song discloses further comprising a first insulator (111) on an upper surface of the memory pillar ([0042]), wherein the bridge includes a part of the first insulator (Fig. 3A), and the first insulator on the upper surface of the memory pillar is continuous with the part of the first insulator included in the bridge (Figs. 3A and 3D). Pertaining to claims 5 and 15 (with these claims being similar in scope), Song discloses wherein a center position of the plurality of second portions in the third direction differs from a center position of the first portion in the third direction (Fig. 3D, note that the left most second portion has a center position that is different than the first portion). As to claims 6 and 16 (with these claims being similar in scope), Song discloses wherein the first member includes a second conductor (CSP) and a second insulator (SS) on a surface of the second conductor (Fig. 3D and [0046]-[0047]). Concerning claims 7 and 17 (with these claims being similar in scope), Song discloses wherein the second insulator covers a side surface of the second conductor (Figs. 3A, 3B, and 3D). Considering claim 8, Song discloses wherein the second insulator has a portion positioned on a lower surface of the bridge and a side surface of the bridge (Fig. 3D). Continuing to claim 9, Song discloses further comprising a first insulator (111) that is positioned on an upper surface of the memory pillar and is included in the bridge (Fig. 3A), wherein the second conductor faces the first insulator in the second portion, with the second insulator interposed therebetween (Figs. 3A and 3B). Referring to claims 10 and 18 (with these claims being similar in scope), Song discloses wherein the second insulator is positioned continuously over a side surface of the first portion (Fig. 3A) and side surfaces of the plurality of second portions (Fig. 3D). Regarding claim 11, Song discloses wherein the first member includes a second insulator (SS) and a third insulator (SP) on a surface of the second insulator, the third insulator contains a material differing from a material of the second insulator ([0047] and [0068]), and the second insulator faces the first insulator in the second portion, with the third insulator interposed therebetween (Figs. 3A and 3D). Pertaining to claims 12 and 20 (with these claims being similar in scope), Song discloses wherein the second insulator has a portion positioned in a center of the first member in the third direction (Fig. 2). As to claim 19, Song discloses wherein the second insulator (SS) has a portion positioned on an upper surface of the first portion (Fig. 3D). Response to Arguments Applicant's arguments filed 12/09/25 have been fully considered but they are not persuasive. Applicant argues that the prior art reference fails to disclose that a length of each of the plurality of second portions in a third direction intersecting with the first direction and the second direction being shorter than a length of the first portion in the third direction, as required by Claim 1. Moreover, given that the prior art reference’s D2 direction is associated with the claimed third direction, since the sidewall ESS has a tapered shape, as shown in Figure 3B, the width in the D2 direction of the portion associated with the second portions is actually larger than the width in the D2 direction of the portion associated with the first portion, which is opposite to what is required by Claim 1. However the examiner disagrees. Song discloses that the support pattern SP may have a width W1, which increases with increasing distance from the substrate 100, when measured in the second direction D2. The width of the support pattern SP in the second direction D2 may be largest at its top level ([0044]). The width of the support portion directly affects the width of the second portion. As the width of the support portion increases in D2 (third direction) the width of the second portion decreases in D2. Therefore the examiner believes that the limitation of the length of each of the plurality of second portion in the third direction (D2) is shorter than a length of the first portion in the third direction is met and the rejection stands. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VALERIE N NEWTON/ Examiner, Art Unit 2897 03/17/26 /CHAD M DICKE/ Supervisory Patent Examiner, Art Unit 2897
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Prosecution Timeline

Jun 12, 2023
Application Filed
Sep 18, 2025
Non-Final Rejection — §102
Dec 09, 2025
Response Filed
Mar 17, 2026
Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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SOLID STATE OPTOELECTRONIC DEVICE WITH PREFORMED METAL SUPPORT SUBSTRATE
2y 5m to grant Granted Apr 07, 2026
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Patent 12581734
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2y 5m to grant Granted Mar 17, 2026
Patent 12575258
DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME
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Patent 12568681
ACTIVE REGION PATTERNING
2y 5m to grant Granted Mar 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
90%
With Interview (+5.6%)
2y 7m
Median Time to Grant
Moderate
PTA Risk
Based on 905 resolved cases by this examiner. Grant probability derived from career allow rate.

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