DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/15/2024, is in compliance with the provisions 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6, 8-10, 13 and 15-18 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Moen et al. (US 20180323187) herein referred to as Moen. (Fig. 3E, Fig. 3A)
As to claim 1, Moen teaches an integrated circuit (IC) device, comprising:
a layer ([0041] “p-type semiconductor substrate 301”) comprising a first doped semiconductor material with a first doping type (1st type, p-type);
a first region (318) over the layer (301), the first region comprising a second doped material (2nd type, n-type); with a second doping type ([0042] deep n-well (DNW) 318) that is opposite from the first doping type
a second region (region including 316 or 317) over the layer, the second region comprising a third doped semiconductor material with the second doping type ([0042] “ N-well regions 316/317);
a first structure ([0042] “N-well regions 316) comprising a fourth doped semiconductor material with the second doping type, the first structure at least partially surrounded by the first region (318);
a second structure ([0042] “P-well 315”) comprising a fifth doped semiconductor material with the first doping type, the second structure at least partially surrounded by the second region (region including 316 or 317); and
an electrically conductive structure (311-314) comprising a first portion over the first structure (316) and a second portion over the second structure (315) ([0042] RF switch transistor 310 includes n-channel CMOS transistor structures 311-314),.
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As to claim 6, Moen teaches the IC device according to claim 1 and further discloses, wherein
the first region (region of 318) or the second region (region including 316 or 317) is over the layer (301) in a first direction (y-direction) , and
a dimension of the first region (region of 318) in a second direction (x-direction) perpendicular to the first dimension is larger than a dimension of the second region (region including 316 or 317) in the second direction.
As to claim 8, Moen teaches an integrated circuit (IC) device, Fig. 3E or 3A comprising:
a base section (343) comprising a first P-well (333) and a P-type semiconductor structure ([0045] “p-region 562” );
a N-well (334) over at least one of the base section (343), the emitter section (342), and the collector section (344);
an emitter section (342) comprising a second P-well (561, Fig. 3E) and a first N-type semiconductor structure (578);
a collector section ([0045] collector regions 344-345) comprising a N-well (334) and a second N-type semiconductor structure (345);
a first contact ([0041]”Power amplifiers 115-116 can be implemented with SiGe HBTs corresponding with those found in HBT region 340”.) electrically coupled to the P-type semiconductor structure ([0045] “p-region 562” ) and the first N-type semiconductor structure (578); and
a second contact electrically ([0041]”Power amplifier 116) coupled to the second N-type semiconductor structure (345).
As to claim 9, the IC device according to claim 8, wherein
a distance from an edge of the P-type semiconductor structure ([0045] “p-region 562” ) to an edge of the first P-well (333) in a direction is greater than a distance from an edge of the first N-type semiconductor structure (578) to an edge of the second P-well (561).
As to claim 10, the IC device according to claim 8, further comprising:
a P-doped substrate (301) over the N-well (334), wherein
the N-well (334) is between the P-doped substrate (301) and at least one of the base section (343), the emitter section (342), and the collector section (344).
As to claim 13, the IC device according to claim 8, further comprising:
an electrical insulator between the first P-well (333) and the second P-well (561, Fig. 3E). ([0044] “Transistor region 330 is isolated from devices in the other regions 310, 320 and 340 of semiconductor structure 300 by shallow trench isolation regions 355-357 and deep trench isolation regions 365-366.”)
As to claim 15, Moen teaches a method for forming an integrated circuit (IC) device, comprising:
forming an N-well (334) in a substrate (301), the N-well between a first portion (Annotated 1st portion) of the substrate and a second portion (Annotated 2nd portion) of the substrate in a first direction (y direction);
forming a first P-well (315) in the first portion of the substrate by doping a first part of the first potion of the substrate (301);
forming a second P-well (333) in the first portion of the substrate (301) by doping a second part of the first potion of the substrate (301);
forming a N-well (334) in the first portion of the substrate (301) by doping a third part of the first potion of the substrate (301), wherein the second part is between the first part and the third party in a second direction (x direction) that is perpendicular to the first direction (y direction);
forming a first semiconductor structure ([0042] “N-well regions 316) in the first P-well (315);
forming a second semiconductor (317) structure in the second P-well (333); and
forming a third semiconductor ([0044] Annotated CMOS 332 structure ) structure in the N-well (334).
As to claim 16, Moen teaches the method according to claim 15 and further discloses:
forming an electrically conductive structure (311-314), a first portion of the electrically conductive structure over the first semiconductor structure (316), a second portion of the electrically conductive structure over the second semiconductor structure (317).
As to claim 17, Moen teaches the method according to claim 15 and further discloses:
forming an electrically conductive structure ([0044] The 1.8V/5V CMOS transistor region 330) over the third semiconductor structure ([0044] Annotated CMOS 332 structure ).
As to claim 18, Moen teaches the method according to claim 15 and further discloses:
forming a well in the first portion of the substrate (301) by doping a fourth part of the first potion of the substrate (301), wherein
the fourth part is between the second part and the third party in the second direction (x direction).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claim(s) 5, 7, 14, 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moen et al. (US 20180323187) herein referred to as Moen. (Fig. 3E, Fig. 3A)
As to claim 5, Moen discloses the IC device according to claim 1,
Moen does not appear to expressly disclose: “a dopant concentration in the second region is at least 2.5 times higher than a dopant concentration in the first region.” Having a dopant concentration in the second region that is at least 2.5 times higher than in the first region is a design requirement typically used to asymmetrically control depletion width, minimize series resistance, block unwanted carrier injection, or form low-resistance ohmic contacts in semiconductor devices.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to adjust the dopant concentration in the second region of the Moen device to at least 2.5 times higher than a dopant concentration in the first region so as to optimize device performance, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. )
Furthermore, the Applicant has not shown that a dopant concentration in the second region is at least 2.5 times higher than a dopant concentration in the first region is novel and would not have been found through routine experimentation.
As to claim 7, Moen discloses the IC device according to claim 1, further comprising:
a third region (554) over the layer (301), the third region comprising a sixth doped semiconductor material with the first doping type (1st type, p-type), wherein
and the second region (region including 316 or 317) is between the first region (318) and the third region (554).
Moen does not appear to expressly disclose: “a dopant concentration in the third region is no more than half of a dopant concentration in the second region.” Restricting a dopant concentration in a third region to no more than half of the concentration in a second region helps control electric field gradients, manage depletion layer widths, and prevent severe lattice distortion or self-compensation effects in tiered semiconductor device structures.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to adjust the dopant concentration in the third region is no more than half of a dopant concentration in the second region so as to optimize device performance, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. )
Furthermore, the Applicant has not shown that a dopant concentration in the third region is no more than half of a dopant concentration in the second region are novel and would not have been found through routine experimentation.
As to claim 14, Moen discloses the IC device according to claim 8,
Moen does not appear to expressly disclose: “a dopant concentration in the first P-well is lower than a dopant concentration in the second P-well or the N-well.” Optimizing dopant concentration in semiconductors precisely balances electrical conductivity against carrier mobility and crystal defect limits. Finding this ideal level maximizes device performance, controls threshold voltages, and prevents excess resistance or unwanted charge recombination.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to adjust the dopant concentration in the first P-well to be lower than a dopant concentration in the second P-well or the N-well so as to optimize device performance, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. )
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moen et al. (US 20180323187) herein referred to as Moen, in view of David Hu, herein referred to as Hu (US 20030102509).
As to claim 19, Moen discloses the method according to claim 18, forming the well (334),
Moen does not appear to expressly disclose: “forming the well before forming the N-well”. In standard P-type substrate CMOS processes, the N-well is formed first as a deep implant before creating localized P-wells or active regions. This sequence accommodates high-temperature drive-in diffusion steps for deeper N-wells, prevents shallow profile distortion, and aligns with baseline compatibility for PMOS and NMOS integration.
Hu teaches in [0053] “The n-wells are typically formed before the N and P diffusions.”
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to form the well in the Moen device, before forming the N-well as in the Hu device since it necessary to form the well area before doping of the well takes place, so as to use an industrially tested and accepted method of manufacturing.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moen et al. (US 20180323187) herein referred to as Moen, in view of Lin et al. herein referred to as Lin (US 20170047317)
As to claim 20, Moen discloses the method according to claim 15, further comprising:
after forming the N-well (334), Fig. 5A-5G
Moen does not appear to expressly disclose: “after forming the N-well, forming a gate over the first semiconductor structure, the second semiconductor structure, or the third semiconductor structure in the second direction.” It is standard and necessary to form the N-well before forming the gate in a conventional self-aligned CMOS fabrication process. If you formed the gate first, extreme temperatures would melt, deform, or cause unwanted chemical reactions in the gate structures. Lin discloses in [0054] ”In some examples, the n-well 502 may be formed before the gate devices 104.”
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, after forming the N-well in the Moen device, to form a gate over the semiconductor structures, so as to ensure the device reliability/design and connectivity requirements to use an industrially tested and accepted method of manufacturing as is disclosed in the Lin device..
Allowable Subject Matter
Claims 2- 4 and 11-12 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance: The prior art taken either singularly or in combination, fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper. The prior art, Moen et al. (US 20180323187) fails to teach a combination of all of the features in the claims.
As to claims 2, the prior art fails to teach all the limitations of each claim.
Moen teaches the IC device according to claim 1, further comprising:
a third region (554) over the layer (301), the third region comprising a sixth doped semiconductor material with the first doping type (1st type, p-type); and
the second region (region including 316 or 317) is between the first region (318) and the third region (554).
Moen does not disclose:
a third structure (573) comprising a seventh doped semiconductor material with the first doping type, the third structure at least partially surrounded by the third region, wherein
As to claim 11, the prior art fails to teach all the limitations of each claim the IC device according to claim 8.
Moen teaches a bipolar transistor comprising a base section (343). However, bipolar transistors do not have gate.
Therefore, Moen does not teach a gate and at least part of the gate is over the P-type semiconductor structure.
As to claim 12, the prior art fails to teach all the limitations of each claim the IC device according to claim 8.
Moen teaches the P-type semiconductor structure ([0045] “p-region 562”, Fig. 3E), the first N-type semiconductor structure (578), or the second N-type semiconductor structure (345).
Moen does not teach the device includes a fin or nanoribbon.
Claims 3 and 4 are allowable at least because they depend from allowable claims 2 and 4, respectively.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN SHAW MUSLIM whose telephone number is (571)270-0071. The examiner can normally be reached Mon-Fri 7 am - 4 pm.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/SHAWN SHAW MUSLIM/Examiner, Art Unit 2897
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