DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
The Amendment filed on 11/17/2025, responding to the Office action mailed
on 8/28/2025, has been entered into the record. The present Office action is made
with all the suggested amendments being fully considered. Accordingly, claims 1-10 are pending in this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Masuoka (US 20100219483 A1) (M83 hereafter) in view of Anderson (US 20170179303 A1) and Masuoka (US 20150364608 A1) (M08 hereafter) and Masuoka (US 20170301679 A1) (M79 hereafter).
Re Claim 1 M83 teaches manufacturing method for manufacturing a pillar-shaped semiconductor device (FIG. 17B), wherein the pillar-shaped semiconductor device comprises a surrounding gate transistor [0128] (SGT} including, a semiconductor pillar (21a) [0065] standing on an upper part of a substrate (1) [0058], a gate insulating layer (17) [0065] surrounding the semiconductor pillar (21a), a gate conductor layer (18) surrounding the gate insulating layer (17), a first impurity region (3a) [0057] connected to a lower end of the semiconductor pillar (21a), and a second impurity region (14) [0065] connected to a top end of the semiconductor pillar (21a), and further wherein the semiconductor pillar (21a) forms a channel (FIG. 17B) between the first impurity region (3a) and the second impurity region (14), the method comprising:
forming the first impurity region (3a) containing donor or acceptor impurities [0057] on an upper surface of the substrate (top of 1);
forming the semiconductor pillar (21a) on the first impurity region (3a) in contact with the first impurity region (FIG. 17B);
coating the upper surface of the substrate (1) and a side wall of the semiconductor pillar (21a) with a first mask material layer (34) [0087];
M83 does not teach forming an inter-element insulation region in the substrate to surround the semiconductor pillar;
forming a first insulation layer, separately from the inter-element insulation region, on the exposed upper surface of the first impurity region between the inter-element insulation region and the semiconductor pillar to surround the semiconductor pillar so that the first insulation layer has an upper surface that coincides with an upper surface of the inter-element insulation region, wherein the first insulation layer demarcates a lower end position of the gate conductor layer;
forming the gate insulating layer which surrounds the semiconductor pillar and the gate conductor layer which surrounds the gate insulating layer; and
forming the second impurity region in the top end of the semiconductor pillar.
Anderson teaches forming an inter-element insulation region (330) [0092] in the substrate (100) [0076] to surround the semiconductor pillar (750, [0121], FIG. 20);
forming a first insulation layer (820) [0131], separately from the inter-element insulation region (330), on the exposed upper surface of the first impurity region (400) [0099] between the inter-element insulation region (330) and the semiconductor pillar (750) to surround the semiconductor pillar so that the first insulation layer (820) has an upper surface that coincides with an upper surface of the inter-element insulation region (330, FIG. 22), wherein the first insulation layer (820) demarcates a lower end position of the gate conductor layer (1030, [0151], FIG. 31)
forming the gate insulating layer (920, [0136] “…WFM cap 920 is a sum of at least one high-k oxide layer …”) which surrounds the semiconductor pillar (750) and the gate conductor layer (1030) which surrounds the gate insulating layer (920); and
forming the second impurity region (1520) in the top end of the semiconductor pillar (750, FIG. 38).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Anderson into the structure of M83 since Anderson teaches a semiconductor device with pillars used as device channels.
The ordinary artisan would have been motivated to modify Anderson in combination with M83 in the above manner for the motivation of forming inter-element insulation regions to help isolate current channels and ensure the device function optimally. [0092] states, “The STI regions 330 separate the islands 220, and provide electrical insulation between the substrate areas below the islands 220.”
M83 in view of Anderson does not teach removing the first mask material layer, except the first mask material layer that covers the side wall of the semiconductor pillar and exposing the upper surface of the first impurity region by etching of the first mask material layer;
removing the first mask material layer that remains on the side wall of the semiconductor pillar by etching.
M08 teaches removing the first mask material layer (116) [0091], except the first mask material (117) layer that covers the side wall of the semiconductor pillar (124) [0068] and exposing the upper surface of the first impurity region (FIG. 9B shows the layer 116 etched to form 117, and FIG. 10B shows the exposed source, 120, [0082]) by etching of the first mask material layer (FIG. 8B and 10B);
removing the first mask material layer that remains (117) on the side wall of the semiconductor pillar (124) by etching (FIG. 11B) [0093].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by M08 into the structure of M83 in view of Anderson since M08 teaches a semiconductor device with pillars used as device channels.
The ordinary artisan would have been motivated to modify M08 in combination with M83 in view of Anderson in the above manner for the motivation of optimally etching the mask layer around the semiconductor pillars to form a device that is nonvolatile and functions optimally. [0013] states, “According to the present invention, it is possible to provide a nonvolatile semiconductor memory transistor having a structure utilizing an island-shaped semiconductor…”
M83 in view of Anderson and M08 does not teach applying thermal or chemical oxidation to form a first insulation layer; and
isotropic etching the first mask material layer
M79 teaches applying thermal oxidation [0103] to form a first insulation layer (14, FIG. 2AB); and
isotropic etching [0108] the first mask material layer (28a, FIG. 2FB).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by M79 into the structure of M83 in view of Anderson and M08 since M79 teaches a semiconductor device with pillars used as device channels.
The ordinary artisan would have been motivated to modify M79 in combination with M83 in view of Anderson and M08 in the above manner for the motivation of using a thermal oxidation process and isotropic etching process to optimally build a semiconductor device as size is continuing to be reduced in semiconductors. [0005] states, “Increasing the degree of integration of CMOS inverter circuits directly leads to size-reduction of circuit chips such as microprocessors.”
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Masuoka (US 20100219483 A1) (M83 hereafter) in view of Anderson (US 20170179303 A1) and Masuoka (US 20150364608 A1) (M08 hereafter) and Masuoka (US 20170301679 A1) (M79 hereafter) and Masuoka (US 8530960 B2) (M60 hereafter).
Re Claim 2 M83 in view of Anderson and M08 and M79 teaches the manufacturing method of a pillar-shaped semiconductor device according to claim 1, wherein a film thickness of the first insulation layer (Anderson, 820) is set thicker than a film thickness of the gate insulating layer (920).
M83 in view of Anderson and M08 and M79 does not teach a position of a lower end of the gate conductor layer is positioned at or lower than an upper end position of the first impurity region in the semiconductor pillar.
M60 teaches a position of a lower end of the gate conductor layer (125, col 7 line 25) is positioned at or lower than an upper end position of the first impurity region (119, col 7 line 30) in the semiconductor pillar (159, FIG. 28).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by M60 into the structure of M83 in view of Anderson and M08 and M79 since M60 teaches a semiconductor device with pillars used as device channels.
The ordinary artisan would have been motivated to modify M60 in combination with M83 in view of Anderson and M08 and M79 in the above manner for the motivation of optimally integrating the gate and first impurity region to optimize the available space as semiconductors continues to get scale down. Col 1 line 15 states, “The degree of integration of semiconductor integrated circuits, namely, integrated circuits using metal oxide semiconductor (MOS) transistors, has been increasing. The increasing degree of integration of such integrated circuits results in MOS transistors having small sizes reaching nano-scale dimensions.”
Re Claim 3 M83 in view of Anderson and M08 and M79 and M60 teaches the manufacturing method of a pillar-shaped semiconductor device according to claim 2,wherein a film thickness of the first mask material layer (M83, 34) is set smaller than twice as thick as the film thickness (measure thickness in vertical direction as shown in figure below) of the gate insulating layer (17).
M83 FIG. 3C fragment shown below with thickness shown of 17 and 34
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Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Masuoka (US 20100219483 A1) (M83 hereafter) in view of Anderson (US 20170179303 A1) and Masuoka (US 20150364608 A1) (M08 hereafter) and Masuoka (US 20170301679 A1) (M79 hereafter) and Noh (US 20200381436 A1).
Re Claim 4 M83 in view of Anderson and M08 and M79 teaches the manufacturing method of a pillar-shaped semiconductor device (M79, FIG. 2UA) according to claim 1, further comprising, after removing the first mask material layer that remains on the side wall of the semiconductor pillar by anisotropic etching (taught by M79 FIG. 2FB), using an ion implantation [M79, 0126] method to implant to the exposed upper surface of the first impurity region (49a), at least one of impurities of a conductivity type (N+) identical to a conductivity type (N+) of impurities in the first impurity region (49a, FIG. 2UB).
M83 in view of Anderson and M08 and M79 does not teach implanting oxygen ions.
Noh teaches implanting oxygen ions ([0042] states, “…the oxygen (O) ions may be implanted …”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Noh into the structure of M83 in view of Anderson and M08 and M79 since Noh teaches a semiconductor device and integrates an oxygen ion implantation method
The ordinary artisan would have been motivated to modify Noh in combination with M83 in view of Anderson and M08 and M79 in the above manner for the motivation of using a procedure of implanting oxygen ions to help a device function at peak levels and precisely control a threshold voltage. [0004] states, “The present inventive concept provides an integrated circuit device having a structure capable of precisely controlling a threshold voltage of a gate electrode and exhibiting enhanced reliability.”
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Masuoka (US 20100219483 A1) (M83 hereafter) in view of Anderson (US 20170179303 A1) and Masuoka (US 20150364608 A1) (M08 hereafter) and Masuoka (US 20170301679 A1) (M79 hereafter) and Noguchi (US 20160086804 A1).
Re Claim 5 M83 in view of Anderson and M08 and M79 teaches the manufacturing method of a pillar-shaped semiconductor device according to claim 1, but does not teach after forming the first insulation layer, using an ion implantation method to implant, below the first insulation layer, impurities of a conductivity type identical to a conductivity type of impurities in the first impurity region.
Noguchi teaches after forming the first insulation layer (4) [0052], using an ion implantation method to implant (17) [0016], below the first insulation layer (4), impurities of a conductivity type (P-type) [0059] identical to a conductivity type of impurities in the first impurity region (7, FIG. 6).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Noguchi into the structure of M83 in view of Anderson and M08 and M79 since Noguchi teaches a semiconductor device and integrates an ion implantation method
The ordinary artisan would have been motivated to modify Noh in combination with M83 in view of Anderson and M08 and M79 in the above manner for the motivation of optimally implanting ions to build a semiconductor device that stably maintain prescribed electrical properties. [0017] states, “…at least one aspect of the present invention aims at providing a method of manufacturing a semiconductor device that can stably maintain prescribed electrical properties.”
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Masuoka (US 20100219483 A1) (M83 hereafter) in view of Anderson (US 20170179303 A1) and Masuoka (US 20150364608 A1) (M08 hereafter) and Masuoka (US 20170301679 A1) (M79 hereafter) and Yasuda (JP 2015015423 A).
Re Claim 6 M83 in view of Anderson and M08 and M79 teaches the manufacturing method of a pillar-shaped semiconductor device according to claim 1, further comprising, after removing the first mask material layer by anisotropic etching, but does not teach forming a semiconductor layer on the exposed upper surface of the first impurity region by selective epitaxial growth, wherein forming the first insulation layer comprises forming the first insulation layer on the exposed upper surface of the first impurity region by thermally or chemically oxidizing the semiconductor layer.
Yasuda teaches forming a semiconductor layer (20, page 7 par 2, “epitaxial silicon layer”) on the exposed upper surface of the first impurity region (41) by selective epitaxial growth, wherein forming the first insulation layer comprises forming the first insulation layer (use formed silicon oxide film) on the exposed upper surface of the first impurity region by thermally or chemically oxidizing the semiconductor layer (page 11 last par states, “in FIG. 11, the surface of the epitaxial silicon layer 20 and the semiconductor substrate 2 is wet-oxidized using a thermal oxidation method, and a liner film is formed on the inner wall of the element isolation trench 69 as a film thickness of, for example, about 10 nm. A silicon oxide film is formed.”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Yasuda into the structure of M83 in view of Anderson and M08 and M79 since Yasuda teaches a semiconductor device and integrates an epitaxial growth process directly on an impurity region.
The ordinary artisan would have been motivated to modify Yasuda in combination with M83 in view of Anderson and M08 and M79 in the above manner for the motivation of forming an epitaxial semiconductor layer over the impurity region to help the device reduce variation in threshold voltage. Page 4 par 5 states, “A technique for reducing variation in threshold voltage by forming an epitaxial silicon layer on a high concentration impurity layer is known.”
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Masuoka (US 20100219483 A1) (M83 hereafter) in view of Anderson (US 20170179303 A1) and Masuoka (US 20150364608 A1) (M08 hereafter) and Masuoka (US 20170301679 A1) (M79 hereafter) and Yasuda (JP 2015015423 A) and Yoshizawa (US 20150244289 A1).
Re Claim 7 M83 in view of Anderson and M08 and M79 and Yasuda teaches the manufacturing method of a pillar-shaped semiconductor device according to claim 6, but does not teach an oxide film growth rate of the thermal or chemical oxidation of the semiconductor layer is greater than an oxide film growth rate of the thermal or chemical oxidation of the first impurity region.
an oxide film growth rate of the thermal or chemical oxidation of the semiconductor layer is greater than an oxide film growth rate of the thermal or chemical oxidation of the first impurity region.
Yoshizawa teaches an oxide film growth rate of the thermal or chemical oxidation of the semiconductor layer (26) is greater than an oxide film growth rate of the thermal or chemical oxidation of the first impurity region (46) ([0079] states. “…conditions for thermal oxidation for forming the first oxide film 46 and the conditions for thermal oxidation for forming the second oxide film 26 are the same, the growth rate (oxidation rate) of the first oxide film 46 is lower…”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Yoshizawa into the structure of M83 in view of Anderson and M08 and M79 and Yasuda since Yoshizawa teaches a semiconductor device with controlling oxidation rates.
The ordinary artisan would have been motivated to modify Yoshizawa in combination with M83 in view of Anderson and M08 and M79 and Yasuda in the above manner for the motivation of controlling oxidation rates in the semiconductor device to help increase yield. [0008] states, “An advantage of some aspects of the invention is to provide a vibrator that has a high sensitivity, does not easily cause sticking and can be manufactured in a high yield…”
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Masuoka (US 20100219483 A1) (M83 hereafter) in view of Anderson (US 20170179303 A1) and Masuoka (US 20150364608 A1) (M08 hereafter) and Masuoka (US 20170301679 A1) (M79 hereafter) and Yasuda (JP 2015015423 A) and Kim (US 20190157452 A1).
Re Claim 8 M83 in view of Anderson and M08 and M79 and Yasuda teaches the manufacturing method of a pillar-shaped semiconductor device according to claim 6, but does not teach forming the semiconductor layer comprises doping the semiconductor layer during epitaxial growth with impurities of a conductivity type identical to impurities in the first impurity region.
Kim teaches forming the semiconductor layer (145) [0027] comprises doping the semiconductor layer (145) during epitaxial growth with impurities of a conductivity type identical ([0027] states “…semiconductor layers 145 may be doped with impurities of the same conductivity type as the lower regions 111 and the impurity region 106.”) to impurities in the first impurity region (FIG. 15).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Kim into the structure of M83 in view of Anderson and M08 and M79 and Yasuda since Kim teaches a semiconductor device and conductivity types used for doping.
The ordinary artisan would have been motivated to modify Kim in combination with M83 in view of Anderson and M08 and M79 and Yasuda in the above manner for the motivation of matching the impurity region and semiconductor layers to have the same doping conductivity type to help the device function optimally and suppress a short channel effect. [0003] states, Multigate field effect transistors (FET) have an active pattern with a fin or nanowire shape, capable of suppressing a short channel effect…”
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Masuoka (US 20100219483 A1) (M83 hereafter) in view of Anderson (US 20170179303 A1) and Masuoka (US 20150364608 A1) (M08 hereafter) and Masuoka (US 20170301679 A1) (M79 hereafter) and Yasuda (JP 2015015423 A) and Bedell (US 20150287740 A1).
Re Claim 9 M83 in view of Anderson and M08 and M79 and Yasuda teaches the manufacturing method of a pillar-shaped semiconductor device according to claim 6, but does not teach after forming the semiconductor layer, using an ion implantation method to implant, to the semiconductor layer, at least one of oxygen ions and impurities of a conductivity type identical to a conductivity type of impurities in the first impurity region.
Bedell teaches after forming the semiconductor layer (55) [0086], using an ion implantation method ([0086] “The well regions 65a, 65b may be formed in the semiconductor layer 55 using ion implantation. For example, the well regions 65a, 65b may be formed by ion implantation of an n-type dopant…”) to implant, to the semiconductor layer, at least one of oxygen ions [0044] and impurities of a conductivity type identical to a conductivity type of impurities in the first impurity region (6a, [0051] “The source and drain regions 6a, 6b are typically formed by ion implantation of n-type or p-type dopants”, FIG. 10B).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Bedell into the structure of M83 in view of Anderson and M08 and M79 and Yasuda since Bedell teaches a semiconductor device and conductivity types used for doping.
The ordinary artisan would have been motivated to modify Bedell in combination with M83 in view of Anderson and M08 and M79 and Yasuda in the above manner for the motivation of doping the semiconductor layer with the same impurity type as the first impurity region to help optimize the transistor performance. [0004] states, “However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFET performance and consequently the overall performance of the complementary metal oxide semiconductor (CMOS) circuits through continued scaling, methods for improving performance without scaling have become critical.”
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Masuoka (US 20100219483 A1) (M83 hereafter) in view of Anderson (US 20170179303 A1) and Masuoka (US 20150364608 A1) (M08 hereafter) and Masuoka (US 20170301679 A1) (M79 hereafter) and Yasuda (JP 2015015423 A) and Xu (US 9343358 B1).
Re Claim 10 M83 in view of Anderson and M08 and M79 and Yasuda teaches the manufacturing method of a pillar-shaped semiconductor device according to claim 6, but does not teach a film thickness of the semiconductor layer is set such that, after forming the semiconductor layer, the first insulation layer with a desired film thickness can be formed by performing thermal or chemical oxidation which enables the semiconductor layer to be changed to an oxide film.
Xu teaches a film thickness of the semiconductor layer (22F, col 7 line 6) is set such that the first insulation layer (24, col 7 line 37, FIG. 3) with a desired film thickness can be formed by performing thermal oxidation (col 7 line 6) which enables the semiconductor (22F) layer to be changed to an oxide film (col 7 line 6 states, “…thermal oxidation process can be employed to convert the semiconductor material layers (22F, 22B) into the dielectric oxide layers (24, 26)…”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Xu into the structure of M83 in view of Anderson and M08 and M79 and Yasuda since Xu teaches using a thermal oxidation process on a semiconductor layer.
The ordinary artisan would have been motivated to modify Xu in combination with M83 in view of Anderson and M08 and M79 and Yasuda in the above manner for the motivation of using a thermal oxidation process to convert a semiconductor layer to an insulating layer to help optimize the stress in the device to ensure optimal performance. Col 1 line 49 states, “The first and second electrically conductive layers apply a first type stress to the substrate. The dielectric oxide layer applies a second type stress to the substrate.”
Response to Arguments
Applicant’s arguments with respect to claims 1-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH MARK SIPLING/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 2/26/26