Prosecution Insights
Last updated: April 19, 2026
Application No. 18/333,000

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Jun 12, 2023
Examiner
FLECK, LINDA JOAN
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK Hynix Inc.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
3y 7m
To Grant
96%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
41 granted / 53 resolved
+9.4% vs TC avg
Strong +19% interview lift
Without
With
+18.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
9 currently pending
Career history
62
Total Applications
across all art units

Statute-Specific Performance

§103
50.8%
+10.8% vs TC avg
§102
30.6%
-9.4% vs TC avg
§112
16.8%
-23.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 53 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, INCLUDING FORMING POLYMER MASK ON A STACK, AND ETCHING USING THE POLYMER MASK TO FORM A SECOND STEPPED STRUCTURE Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 1-8 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Izawa et al. US 20180224740 A1, hereafter Izawa in view of Atasoy et al., US 20150079351 A1, hereafter Atasoy. Regarding claim 1, Izawa discloses : A manufacturing method of a semiconductor device, the manufacturing method comprising: forming a stack including first material layers and second material layers that are alternately stacked (Izawa, Figure 1A, stacked body TA, formed of insulation layers 2 of silicon nitride film and layers 3 of silicon oxide film); forming, on the stack, an polymer mask including a first stepped structure (Izawa, Figure 1C, and [0019] discloses that the imprint pattern 5 is cured while the template TP is pressed against the imprint pattern 5, [0016] discloses that imprint material 4 is a ultraviolet curable resin or a thermoset resin, and [0013] discloses that the template includes steps); and forming a second stepped structure in the stack by etching the stack using the polymer mask as an etching barrier (Izawa, Figure 2A-2B, and [0021]-[0022] discloses that the imprint pattern is used to etch the steps into the stack). Izawa fails to disclose: inorganic material-containing Atasoy discloses: inorganic material-containing (Atasoy, [0092] discloses a resist compound containing dipentaerythritol pentaacrylate, dipentaerythritol hexaacrylate (monomers), . . . or blends thereof, the resist also comprises nanoparticles of ZnO, TiO2, ZrO2, SnO2, AlO, and the resist is disclosed as useable for an etch mask [0091]) It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Atasoy to the process of Izawa and to therefore have used the resist of Atasoy in the process of Izawa because Atasoy discloses that the use of a resist containing oxide nanoparticles as an etch mask [0091] and when used as a mask it has an increased scratch resistance over a mask without such particles, such resistance would increase the etch resistance of the mask, the composition also facilitates the demolding and reduces defects in the nanoscale [0037], and [0064]-[0065]. Regarding claim 2, the combination of Izawa and Atasoy as applied to claim 1 disclose: The manufacturing method of claim 1, wherein the forming of the polymer mask comprises: applying inorganic material-containing resist on the stack (Izawa, Figures 1A and [0016] discloses putting imprint material 4 on the stack, Atasoy, [0092] discloses a resist compound containing dipentaerythritol pentaacrylate, dipentaerythritol hexaacrylate (monomers), . . . or blends thereof, the resist also comprises nanoparticles of ZnO, TiO2, ZrO2, SnO2, AlO, and the resist is disclosed as useable for an etch mask [0091]); pressing the resist with a mold including a reversed stepped structure (Izawa, Figure 1C, and [0019] discloses the use of a template TP to shape the imprint material 4); and curing the resist (Izawa, Figure 1C, and [0019] discloses curing the imprint pattern). The combination of Izawa and Atasoy as applied to claim 1 fail to disclose the following composition for the mold: polymer Atasoy discloses: polymer (Atasoy, [0102] discloses the use their resist composition, a polymer when crosslinked, for a mold) It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Atasoy to use a polymer to mold the resin because Atasoy discloses that such a mold does not require the use of an anti-sticking layer to facilitate de-molding, and since an anti-sticking layer is a high cost factor in mass production [0009] not using one will reduce the cost of fabrication. Regarding claim 3, the combination of Izawa and Atasoy disclose: The manufacturing method of claim 2, wherein the curing of the resist comprises: forming a polymer by polymerizing monomers and inorganic nanoparticles (Atasoy, [0077] discloses the curing to cross link the material of the resist). Regarding claim 4, the combination of Izawa and Atasoy disclose: The manufacturing method of claim 3, wherein the monomer includes dipentaerythritol penta/hexaacrylate (DPHA) (Atasoy, [0092] discloses a resist containing dipentaerythritol pentaacrylate, dipentaerythritol hexaacrylate or blends thereof). Regarding claim 5, the combination of Izawa and Atasoy disclose: The manufacturing method of claim 1, wherein the inorganic material includes at least one of TiO2, Al2O3, ZrO2, Cr2O3, WO3, ZnO, SnO2, and Fe2O3 (Atasoy, [0097] discloses the resin contains suitable non-conductive nanoparticles and/or nanocrystals, preferably selected from the group consisting of oxides, TiO2, ZrO2, SnO2); Regarding claim 6, the combination of Izawa and Atasoy disclose: The manufacturing method of claim 1, wherein the polymer mask includes a material having a lower etching rate than the first material layers and the second material layers (Atasoy, [0145 discloses an etch rate of 1:10 with respect to the substrate, also since the composition of the mask in Atasoy is the same as the claimed composition the mask of Atasoy must have the same properties as the claimed mask. See MPEP 2112.01 II.). Regarding claim 7, the combination of Izawa and Atasoy disclose: The manufacturing method of claim 6, wherein the first material layers each include silicon nitride, the second material layers each include silicon oxide, and the inorganic material includes at least one of TiO2, Al2O3, and ZrO2 (Izawa, [0016] discloses material for the insulation layers 2 may be a silicon nitride film, for example. The material for the insulation layers 3 may be a silicon oxide film, and Atasoy, [00907] discloses the resin contains suitable non-conductive nanoparticles and/or nanocrystals, preferably selected from the group consisting of oxides, TiO2, ZrO2). Regarding claim 8, the combination of Izawa and Atasoy disclose: The manufacturing method of claim 1, wherein the polymer mask includes metal (Atasoy, [0097] discloses the resin contains suitable non-conductive nanoparticles and/or nanocrystals, preferably selected from the group consisting of oxides, TiO2, ZrO2, SnO2 these compounds contain metals, Atasoy further discloses that the resist, which when crosslinked is a polymer, can include metals [0096]). Regarding claim 12: The manufacturing method of claim 1, wherein a first step height of the first stepped structure and a second step height of the second stepped structure are identical to each other or different from each other (when you have two items with heights the heights can either be equal to or not equal to each other), and a first width of the first stepped structure and a second width of the second stepped structure are substantially identical to each other (Atasoy, [0021] and [0022] and Figure 2A-2B show that imprint pattern is used as a mask to etch the steps, therefore the mask determines the width of the etched step, and the step of the first step structure and of the second step structure would inherently be substantially the same). Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Izawa and Atasoy as applied to claim 1 above, and further in view of Koh et al., US 20150093897 A1, hereafter Koh. Regarding claim 9, Izawa and Atasoy fail to disclose: The manufacturing method of claim 1, the first stepped structure is reproduced in the stack to form the second stepped structure (Izawa, Figure 2A-2B, and [0021]-[0022] discloses that the imprint pattern is used to etch the steps into the stack) Izawa and Atasoy fail to disclose: wherein, the polymer mask is etched when the stack is etched Koh discloses the following: wherein, the polymer mask is etched when the stack is etched (Koh, Figures 10-11, and [0057] discloses that the stair patterns are simultaneously formed on the substrate by dry etching, in this interpretation “when” is interpreted as simultaneously) It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the application to have etched the polymer mask and the stack at the same time, doing so would decrease the time and complexity by reducing the number of etchants and etch steps when fabricating the devices. Regarding claim 10, Izawa and Atasoy fail to disclose: The manufacturing method of claim 1, wherein a first step height of the first stepped structure and a second step height of the second stepped structure are substantially identical to each other. Koh discloses : Koh, Figures 10-11, and [0057] discloses that the stair patterns are simultaneously formed on the substrate by dry etching. It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the application to have etched the polymer mask and the stack at the same time, doing so would decrease the time and complexity by reducing the number of etchants and etch steps when fabricating the devices. In the method of Izawa, Atasoy, and Koh the ratio of the etch rate of the polymer of first stepped structure to the material of the stack will determine the height of the steps of first stepped structure necessary to form the desired height of the second stepped structure. In the instant claims having a first stepped structure height and the second step structure height being substantially the same is equivalent to have a ration ratio of the etch rate of the polymer of first stepped structure to the material of the stack equal to one. Atasoy discloses that the etch rate of the mask to the material being etched can be 1:1 or extended to 1:10 (Atasoy, [0093]). When the etch rate of the polymer of first stepped structure is equal to the etch rate of the material of the stack the steps of the first stepped structure will be the same as the steps of the second stepped structure. Regarding claim 11, Izawa and Atasoy fail to disclose: The manufacturing method of claim 1, wherein a first step height of the first stepped structure and a second step height of the second stepped structure are different from each other. Koh discloses : Koh, Figures 10-11, and [0057] discloses that the stair patterns are simultaneously formed on the substrate by dry etching. It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the application to have etched the polymer mask and the stack at the same time, doing so would decrease the time and complexity by reducing the number of etchants and etch steps when fabricating the devices. In the method of Izawa, Atasoy, and Koh the ratio of the etch rate of the polymer of first stepped structure to the material of the stack will determine the height of the steps of first stepped structure necessary to form the desired height of the second stepped structure. In the instant claims having a first stepped structure height and the second step structure height being substantially the same is equivalent to have a ration ratio of the etch rate of the polymer of first stepped structure to the material of the stack equal to one. Atasoy discloses that the etch rate of the mask to the material being etched can be 1:1 or extended to 1:10 (Atasoy, [0093]). When the etch rate of the polymer of first stepped structure is one tenth of the etch rate of the material of the stack the steps of the first stepped structure will be less than the thickness of the steps of the second stepped structure. Claim 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over Izawa et al. US 20180224740 A1, hereafter Izawa in view Atasoy et al., US 20150079351 A1, hereafter Atasoy. Regarding claim 13, Izawa discloses the following limitations: A manufacturing method of a semiconductor device, the manufacturing method comprising: forming a stack (Figure 1A, stacked body TA, formed of insulation layers 2 of silicon nitride film and layers 3 of silicon oxide film); applying, on the stack, resist (Figure 1A, imprint material 4); pressing the resist with a mold including a reversed target structure (Figure 1B-1D, template TP, is pressed onto the imprint material 4 to form imprint pattern 5, which has a reversed structure as compared to template TP); forming a mask including a first target structure (Figure 1C, and [0019] discloses that the imprint pattern 5 is cured while the template TP is pressed against the imprint pattern 5, and [0016] discloses that imprint material 4 is a ultraviolet curable resin or a thermoset resin, and [0021] show the imprint pattern used as a mask); removing the mold (Figure 1D, template TP is removed from imprint pattern 5); and etching the mask and the stack to form a second target structure in the stack (Figure 2A-2B, and [0022] Next, as illustrated in FIG. 2B, the processes illustrated in FIGS. 1D and 2A are repeatedly performed on the individual stairs to form the steps C1 corresponding in numbers to the steps B1 in the imprint pattern 5 on the stacked body TA), wherein the first target structure is substantially reproduced to form the second target structure in the stack (Shown in Figure 2A and 2B, where steps C1 are substantially similar to those of the imprint pattern 5). Izawa fails to disclose the following limitations: (resist) including monomers and inorganic nanoparticles Polymer (mold) an inorganic material-containing polymer (mask) by polymerizing the monomers and the inorganic nanoparticles Atasoy discloses the following limitations: (resist) including monomers and inorganic nanoparticles (Atasoy, [0092] discloses a resist compound containing dipentaerythritol pentaacrylate, dipentaerythritol hexaacrylate (monomers), . . . or blends thereof, the resist also comprises nanoparticles of ZnO, TiO2, ZrO2, SnO2, AlO, and the resist is disclosed as useable for an etch mask [0091]) polymer (mold) (Atasoy, [0102] discloses the use their resist composition, a polymer when crosslinked, for a mold) an inorganic material-containing polymer (mask) (Atasoy, [0092] discloses a resist compound containing dipentaerythritol pentaacrylate, dipentaerythritol hexaacrylate, . . . or blends thereof, the resist also comprises nanoparticles of ZnO, TiO2, ZrO2, SnO2, AlO, [0129] discloses that the resist is cross linked (and therefore forms a polymer), and the resist is disclosed as useable for an etch mask [0091]) by polymerizing the monomers and the inorganic nanoparticles (Atasoy, [0077] discloses the curing to cross link the material of the resist) It would have been obvious to one of ordinary skill in the art at the time of the effective filing date to have applied the teachings of Atasoy to the method of Izawa and to therefore use a resist containing monomers and inorganic nanoparticles, which when cured cross link to form a polymer because Atasoy discloses Atasoy discloses that the use of a resist containing oxide nanoparticles as an etch mask [0091] and when used as a mask it has an increased scratch resistance over a mask without such particles, such resistance would increase the etch resistance of the mask, the composition also facilitates the demolding and reduces defects in the nanoscale [0037], and [0064]-[0065]. It would have further been obvious to have used a polymer mold to shape the resist because Atasoy discloses that his composition can be used to mold the resin because and that such a mold does not require the use of an anti-sticking layer to facilitate de-molding, and since an anti-sticking layer is a high cost factor in mass production [0009] not using one will reduce the cost of fabrication. Regarding claim 14, the combination of Izawa and Atasoy disclose the following limitations: The manufacturing method of claim 13, wherein the stack includes first material layers and second material layers that are alternately stacked (Izawa, Figure 1A, [0016] stacked body TA, formed of insulation layers 2 of silicon nitride film and layers 3 of silicon oxide film), the first material layers each include silicon nitride ([0016] insulation layers 2, of silicon nitride), the second material layers each include silicon oxide ([0016] insulation layers 3, of silicon oxide), and the inorganic material includes at least one of TiO2, Al2O3, and ZrO2 (Atasoy, [0092] discloses nanoparticles of ZnO, TiO2, ZrO2, SnO2, AlO [0091]). Regarding claim 15, the combination of Izawa and Atasoy disclose the following limitations: The manufacturing method of claim 13, wherein the polymer mask includes metal (Atasoy, [0097] discloses the resin contains suitable non-conductive nanoparticles and/or nanocrystals, preferably selected from the group consisting of oxides, TiO2, ZrO2, SnO2 these compounds contain metals, Atasoy further discloses that the resist, which when crosslinked is a polymer, can include metals [0096]). Regarding claim 16, the combination of Izawa and Atasoy disclose the following limitations: The manufacturing method of claim 13, wherein the inorganic material includes at least one of TiO2, Al2O3, ZrO2, Cr2O3, WO3, ZnO, SnO2, and Fe2O3 (Atasoy, [0097] discloses the resin contains suitable non-conductive nanoparticles and/or nanocrystals, preferably selected from the group consisting of oxides, TiO2, ZrO2, SnO2). Regarding claim 17, the combination of Izawa and Atasoy disclose the following limitations: The manufacturing method of claim 13, wherein a first height of the first target structure and a second height of the second target structure are identical to each other or different from each other (when you have two items with heights the heights can either be equal to or not equal to each other), and a first width of the first target structure and a second width of the second target structure are substantially identical to each other (Atasoy, [0021] and [0022] and Figure 2A-2B show that imprint pattern is used as a mask to etch the steps, therefore the mask determines the width of the etched step, and the step of the first step structure and of the second step structure would inherently be substantially the same). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Muramoto et al., US 20160214282 A1, discloses etching using a mask of dipentaerythritol penta/hexaacrylate and oxide particles such as SiO2 , TiO2 , ZrO2 , SnO2, and Al2O3. Konno et al., US 20220334475 A1, discloses forming a mask of DPHA and titania or zirconia by imprinting and using the mask for etching. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LINDA J FLECK whose telephone number is (703)756-1253. The examiner can normally be reached 7:30-4:30 ET, first Friday off. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William (Blake) Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LINDA J. FLECK/ Examiner, Art Unit 2812 /William B Partridge/ Supervisory Patent Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Jun 12, 2023
Application Filed
Jan 24, 2026
Non-Final Rejection — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
96%
With Interview (+18.9%)
3y 7m
Median Time to Grant
Low
PTA Risk
Based on 53 resolved cases by this examiner. Grant probability derived from career allow rate.

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