Prosecution Insights
Last updated: May 29, 2026
Application No. 18/333,033

SEMICONDUCTOR DEVICE

Final Rejection §102§103
Filed
Jun 12, 2023
Priority
Jul 25, 2022 — JP 2022-117867
Examiner
NIELSEN, DEREK LANG
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Renesas Electronics Corporation
OA Round
2 (Final)
67%
Grant Probability
Favorable
3-4
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
36 granted / 54 resolved
-1.3% vs TC avg
Strong +49% interview lift
Without
With
+48.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
15 currently pending
Career history
78
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
92.7%
+52.7% vs TC avg
§102
4.5%
-35.5% vs TC avg
§112
2.2%
-37.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 54 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION This Office Action is in response to the Amendment and Request for Reconsideration filed December 30, 2025. Applicant’s amendments to claims 1 and 3 have been entered. Claims 2 and 5-12 have been canceled. Claims 1, 3 and 4 are currently pending. Response to Amendment The amendments to the claims filed December 30, 2025 have been entered. Applicant’s amendments to the claims have failed to overcome each and every rejection set forth in the Non-Final Office Action filed October 1, 2025. Response to Arguments Applicant's arguments filed December 30, 2025 with respect to the rejection(s) of claim(s) 1, 3 and 4 under 35 U.S.C. 103 have been fully considered and are persuasive in view of Applicant’s amendments. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Qiao et al., US 2019/0019751 A1 (hereinafter Qiao). Applicant’s arguments on pages 6-7 with respect to the rejections of claims 1, 3, and 4 as being unpatentable over Ko in view of Iyer have been fully considered but are moot because they do not apply to the references as applied in the current Office Action. Note that the rejection no longer relies on Iyer for the teaching of a thickness of the first layer in the first portion of the fuse body is smaller than a thickness of the first layer in the second portion. In response to Applicant’s argument on page 7 that the dependent claims are patentably distinct over the prior art, and are also allowable based at least on their dependency from the independent claim 1, as amended, see the rejections of the claims below. Claim Rejections - 35 USC § 102 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim 2 was rejected in the previous Office Action under 35 U.S.C. 102(a)(1) as being anticipated by Ko et al., US 2007/0252237 A1 (hereinafter Ko). Applicant canceled claim 2 in the amendment filed December 30, 2025, therefore the rejection is moot and has been withdrawn. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Ko et al., US 2007/0252237 A1 (hereinafter Ko) in view of Qiao et al., US 2019/0019751 A1 (hereinafter Qiao). Regarding claim 1, as currently amended, Ko teaches: A semiconductor device comprising: a semiconductor substrate having a main surface (Ko, integrated fuse 20 formed on upper surface of semiconductor substrate, described but not shown, [0030]); and an electric fuse (Ko, FIGs. 2A-2C, integrated fuse 20, [0019]) including a fuse body, the fuse body being formed on the main surface (Ko, FIGs. 2A-2C, integrated fuse 20 including conductive layer 21 and polysilicon layer 22 formed on upper surface of semiconductor substrate, [0019; 0030]), having a width and extending in one direction (Ko, FIGs. 2A-2C, width WF and length LF, [0021-0022]), wherein the fuse body includes: a first layer (Ko, FIGs. 2A-2C, polysilicon layer 22, [0020-0021]) having a first melting point (Applicant’s specification states melting point of silicon is 1414° C); a second layer laminated in contact with the first layer (Ko, FIGs. 2A-2C, conductive layer 21, made of cobalt silicide, [0022; 0024]) and having a second melting point higher than the first melting point (Applicant’s specification states melting point of cobalt is about 1495° C); a first portion to be cut as the electric fuse (Ko, FIGs. 2B, 2C, polysilicon fuse link region 25, including reduced thickness region 21B of conductive layer 21, [0020-0028]), the first portion having a first thickness (Ko, FIG. 2C shows the first thickness of the first portion as the height from the lower surface of polysilicon layer 22 [the first layer] to the upper surface of reduced thickness region 21B of conductive layer 21 [the second layer], [0023]); and a second portion connected to the first portion and having a second thickness (Ko, FIG. 2C shows the second portion as the region of integrated fuse 20 [the fuse body] to the right of polysilicon fuse link region 25 [the first portion], including portion 21A of conductive layer 21 [the second layer] and anode 24 of polysilicon layer 22 [the first layer], indicated as having thickness T, [0023]), wherein the first thickness of the first portion corresponding to a height from a lower surface of the first layer to an upper surface of the second layer is smaller than the second thickness of the second portion corresponding to a height from the lower surface of the first layer to the upper surface of the second layer (Ko, FIG. 2C shows the first thickness of the first portion, the height from the lower surface of polysilicon layer 22 [the first layer] to an upper surface of reduced thickness region 21B of conductive layer 21 [an upper surface of the second layer], is smaller than thickness T [the second thickness of the second portion corresponding to a height from the lower surface of the first layer to the upper surface of the second layer], [0020-0028]), Ko is silent regarding: wherein a thickness of the first layer in the first portion of the fuse body is smaller than a thickness of the first layer in the second portion. However, Qiao, in the same field of endeavor, teaches a metal silicide / polysilicon fuse wherein a thickness of the first layer in the first portion of the fuse body is smaller than a thickness of the first layer in the second portion (Qiao, FIG. 5 shows upper surface of polysilicon melt layer [the first layer] reduced in height in the center region of the fuse body [the first portion of the fuse body], resulting in a polysilicon melt layer thickness in the center region of the fuse body that is smaller than the thickness of the polysilicon melt layer shown in the region to the right of the fuse body [the thickness of the first layer in the second portion]; “a recessed opening is formed on the upper surface of the polysilicon melt layer,” [0056]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ko with the teachings of Qiao, arriving at Applicant’s claimed thickness of the first layer in the first portion of the fuse body is smaller than a thickness of the first layer in the second portion with predictable results and without undue experimentation. The motivation for doing so would be, as recognized by Qiao, to control the blowing time of the polysilicon melt while reducing the particles of the polysilicon melt ejected during the blowing, thereby improving device performance and reliability. Regarding claim 3, Ko in view of Qiao teaches: The semiconductor device according to claim 1, wherein the first layer is a polysilicon film, and wherein the second layer is a metal silicide film (Ko, FIGs. 4A-4B, “the conductive layer (21) [the second layer] is a silicide layer that is formed on the polysilicon layer (22) [the polysilicon film],” [0024]; Qiao, [0061]). Regarding claim 4, Ko in view of Qiao teaches: The semiconductor device according to claim 3, wherein the metal silicide film includes a cobalt silicide film (Ko, FIG. 2C, “silicide layer (21) [the metal silicide film] can include … cobalt silicide,” [0024]). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEREK NIELSEN whose telephone number is (703)756-1266. The examiner can normally be reached Monday - Friday, 8:30 A.M. - 5:30 P.M.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DALE E PAGE can be reached at (571) 270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /D.L.N./Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Jun 12, 2023
Application Filed
Oct 01, 2025
Non-Final Rejection mailed — §102, §103
Dec 30, 2025
Response Filed
Apr 01, 2026
Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
67%
Grant Probability
99%
With Interview (+48.6%)
3y 7m (~7m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 54 resolved cases by this examiner. Grant probability derived from career allowance rate.

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