9DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election with traverse of Species II and A directed to Fig. 6 (claims 1-4, 6-10, 11-15 and 16-20) in the reply filed on August 28th, 2025 is acknowledged. The traversal is on the ground(s) that there would be no undue search and examination burden all Species I to III and A to B. This is not found persuasive because these Species have differences in structure and configurations as stated in the Examiners’ restriction requirement and these differences requires different field of search including different keyword search and different search queries which would create burden on the Examiner.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 9 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ahn et al. (Pub. No.: US 2017/0352666 A1), hereinafter as Ahn.
Regarding claim 1, Ahn discloses a method of manufacturing an integrated circuit device in Figs. 4, 6A, 7, and 19A-19E, the method comprising: forming a plurality of lower electrodes (plurality of lower electrodes 162A) above a substrate (substrate 102) (see Figs. 6A, 7, 19A-19C and [0086], [0105-0106], [0195], [0201]); forming a supporter (supporting member 180) configured to support the plurality of lower electrodes (see Fig. 19A-19C and [0197-0201]); forming a dielectric film (combination of layer 172, 164 and 174) on the plurality of lower electrodes and the supporter (see Figs. 7, 19E and [0103], [0106], [0205]); and forming an upper electrode (upper electrode 166A) on the dielectric film (see Fig. 7 and [0106-0107], [0206]), wherein the dielectric film includes a lower leakage current prevention layer (layer 172 being same as layer 52 being metal oxide) on an outer surface of each of the plurality of lower electrodes and an outer surface of the supporter (see Figs. 7, 19E and [0050], [0103]), a first capacitor material layer (layer 32 of layer 30C) on the lower leakage current prevention layer (layer 164 in Fig. 7 being the same as layer 30C in Fig. 4), an upper material layer (layer 34 of layer 30C) on the first capacitor material layer, and a second capacitor material layer (layer 174 being same as layer 54) on the upper material layer (see Figs. 4, 7, 19E and [0050], [0078], [0103], [0106]).
Regarding claim 9, Ahn discloses the method of claim 1, wherein the first capacitor material layer is thicker than the second capacitor material layer (layer 32 is thicker than layer 174/54) (see Figs. 1, 4 and [0038-0039], [0050], [0078-0079]).
Regarding claim 16, Ahn discloses a method of manufacturing an integrated circuit device in Figs. 4, 6A, 7, and 18A-18C, 19A-19E, the method comprising: the method comprising: forming an isolation film (isolation layer 104) on a substrate (substrate 102) (see Fig. 18A and [0172-0173], [0195-0196]), the isolation film defining an active region (active region 106) of the substrate (see Fig. 18A and [0173]); forming a gate structure (gate structure 120) on the substrate, the gate structure crossing the active region and extending in a first direction (X-direction) (see Figs. 6A, 18A and [0092], [0174]); forming a source/drain (source/drain regions 109A/109B) in the active region, the source/drain respectively at opposite sides of the gate structure (see Fig. 6A, 18A and [0174]); forming a bit line structure (bit line structure 130) on the substrate, the bit line structure extending in a second direction (Y-direction), the second direction being perpendicular to the first direction (see Figs. 6A, 18B and [0097], [0181]); forming a plurality of contact structures (plurality of contact structures 146) on the source/drain, respectively (see Fig. 18C and [0183]); forming a plurality of lower electrodes (plurality of lower electrodes 162A) on the plurality of contact structures (see Figs. 6A, 7, 19A-19C and [0086], [0105-0106], [0195], [0201]); forming a supporter (supporting member 180) configured to support the plurality of lower electrodes (see Fig. 19A-19C and [0197-0201]); forming a dielectric film (combination of layers 172, 164 and 174) on the plurality of lower electrodes and the supporter (see Figs. 7, 19E and [0103], [0106], [0205]); and forming an upper electrode (upper electrode 166A) on the dielectric film (see Fig. 7 and [0106-0107], [0206]), wherein the dielectric film includes a lower leakage current prevention layer (layer 172 being same as layer 52 being metal oxide) on an outer surface of each of the plurality of lower electrodes and an outer surface of the supporter (see Figs. 7, 19E and [0050], [0103]), a first capacitor material layer (layer 32 of layer 30C) on the lower leakage current prevention layer (layer 164 in Fig. 7 being the same as layer 30C in Fig. 4), an upper material layer (layer 34 of layer 30C) on the first capacitor material layer, and a second capacitor material layer (layer 174 being same as layer 54) on the upper material layer (see Figs. 4, 7, 19E and [0050], [0078], [0103], [0106]).
Claims 1-2, 6 and 10-11 and are rejected under 35 U.S.C. 102(a)(2) as being anticipated by KANG (Pub. No.: US 2021/0359082 A1).
Regarding claim 1, KANG discloses a method of manufacturing an integrated circuit device in Figs. 6C and 21-22B, 23A-23B, the method comprising: forming a plurality of lower electrodes (plurality of bottom electrodes 601) above a substrate (substrate 501) (see Figs. 21-22A, 23A-23B and [0242-0245], [0253-0256]); forming a supporter (support 600s) configured to support the plurality of lower electrodes (see Fig. 23B and [0256]); forming a dielectric film (multi-layer stack 603 being same as stack ML16B of Fig. 6C) on the plurality of lower electrodes and the supporter (see Figs. 23A-23B and [0254], [0257]); and forming an upper electrode (top electrode 602) on the dielectric film (see Figs. 23A-23B and [0256]), wherein the dielectric film (multi-layer stack 603/ML16B) includes a lower leakage current prevention layer (layer HBG) on an outer surface of each of the plurality of lower electrodes and an outer surface of the supporter (indirectly on bottom electrodes 601 and support 600s) (see Figs. 6C, 23A-23B and [0124-0125], [0131]), a first capacitor material layer (layer HK3) on the lower leakage current prevention layer (see Fig. 6C and [0124-0125], [0131]), an upper material layer (layer AFE2) on the first capacitor material layer (see Fig. 6C and [0131]), a second capacitor material layer (layer HK4) on the upper material layer (see Fig. 6C and [0131]).
Regarding claim 2, KANG discloses the method of claim 1, wherein the lower leakage current prevention layer includes a dielectric material doped with impurities, and the impurities include at least one of aluminum (Al) (layer HBG being Al doped zirconium oxide) (see Figs. 6C, 23A-23B and [0131], [0254-0256]).
Regarding claim 10, KANG discloses the method of claim 1, wherein the lower leakage current prevention layer is configured to reduce leakage current flowing between the plurality of lower electrodes neighboring each other (layer HBG is made of dielectric material of Zirconium oxide being doped with Aluminum can perform the same function as the current prevention layer to reduce the leakage current flowing between bottom electrodes 601) (see Figs. 6C, 23B and [0131-0132]).
Regarding claim 11, KANG discloses a method of manufacturing an integrated circuit device in Figs. 6C and 21-22B, 23A-23B, the method comprising: forming a plurality of lower electrodes (plurality of bottom electrodes 601) above a substrate (substrate 501) (see Figs. 21-22A, 23A-23B and [0242-0245], [0253-0256]); forming a supporter (support 600s) configured to support the plurality of lower electrodes (see Fig. 23B and [0256]); forming a dielectric film (multi-layer stack 603 being same as stack ML16B of Fig. 6C) on the plurality of lower electrodes and the supporter (see Figs. 23A-23B and [0254], [0257]); and forming an upper electrode (top electrode 602) on the dielectric film (see Figs. 23A-23B and [0256]), wherein the dielectric film (multi-layer stack 603/ML16B) includes a lower leakage current prevention layer (layer HBG) on an outer surface of each of the plurality of lower electrodes and an outer surface of the supporter (indirectly on bottom electrodes 601 and support 600s) (see Figs. 6C, 23A-23B and [0124-0125], [0129], [0131]), a first capacitor material layer (layer HK3) on the lower leakage current prevention layer (see Fig. 6C and [0124-0125], [0131]), an upper material layer (layer AFE2) on the first capacitor material layer (see Fig. 6C and [0131]), a second capacitor material layer (layer HK4) on the upper material layer (see Fig. 6C and [0131]), and an upper leakage current prevention layer (layer LBL) on the second capacitor material layer (see Fig. 6C and [0131]).
Note: the following rejection of claim 1 based on different interpretation of the dielectric film for rejecting claim 6.
Regarding claim 1, KANG discloses a method of manufacturing an integrated circuit device in Figs. 6B and 21-22B, 23A-23B, the method comprising: forming a plurality of lower electrodes (plurality of bottom electrodes 601) above a substrate (substrate 501) (see Figs. 21-22A, 23A-23B and [0242-0245], [0253-0256]); forming a supporter (support 600s) configured to support the plurality of lower electrodes (see Fig. 23B and [0256]); forming a dielectric film (multi-layer stack 603 being same as stack ML16A of Fig. 6B) on the plurality of lower electrodes and the supporter (see Figs. 23A-23B and [0254], [0257]); and forming an upper electrode (top electrode 602) on the dielectric film (see Figs. 23A-23B and [0256]), wherein the dielectric film (multi-layer stack 603/ML16A) includes a lower leakage current prevention layer (layer AFE1 being AFE-HZO) on an outer surface of each of the plurality of lower electrodes and an outer surface of the supporter (indirectly on bottom electrodes 601 and support 600s) (see Figs. 6B, 23A-23B and [0124-0125], [0129]), a first capacitor material layer (layer HK2 being ZrO2) on the lower leakage current prevention layer (see Fig. 6B and [0124-0125], [0129]), an upper material layer (layer HBG being Al2O3) on the first capacitor material layer (see Fig. 6B and [0129]), a second capacitor material layer (layer HK3 being ZrO2) on the upper material layer (see Fig. 6B and [0129]).
Regarding claim 6, KANG discloses the method of claim 1, wherein the first capacitor material layer and the second capacitor material layer include zirconium oxide (ZrO2) (both layers HK2 and HK3 includes ZrO2), and the upper material layer includes aluminum oxide (Al2O3) (layer HBG includes Al2O3) (see Fig. 6B and [0129]).
Allowable Subject Matter
Claims 3, 4, 7-8, 12-15, and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to disclose or suggest the claimed invention having:
wherein the forming the lower leakage current prevention layer includes alternately performing a first atomic layer deposition process and a second atomic layer deposition process, the first atomic layer deposition process includes a cycle of supplying and purging a dielectric film precursor, supplying and purging an impurity precursor, and supplying and purging a reactant, and the second atomic layer deposition process includes a cycle of supplying and purging the dielectric film precursor and supplying and purging the reactant as recited in claim 3.
Further comprising: forming a lower doped layer on the supporter and the plurality of lower electrodes, wherein the lower doped layer is formed between the lower leakage current prevention layer and the supporter, the lower doped layer is formed between the lower leakage current prevention layer and the plurality of lower electrodes, and the lower doped layer includes titanium oxide (TiO2) doped with a group V element as an impurity as recited in claim 7.
Wherein the lower leakage current prevention layer and the upper leakage current prevention layer each include a dielectric material doped with impurities, and the impurities include at least one of aluminum (Al), silicon (Si), magnesium (Mg), calcium (Ca), cobalt (Co), yttrium (Y), tantalum (Ta), niobium (Nb), hafnium (Hf), zirconium (Zr), and molybdenum (Mo) as recited in claim 12.
Further comprising: forming a lower doped layer on the supporter and the plurality of lower electrodes, wherein the lower doped layer is formed between the lower leakage current prevention layer and the supporter, the lower doped layer is formed between the lower leakage current prevention layer and the plurality of lower electrodes, and the lower doped layer includes titanium oxide (TiO2) doped with a group V element as an impurity as recited in claim 13.
Wherein the lower leakage current prevention layer and the upper leakage current prevention layer are each formed by alternately performing a first atomic layer deposition process and a second atomic layer deposition process, the first atomic layer deposition process includes a cycle of supplying and purging a dielectric film precursor, supplying and purging an impurity precursor, and supplying and purging a reactant, and the second atomic layer deposition process includes a cycle of supplying and purging the dielectric film precursor and supplying and purging the reactant as recited in claim 15.
Further comprising: forming a titanium oxide thin film on the supporter and the plurality of lower electrodes, wherein the titanium oxide thin film is formed between the lower leakage current prevention layer and the supporter, the titanium oxide thin film is formed between the lower leakage current prevention layer and the plurality of lower electrodes, the titanium oxide thin film is doped with a group V element as an impurity, and the dielectric film further includes an upper leakage current prevention layer on the second capacitor material layer as recited in claim 17.
Claims 4, 8, 14 and 18-20 depend on claims 3, 7, 13, and 17 and therefore also include said claimed limitation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818