DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20130017629 (Pyo et al) in view of US 20150325587 (Chen) and US 20210183771 (Lee et al).
Concerning claim 1, Pyo discloses a semiconductor device comprising (Fig. 14): a supporter (10). . .; a gate structure (175) comprising gate lines that are stacked on the supporter, wherein the gate lines comprise pads (note that conductive layers 175 are used as gate structures and the ends of the gate structures are considered a pad that is later used as the connection point for subsequently formed contact plugs), respectively; first contact plugs (183) that are connected to the pads, respectively; and channel structures (140) that extend through the gate structure (Fig. 14).
Pyo does not disclose that the supporter is formed comprising a plurality of stairs or the pads are disposed over the plurality of stairs, wherein the pads are disposed over an upper surface of the gate structure, and the pads extend along the upper surface of the gate structure. However, Chen discloses a 3D memory device (analogous to the memory device of Pyo) in which a support structure (400) is formed (Fig.9) and gate structures ([0063]) are formed over the supporter structure ([0053]). Chen discloses that in conventional art with interlayer connections there can arise as the number of layers increases, because not only does the number of etch steps increase even using binary system etch approaches, but also the depths of the required vias increase. With greater depths, the layout area for each interlayer connector can increase and process control issues arise. Thus it is desirable to provide a technology that can improve the reliability and reduce the costs of manufacturing for interlayer connectors in multilayer integrated circuits such as 3D memory which the supporter structure does ([0011]-[0013]). The invention of Pyo discloses interlayer connections (181 and 183) that controls the depths of the vias (Fig. 14) and therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the support structure (10) of Pyo with the support structure (400) of Chen in order to improve the reliability and reduce the costs of manufacturing for interlayer connectors in multilayer integrated circuits such as 3D memory.
Additionally, Lee discloses a vertical memory device (Fig. 1, analogous to the memory device of Pyo) in which gate structures comprising gate lines (104b) are formed in an alternating stack with insulating layers (102b) over a substrate (100) and pads (114) are disposed over an upper surface of the gate structure, and the pads extend along the upper surface of the gate structure with the contact plugs extending through the pads (which are part of the gate structure). Lee discloses that utilization of such configuration allows for a punching defect of the contact plug to be decreased ([0148]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention of Pyo in view of Chen an Lee in order to provide a structure in which pads are disposed over an upper surface of the gate structure, and the pads extend along the upper surface of the gate structure to decrease a punching defect of the contact plug.
Continuing to claim 2, Pyo in view of Chen and Lee discloses wherein the pads correspond to the plurality of stairs (Lee Fig. 1).
Considering claim 3, Pyo in view of Chen and Lee discloses wherein a number of the pads are is the same as a number of the plurality of stairs (Lee Fig. 1).
Referring to claim 4, Pyo in view of Chen and Lee discloses wherein upper surfaces of the pads are disposed at a level substantially the same as a level of upper surfaces of the channel structures (Pyo Fig. 14).
Regarding claim 5, Pyo in view of Chen and Lee discloses wherein heights of the first contact plugs are substantially the same with each other (Pyo Fig. 14 and [0130]).
Pertaining to claim 6, Pyo in view of Chen and Lee discloses further comprising second contact plugs (181) that are connected to the channel structures, respectively (Pyo Fig. 14 and [0130]).
As to claim 7, Pyo in view of Chen and Lee discloses wherein the first contact plugs have a height that is substantially the same as a height of the second contact plugs (Pyo Fig. 14 and [0130]).
Concerning claim 8, Pyo in view of Chen and Lee discloses wherein the supporter comprises one of an insulating material, a conductive material, and a combination of the insulating material and the conductive material (Chen [0053]).
Continuing to claim 9, Pyo in view of Chen and Lee discloses wherein the supporter is a part of a substrate (Chen Fig. 9 and [0053]), and wherein the gate structure is disposed over the substrate (Lee Fig. 1).
Considering claim 10, Pyo discloses a semiconductor device comprising (Fig. 20F): a first supporter (10). . .; a second supporter (305) disposed over the first supporter and . . .; a first gate structure (370 lower set) comprising first gate lines that are stacked over the first supporter (Fig. 20F and [0168]-[0171]), wherein the first gate lines comprise first pads (note that conductive layers 370 are used as gate structures and the ends of the gate structures are considered a pad that is later used as the connection point for subsequently formed contact plugs), respectively, and the first pads are disposed over the first stairs (Fig. 20F), respectively; a second gate structure comprising second gate lines that are stacked over the second supporter, wherein the second gate lines (370 upper set) comprise second pads (note that conductive layers 370 are used as gate structures and the ends of the gate structures are considered a pad that is later used as the connection point for subsequently formed contact plugs), respectively, . . . (Fig. 20F), respectively; first contact plugs (183) that extend through the second gate structure and that are connected to the first pads (Fig. 20F note that contact plug connected to the first gate structure and first gate pad comprises two portions, one that is located in the support structure 305 and another portion that is located above the support structure and that the examiner is interpreting the contact plug portion that is formed within the support structure 305 as the first contact plug), respectively; and second contact plugs (183) that are connected to the second pads, respectively (Fig. 20F).
Pyo does not disclose that the first and second supporter is formed comprising a plurality of stairs or the first and second pads are disposed over the plurality of stairs, wherein the first pads are disposed over an upper surface of the first gate structure, and the first pads extend along the upper surface of the first gate structure and wherein the second pads are disposed over an upper surface of the second gate structure, and the second pads extend along the upper surface of the second gate structure. However, Chen discloses a 3D memory device (analogous to the memory device of Pyo) in which a support structure (400) is formed (Fig.9) and gate structures ([0063]) are formed over the supporter structure ([0053]). Chen discloses that in conventional art with interlayer connections there can arise as the number of layers increases, because not only does the number of etch steps increase even using binary system etch approaches, but also the depths of the required vias increase. With greater depths, the layout area for each interlayer connector can increase and process control issues arise. Thus it is desirable to provide a technology that can improve the reliability and reduce the costs of manufacturing for interlayer connectors in multilayer integrated circuits such as 3D memory which the supporter structure does ([0011]-[0013]). The invention of Pyo discloses interlayer connections (181 and 183) that controls the depths of the vias (Fig. 14) and therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify each of the support structures (10 +305) of Pyo with the support structure (400) of Chen in order to improve the reliability and reduce the costs of manufacturing for interlayer connectors in multilayer integrated circuits such as 3D memory.
Additionally, Lee discloses a vertical memory device (Fig. 1, analogous to the memory device of Pyo) in which gate structures comprising gate lines (104b) are formed in an alternating stack with insulating layers (102b) over a substrate (100) and pads (114) are disposed over an upper surface of the gate structure, and the pads extend along the upper surface of the gate structure with the contact plugs extending through the pads (which are part of the gate structure). Lee discloses that utilization of such configuration allows for a punching defect of the contact plug to be decreased ([0148]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention of Pyo in view of Chen an Lee in order to provide a structure in which pads (both first and second pads) are disposed over an upper surface of the gate structure (both first and second gate structures), and the pads extend along the upper surface of the gate structure to decrease a punching defect of the contact plug.
Referring to claim 11, Pyo in view of Chen and Lee discloses further comprising third contact plugs that are connected to the first contact plugs, respectively (Pyo Fig. 20F, note that contact plug connected to the first gate structure and first gate pad comprises two portions one that is located in the support structure 305 and another portion that is located above the support structure and that the examiner is interpreting the contact plug portion that is formed above support structure 305 as the third contact plug).
Regarding claim 12, Pyo in view of Chen and Lee discloses further comprising channel structures (Pyo 140+350) that extend through the second gate structure and the first gate structure (Pyo Fig. 20F).
Pertaining to claim 13, Pyo in view of Chen discloses further comprising fourth contact plugs (Pyo 181) that are connected to the channel structures, respectively (Pyo Fig. 20F).
As to claim 14, Pyo in view of Chen discloses wherein the second contact plugs, the third contact plugs, and the fourth contact plugs have substantially a same height (Pyo Fig. 20F).
According to claim 15, Pyo in view of Chen discloses wherein the first contact plugs are disposed between the second pads and the channel structures (Pyo Fig. 20F, note that the channel structures comprise an upper portion 350 and a lower portion and that the second pads are located at the top of the second channel portion 350. Therefore the first contact plugs are located positionally between the lower portion of the channel structure and the second pads).
Concerning claim 16, Pyo in view of Chen discloses wherein the first pads are disposed substantially at a same level (Pyo Fig. 14 and Lee Fig. 1 note that conductive layers 370 are used as gate structures and the modification of Pyo to incorporate the gate pads over the gate structures for subsequent contact plug connection in the configuration of Lee yields the configuration where the pads are at the same level).
Continuing to claim 17, Pyo in view of Chen discloses wherein the second pads are disposed substantially at a same level (Pyo Fig. 14 and Lee Fig. 1 note that conductive layers 370 are used as gate structures and the modification of Pyo to incorporate the gate pads over the gate structures for subsequent contact plug connection in the configuration of Lee yields the configuration where the pads are at the same level).
Considering claim 18, Pyo in view of Chen discloses wherein the first supporter and the second supporter comprises one of an insulating material, a conductive material, and a combination of the insulating material and the conductive material (Chen [0053]).
Referring to claim 19, Pyo in view of Chen discloses wherein the first supporter is a part of a substrate (Chen Fig. 9 and [0053]) and wherein the first gate structure is disposed over the substrate (Lee Fig. 1).
Regarding claim 20, Pyo in view of Chen and Lee discloses wherein the first pads correspond to the plurality of first stairs, wherein the second pads correspond to the plurality of second stairs, wherein a number of the first pads is the same as a number of first stairs in the plurality of first stairs, and wherein a number of the second pads is the same as a number of second stairs in the plurality of second stairs (Chen Fig. 9 and Lee Fig. 1, note that the configuration in which the pads are formed along an upper surface of the gate structure seen in Lee is the same for both the first and second gate structures of the aforementioned modified configuration ).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VALERIE N NEWTON/ Examiner, Art Unit 2897 04/02/26
/CHAD M DICKE/ Supervisory Patent Examiner, Art Unit 2897
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