DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment dated January 2, 2026, in which claims 1-3, 11, and 15-18 were amended, has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-14 and 16-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (U.S. Pub. 2020/0152569).
Regarding claims 1-10, Lee [Figs.9-13] discloses a semiconductor device, comprising:
an interconnect [113a-c] including:
a bottom interconnect section [section below center narrow region of via 113a and 113b] having a first orientation along a Y-axis and comprising a first interconnect portion [113b] and a second interconnect portion [section below center narrow region of via 113a], wherein the second interconnect portion is in direct contact with the first interconnect portion and extends upward from the first interconnect portion along the Y-axis [Fig.13A] [Note that 113b makes direct contact with the bottom of 113a]; and
a top interconnect section [section above center narrow region of via 113a, and 113c] coupled to the bottom interconnect section and having a second orientation along to the Y-axis, wherein the second orientation of the top interconnect section is a vertical reflection of the first orientation of the bottom interconnect section and comprising a third interconnect portion [section above center narrow region of via 113a] and a fourth interconnect portion [113c], wherein the fourth interconnect portion is in direct contact with the third interconnect portion and extends upward from the third interconnect portion along the Y-axis [Fig.13A] [Note that 113c makes direct contact with the top of 113a];
wherein the second interconnect portion of the bottom interconnect section comprises:
a first wider region;
a first narrower region located above the first wider region; and
a first pair of tapered sidewalls that connects the first wider region and the first narrower region [section below center narrow region of via 113a and above 113b];
wherein the third interconnect portion of the top interconnect section comprises:
a second narrower region;
a second wider region located above the second narrower region; and
a second pair of tapered sidewalls that connects the second wider region and the second narrower region [section above center narrow region of via 113a and below 113c] [Fig.13A];
wherein the first pair of tapered sidewalls tapers up from the first wider region of the second interconnect portion towards a center line defined by the bottom interconnect section to define the first narrower region of the second interconnect portion, and wherein the second pair of tapered sidewalls tapers down from the second wider region of the third interconnect portion towards the center line to define the second narrower region of the third interconnect portion [Via 113a; Fig.11A];
wherein the first pair of tapered sidewalls of the second interconnect portion and the second pair of tapered sidewalls of the third interconnect portion includes opposing orientations relative to each other along the Y-axis [Via 113a; Fig.11A];
further comprises:
an intersection [center line of 113a] formed by the second narrower region of the third interconnect portion and the first narrower region of the second interconnect portion, wherein the intersection joins the top interconnect section and the bottom interconnect section to form a continuous structure [Via 113a; Fig.11A];
wherein the first interconnect portion [113b] extends a first width [width at the upper surface of 113b] parallel to an X-axis, and wherein the first wider region of the second interconnect portion extends perpendicularly from the first interconnect portion on opposite sides of a center line defined by the bottom interconnect section to define a second width [width at the wider portion of bottom section of 113a] parallel to the X-axis, wherein the first width is less than the second width [Fig.13A];
wherein the second width [width at the wider portion of bottom section of 113a] of the first wider region tapers up to the first narrower region [center line of 113a] of the second interconnect portion, wherein the first narrower region extends a third width [width of the via at the center line of 113a] parallel to the X-axis, and wherein the second width of the first wider region is greater than the third width of the first narrower region [Figs.11A,13A];
wherein the second wider region of the third interconnect portion extends a fourth width parallel to the X-axis and tapers down to the second narrower region of the third interconnect portion, wherein the second narrower region extends a fifth width parallel to the X-axis, and wherein the fourth width is greater than the fifth width [Top section of 113a] [Figs.11A,13A];
wherein the fourth width of the second wider region of the third interconnect portion and the second width of the first wider region of the second interconnect portion include a same width [widths at opposite wider portions of 133a] parallel to the X-axis [Figs.11A,13A].
Regarding claims 11-14, Lee [Figs.9-13] discloses a semiconductor device, comprising:
an interconnect [113a-c] including:
a first interconnect portion [113b] extending along a Y-axis;
a second interconnect portion [bottom section of 113a] in direct contact with the first interconnect portion extending upwards from the first interconnect portion along the Y-axis and including a first tapered profile [Fig.13A] [Note that 113b makes direct contact with the bottom of 113a];
a third interconnect portion [top section of 113a] extending upwards from the second interconnect portion along the Y-axis and including a second tapered profile having an opposing orientation relative to the first tapered profile of the second interconnect portion; and
a fourth interconnect portion [113c] in direct contact with the third interconnect portion extending upwards from the third interconnect portion along the Y-axis [Figs.11A,13A] [Note that 113c makes direct contact with the top of 113a];
wherein the first tapered profile of the second interconnect portion and the second tapered profile of the third interconnect portion forms a hyperboloid line profile along the Y-axis [Via 113a] [Figs.11A];
wherein the hyperboloid line profile includes a first locally widened critical dimension (CD) defined by a first wider region of the second interconnect portion and a second locally widened CD defined by a second wider region of the third interconnect portion, wherein the first locally widened CD includes the opposing orientation relative to the second locally widened CD [Via 113a] [Figs.11A];
wherein the first interconnect portion [113b] is located between first sections of a first dielectric layer [111c] [Fig.13A], the second interconnect portion and the third interconnect portion are located between second sections of a second dielectric layer [111a], and the fourth interconnect portion is located between third sections of a third dielectric layer [111b] [Fig.13A].
Regarding claims 16-20, Lee [Figs.9-13] discloses a semiconductor device, comprising:
a first interconnect [113a-c] including:
a bottom interconnect section including a first arrow-shaped profile extending along a Y-axis [section below center narrow region of via 113a and 113b] and comprising a first interconnect portion [113b] and a second interconnect portion [section below center narrow region of via 113a], wherein the second interconnect portion is in direct contact with the first interconnect portion and extends upward from the first interconnect portion along the Y-axis [Fig.13A] [Note that 113b makes direct contact with the bottom of 113a]; and
a top interconnect section including a second arrow-shaped profile extending along the Y-axis [section above center narrow region of via 113a and 113c] and comprising a third interconnect portion [section above center narrow region of via 113a] and a fourth interconnect portion [113c], wherein the fourth interconnect portion is in direct contact with the third interconnect portion and extends upward from the third interconnect portion along the Y-axis [Note that 113c makes direct contact with the top of 113a], wherein the second arrow-shaped profile includes an opposite orientation relative to the first arrow-shaped profile [Figs.11A,13A];
wherein the second interconnect portion of the bottom interconnect section comprises a first arrowhead portion of the first arrow-shaped profile and the first interconnect portion of the bottom interconnect section [via portion of 113b] comprises a first shaft portion of the first arrow-shaped profile [Figs.11A,13A];
wherein the third interconnect portion of the top interconnect section comprises a second arrowhead portion of the second arrow-shaped profile and the fourth interconnect portion of the top interconnect section [via portion of 113c] comprises a second shaft portion of the second arrow-shaped profile [Figs.11A,13A];
wherein the first arrowhead portion of the first arrow-shaped profile and the second arrowhead portion of the second arrow-shaped profile forms a hyperboloid line profile [113a] along the Y-axis [Figs.11A,13A];
further comprising a second interconnect [second 113a-c structure] [Figs.11A,13A], wherein the second interconnect and the first interconnect includes a uniform total interconnect height and a uniform line profile [Figs.11A,13A].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. Pub. 2020/0152569) in view of Heo et al. (U.S. Pub. 2020/0020638) [Hereafter “Heo”].
Regarding claim 15, Lee [Fig.13A] discloses a semiconductor device
wherein the first dielectric layer [111c] locating the first interconnect portion [113b] and the third dielectric layer [111b] locating the fourth interconnect portion [113c] comprise dielectric materials, and wherein the second dielectric layer [111a] comprises a same dielectric material along the second interconnect portion and the third interconnect portion [113a].
Lee fails to explicitly disclose wherein the first dielectric layer and the third dielectric layer comprise different dielectric materials. However, Heo [Fig.13] discloses a semiconductor device wherein the first dielectric layer [171] locating the first interconnect portion [173] and the third dielectric layer [160] locating the fourth interconnect portion [163] comprise different dielectric materials [Paras.82,84], and wherein the second dielectric layer [181] comprises a same dielectric material along the second interconnect portion and the third interconnect portion [183].
It would have been obvious to provide the dielectric materials as claimed, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Response to Arguments
Applicant's arguments filed January 2, 2026, have been fully considered but they are not persuasive. As noted above in the treatment of the claims, the interconnect portions 113b and 113c make direct contact with the bottom surface and top surface of via structure 113a, respectively. Consequently, Lee [Fig.13A] discloses the required limitations of the first interconnect portion is in direct contact with the second interconnect portion, and the third interconnect portion is in direct contact with the fourth interconnect portion.
Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made Final.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BAC H AU/Primary Examiner, Art Unit 2898
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