Office Action Predictor
Last updated: April 16, 2026
Application No. 18/333,679

SEMICONDUCTOR DEVICE

Final Rejection §112
Filed
Jun 13, 2023
Examiner
KIM, JAY C
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Wavepia Co., LTD.
OA Round
2 (Final)
48%
Grant Probability
Moderate
3-4
OA Rounds
3y 6m
To Grant
70%
With Interview

Examiner Intelligence

Grants 48% of resolved cases
48%
Career Allow Rate
412 granted / 849 resolved
-19.5% vs TC avg
Strong +22% interview lift
Without
With
+21.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
67 currently pending
Career history
916
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
39.1%
-0.9% vs TC avg
§102
19.5%
-20.5% vs TC avg
§112
39.6%
-0.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 849 resolved cases

Office Action

§112
DETAILED ACTION This Office Action is in response to Amendment filed November 20, 2025. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-3, 5, 6 and 8 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor, at the time the application was filed, had possession of the claimed invention. Regarding claim 1, Applicant did not originally disclose that “an inside of the at least one first through-via is fully filled with a conductive material” as recited on line 16, because (a) Applicant did not use the word “full”, “fully”, “complete” or “completely” in describing the at least one first through-via or the conductive material in the original disclosure, (b) therefore, Applicant did not originally disclose whether all the atoms constituting the sidewalls of the at least one first through-via are bonded to the atoms constituting the conductive material, or the volume of the inside of the at least one first through-via should be the same with the volume of the conductive material to satisfy the limitation recited on line 16, (c) as shown in Fig. 12 of Dhamdhere et al. (US 12,444,648), and as stated by Dhamdhere et al. on lines 3-6 of column 26, i.e. “The inventors have discovered that, even when grown by atomic layer deposition, ultrathin (e.g., <5 nm) TiN layers may not continuously cover the underlying surface and have discontinuities”, one of ordinary skill in the art understands that a vertical opening or a trench may not be fully filled with a material that is subsequently deposited into the vertical opening or trench, (d) Fig. 12 of Kim et al. (US 12,431,388) also shows a similar feature of less than full filling of a vertical opening or a trench, and (e) therefore, the limitation “an inside of the at least one first through-via is fully filled with a conductive material” as recited on line 16 fails to comply with the written description requirement. Claims 2, 3, 5, 6 and 8 depend on claim 1, and therefore, claims 2, 3, 5, 6 and 8 also fail to comply with the written description requirement. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-3, 5, 6 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. (1) Regarding claim 1, it is not clear what the limitation “at least one temperature sensor …having electrical properties changed according to a temperature of the at least one transistor (emphasis added)” recited on lines 8-9 suggests, because (a) in original claim 6, Applicant claimed “at least one temperature sensor …having electrical properties changed according to a temperature of the transistor (emphasis added)” or a temperature of a single transistor, (b) however, the limitation cited above can suggest that a single temperature sensor can have electrical properties changed according to a temperature of two or more transistors, and (c) in this case, it is not clear what “a temperature of the at least one transistor” refers to when the at least one transistor implies two or more transistors, and when the two or more transistors are not in thermal equilibrium. (2) Also regarding claim 1, it is not clear what the limitation “at least one second through-via configured to pass through the semiconductor substrate under the at least one temperature sensor (emphasis added)” recited on lines 10-11 suggests, because (a) in original claim 7, Applicant claimed “at least one second through-via configured to pass through the semiconductor substrate under the temperature sensor (emphasis added)” or a single temperature sensor, (b) however, the limitation cited above can suggest that a second through-via can be configured to pass through the semiconductor substrate under a plurality of temperature sensors, and (c) in this case, it is not clear whether the limitation cited above can suggest that the plurality of temperature sensors can share the second through-via, or the limitation cited above should be interpreted as each second through-via is disposed under one of the temperature sensors. (3) Further regarding claim 1, it is not clear what the limitation “an inside of the at least one first through-via is fully filled with a conductive material” recited on line 16 suggests, because (a) as discussed above under 35 USC 112(a) rejection, Applicant did not use the word “full”, “fully”, “complete” or “completely” in describing the at least one first through-via or the conductive material in the original disclosure, and (b) therefore, it is not clear whether the limitation cited above suggests whether all the atoms constituting the sidewalls of the at least one first through-via are bonded to the atoms constituting the conductive material, or the volume of the inside of the at least one first through-via should be the same with the volume of the conductive material to satisfy the limitation recited on line 16. (4) Still further regarding claim 1, it is not clear how the temperature sensor 170 in Fig. 2 of current application, 370 in Fig. 4 of current application and 570 in Fig. 6 of current application can function as a temperature sensor, because (a) Applicant discloses in paragraph [0080] of current application that “The temperature sensor 170 composed of a thermo-variable resistor may be made of one of various materials”, and that “The temperature sensor 170 may be a thin film resistor (TFR) and may be made of NiCr or TaN”, (b) however, the temperature sensor 170/370/570 are completely encapsulated by the active layer 130/330/530, the metal layer 180/380/580 and the underlying structure, (c) therefore, the temperature sensor formed of NiCr or TaN would be constrained by the surrounding active layer and metal layer, and thus its resistance may not be able to exhibit thermos-variability, or its resistance would at least be affected by the thermal expansion or contraction of the active layer and the metal layer, (d) in this case, the temperature sensor may not be able to function as a proper temperature sensor, and the correlation of its resistance with the temperature would also depend on surrounding material layers, and (e) furthermore, for the temperature sensor to function as a temperature sensor, the temperature sensor 170/370/570 should be electrically connected with at least two electrical terminals, and however, all the conductors and semiconductors shown in Figs. 2, 4 and 6 of current application appear to be shorted, and thus the alleged temperature sensor 170/370/570 formed of NiCr or TaN may not be able to function as a temperature sensor especially for the embodiment shown in Fig. 6 of current application where the top and bottom ends of the alleged temperature sensor 570 is shorted by the metal layer 580 electrically connected to the source electrode 545, which is electrically connected to the lower metal layer 510, which is in turn electrically connected to the alleged temperature sensor 570; please note that Applicant originally elected species shown in Fig. 6 of current application, because claim 9 recites a configuration of the embodiment shown in Fig. 6 of current application, i.e. “the metal layer is in contact with the source electrode”. Claims 2, 3, 5, 6 and 8 depend on claim 1, and therefore, claims 2, 3, 5, 6 and 8 are also indefinite. Response to Arguments Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAY C KIM/Primary Examiner, Art Unit 2815 /J.K./Primary Examiner, Art Unit 2815 January 22, 2026
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Prosecution Timeline

Jun 13, 2023
Application Filed
Aug 21, 2025
Non-Final Rejection — §112
Nov 20, 2025
Response Filed
Jan 22, 2026
Final Rejection — §112
Mar 05, 2026
Interview Requested
Mar 10, 2026
Applicant Interview (Telephonic)
Mar 10, 2026
Examiner Interview Summary

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
48%
Grant Probability
70%
With Interview (+21.9%)
3y 6m
Median Time to Grant
Moderate
PTA Risk
Based on 849 resolved cases by this examiner. Grant probability derived from career allow rate.

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