Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
The limitations of the claims are often able to refer to multiple things in the specification, while the specification fails to specify what from the claims are in the figures. As an example, the claims have “the first cell”, “the first electrode”, “the first source region”, “the first pin”, etc., however, it is no possible to draw a proper connection from the language of the claims to the figures and/or the specification without making guesses. Examination is still possible if the broadest reasonable interpretation is used, however, further prosecution may prove to be difficult as it may be difficult to bring in limitations or arguments from the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1-3, 6, 8, and 15 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In Claim 1, regarding the line “a third direction perpendicular to the first direction or the second direction,” does this mean that it can either be perpendicular to direction 1 or 2 but not both, meaning that the third direction can't be orthogonal to the plane that the first and second direction make? Examiner believes that this is not the intended limitation for the third direction the applicant is intending. Evidence for this can be seen when discussing via's in claim 3. There is mention of them having their longitudinal axis being in the third direction. In the figures the direction that the via’s make are orthogonal to the XY plane. Because a via is a structure that typically is used to traverse through layers it is typically perpendicular to the plane of a surface or substrate, a via is typically orthogonal/perpendicular to a plane. Examiner further uses this as evidence that the third direction is actually meant to be perpendicular to the first direction AND the second direction instead of only one or the other.
Similarly, claim 8 states “the pin having a longitudinal axis that is substantially perpendicular to the horizontal axis or the vertical axis.” For the same reasons as above, Examiner believes that the limitation is supposed to read “horizontal axis AND the vertical axis” as Examiner believes applicant is not trying to exclude having a orthogonal pin to the horizontal/vertical axis plane.
Similar again is Claim 15, where Examiner will treat the recited limitation of “third direction perpendicular to the first direction or the second direction,” as if it read “third direction perpendicular to the first direction AND the second direction.”
In an effort for compact prosecution, the limitations of claims 1, 8, and 15, as discussed above will be examined as stated, however, appropriate actions are still needed.
Claim 1 recites the limitations "a first portion", “a second portion” and “a third portion” in lines 6, 8, and 10. There is insufficient antecedent basis for this limitation in the claim. The first, second, and third portions had already been introduced previously. In an effort for compact prosecution, the claim will be examined as if the first portion, second portion, and third portion are the same in lines 6, 8, and 10 as their previously introduced counterparts in line 3. Regardless, appropriate action is necessary.
Claims 2, 3, and 6 us the word “another”, without properly referring to what the limitation is “another” from. For claim 2, “an additional electrically conductive structure connected to another one of the first electrode, the second electrode, and the third electrode,” it is unclear as to what the “another” would be referring to as all of the first electrode, the second electrode, and the third electrode are connected in their own right already. The “another” for claim 2 could be referring to a different electrode than the electrode that is connected to the electrically conductive structure, but it is still not explicitly clear. Claim 3 is similar in the limitation is probably referring to a different electrode than the electrode that is connected to the electrically conductive structure. For claims 2 and 3, the claims will be examined as if the “another” was “one of the first electrode, the second electrode, and the third electrode, different from the first electrode, the second electrode, and the third electrode that is connected to the electrically conductive structure”.
For claim 6, the use of “another” fails to describe the another is different from. Similar to above, and in an effort for compact prosecution, the claim will be examined as if it read “a fourth electrode over a different portion of the additional semiconductor structure in the third direction than the portion that the second electrode is over of the additional semiconductor structure in the third direction.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by United States Patent Application Publication by You et al. (US 20210305232 A1; You H).
Regarding Claim 1, You H discloses an integrated circuit (IC) device (Fig. 14, device in figure), comprising:
a semiconductor structure (CR1) having a longitudinal axis along a first direction (X), the semiconductor structure comprising a first portion (Space between AR1 and AR2 in CR1), a second portion (AR2), and a third portion (AR1),
wherein the first portion is between the second portion and the third portion in a second direction (Y) perpendicular to the first direction (Fig. 14, where the space between AR1 and AR2 is between them in the second [Y] direction);
a first electrode (I1b) over the first portion of the semiconductor structure in a third direction perpendicular to the first direction and (See above rejections for reasons of the change) the second direction (Fig. 14, Where electrode I1b is vertically [third direction] over the first portion [Space between AR1 and AR2 in CR1]) and;
a second electrode (CA14 or CW1) over the second portion of the semiconductor structure in the third direction (Fig. 14, Where electrode CA14 or CW1 is vertically [third direction] over the second portion AR2);
a third electrode (CA11) over the third portion of the semiconductor structure in the third direction (Fig. 14, Where electrode CA11 is vertically [third direction] over the third portion AR1); and
an electrically conductive structure (VA1 connected to CA11, or VB1 connected to second electrode CW1) connected to one of the first electrode, the second electrode, and the third electrode, wherein the electrically conductive structure has a longitudinal axis (Examiner notes that there is nothing inherently special about an axis being longitudinal, only that the axis is in the length direction. However, because there is no “length direction” defined, any axis may be considered the longitudinal axis, so long as the direction remains consistent in future limitations regarding direction of length) along the third direction (Fig. 12, where electrically conductive structure VA1 has a longitudinal access in the third [vertical] direction).
Regarding Claim 2, You H discloses the IC device according to claim 1, further comprising:
an additional electrically conductive (Para. 59, Via structure for CM16 electrode, also called VA1) structure connected to another one of the first electrode, the second electrode, and the third electrode,
wherein the additional electrically conductive structure has a longitudinal axis along the third direction (Because the VIA structure here is similar to electrically conductive structure VA1, it will similarly have a longitudinal axis).
Regarding Claim 3, You H discloses the IC device according to claim 1, further comprising:
a via (Fig. 14, VA1 with CA14) comprising a first end and a second end, the first end connected to another one of the first electrode, the second electrode, and the third electrode; and
an electrically conductive layer connected to the second end of the via (Para. 59, ”a first routing via VA1 which connects the sixth connection contact CM16 and the second power supply wiring V.sub.SS may be formed”).
Regarding Claim 4, You H discloses the IC device according to claim 1, further comprising:
an additional semiconductor structure (FR1 and/or CR2) substantially in parallel with the semiconductor structure (They are planar, making them substantially parallel. Furthermore, examiner notes that “substantially” is a term of degree where reasonable minds can disagree as to the metes and bounds of what would and would not be considered substantially parallel),
wherein the first electrode is over a portion of the additional semiconductor structure in the third direction (Fig. 14-17, The first electrode I1b overhangs the edge of the semiconductor cell CR1 in a manor such that at least a portion of the first electrode is over at least a portion of the semiconductor structure CR1 and the additional semiconductor structure FR1), and the electrically conductive structure is connected to the first electrode.
Regarding Claim 5, You H discloses the IC device according to claim 1, further comprising:
an additional semiconductor structure (FR1 and/or CR2) substantially in parallel with the semiconductor structure (They are planar, making them substantially parallel. Furthermore, examiner notes that “substantially” is a term of degree where reasonable minds can disagree as to the metes and bounds of what would and would not be considered substantially parallel),
wherein the second electrode (CW1) is over a portion of the additional semiconductor structure in the third direction (Fig. 14-18, where second electrode CW1 is vertically [third direction] over the second portion AR2 and additional semiconductor structure FR1), and the electrically conductive structure (VB1) is connected to the second electrode (Para. 69).
Regarding Claim 6, You H discloses the IC device according to claim 5, further comprising:
a fourth electrode (CW2) over another portion of the additional semiconductor structure (Fig. 15-17, where electrode 3 and 4 are over a different part of the additional semiconductor structure in the third direction),
wherein the fourth electrode is separated from the third electrode by an electrical insulator (Para. 123 where there is fourth interlayer insulating film 410 separating the electrodes).
Regarding Claim 7, You H discloses the IC device according to claim 1, wherein the semiconductor structure has a fin or nanoribbon (Para. 140).
Regarding Claim 8, You H discloses an integrated circuit (IC) device, comprising:
a first transistor comprising (Para. 33) a first source region (160 - within AR1, Para. 97), a first drain region (160 - within AR1, Para. 97), and a first channel region (Fig. 14, vertically underneath the upper portion of gate structure G1, Para 33), wherein the first source region is over the first drain region along a horizontal axis (X axis) of the IC device (Fig. 14, along the horizontal axis chose X, it is easy to construe that the first source region is over the first drain region depending on orientation of the device);
a second transistor (Para 33) over the first transistor along a vertical axis of the IC device, the second transistor comprising a second source region (260 - within AR1, Para. 97), a second drain region (260 - within AR1, Para. 97), and a second channel region (Fig. 14, vertically underneath the bottom portion of gate structure G1, Para 33);
a gate structure (G1) comprising a first portion (Fig. 14, upper half of G1 along Y axis) and a second portion (Fig. 14, lower half of G1 along Y axis), wherein the first portion is over the first channel region, and the second portion is over the second channel region (Fig. 14); and
a pin (IW1/IW2) connected to the gate structure, the pin having a longitudinal axis that is substantially perpendicular to the horizontal axis and the vertical axis.
Regarding Claim 9, You H discloses the IC device according to claim 8, wherein the pin is an input pin of the IC device (Para. 64-65, where IW1 and IW2 and routinely referred to as input wiring).
Regarding Claim 10, You H discloses the IC device according to claim 8, further comprising:
a trench electrode (DW1) comprising a third portion and a fourth portion, wherein the third portion is over the first source region or the first drain region, the fourth portion is over the second source region or the second drain region (Because trench electrode DW1 is made in the second routing level, both and/or all portions of the trench electrode will be over the first source region or the first drain region and over the second source region or the second drain region); and
an additional pin connected (VB1) to the trench electrode, the additional pin having a longitudinal axis that is substantially perpendicular to the horizontal axis or the vertical axis (Pin OW1 is rectangle in shape and any axis may be considered its longitudinal axis, where we can choose an axis to make the axis perpendicular to the horizontal axis or the vertical axis).
Regarding Claim 11, You H discloses the IC device according to claim 10, wherein the additional pin is an output pin of the IC device (Para. 63).
Regarding Claim 12, You H discloses the IC device according to claim 8, further comprising:
a trench electrode (CA11) over the first source region or the first drain region (Fig. 14);
a metal layer (Vdd – M1); and
an additional pin (VA1) having a longitudinal axis that is substantially perpendicular to the horizontal axis or the vertical axis (Pin VA1 is rectangle in shape and any axis may be considered its longitudinal axis, where we can choose an axis make it perpendicular to the horizontal axis or the vertical axis), the additional pin connected to the trench electrode and the metal layer (Para. 58, “first routing via VA1 which connects the first connection contact CM11 and the first power supply wiring V.sub.DD may be formed. Therefore, the first source/drain contact CA11 may be connected to the first power supply wiring V.sub.DD”).
Regarding Claim 13, You H discloses the IC device according to claim 12, wherein the metal layer is a power plane (As the metal layer is a power supply wiring and not simply metal traces, it would qualify as a power plane).
Regarding Claim 14, You H discloses the IC device according to claim 12, wherein:
the trench electrode is a first trench electrode (CA11),
the additional pin is a first additional pin (VA1, upper left VA1 in Fig. 14) and is connected to a first section of the metal layer (Vdd – M1), and
the IC device further comprises a second trench electrode (CA14) and a second additional pin (VA1, Still called VA1, however, this pin is the lower one connected to CA14 in Fig, 14), and
the second additional pin has a longitudinal axis that is substantially perpendicular to the horizontal axis or the vertical axis (Pin VA1 is rectangle in shape and any axis may be considered its longitudinal axis, where we can choose an axis make it perpendicular to the horizontal axis or the vertical axis) and is connected to the second trench electrode and a second section of the metal layer (Para. 59).
Regarding Claim 15, You H discloses an integrated circuit (IC) device, comprising:
a first cell (CR1) comprising:
a first electrode (CA14) over a first source region (160 - within AR2, Para. 97) or a first drain region (160 - within AR2, Para. 97) of a first transistor in a first direction (Y axis in Fig. 14), wherein the first source region is over the first drain region in a second direction perpendicular (Z axis in Fig 14) to the first direction (Para. 48, and Fig. 14, Where electrode CA14 is over the source/drain regions AR2 both in the first direction [Y labeled axis here] and the second direction [Z labeled axis]), and
a first pin (IW2) connected to the first electrode and having a longitudinal axis along the first direction (Para. 61, and Fig. 14); and
a second cell (CR2) comprising:
a second electrode (CA26) over a second source region (260 - within AR1, Para. 97) or a second drain region (260 - within AR1, Para. 97) of a second transistor in the first direction, wherein the second source region is over the second region in the second direction (Para. 161, and Fig. 14, Where electrode CA26 is over the source/drain regions AR1 both in the first direction [Y labeled axis here] and the second direction [Z labeled axis]), and
a second pin (OW3) connected to the second electrode and having a longitudinal axis along the first direction (Para. 161, and Fig. 14),
wherein the first pin is misaligned with the second pin in in a third direction perpendicular to the first direction
Regarding Claim 16, You H discloses the IC device according to claim 15, wherein the first pin or the second pin is an output pin (Para. 169-172, where OW3 is routinely referred to as input wiring).
Regarding Claim 17, You H discloses the IC device according to claim 15, wherein:
the first cell further comprises a third pin (IW1) having a longitudinal axis along the first direction (The axis of IW1 that is in the Y direction),
the second cell further comprises a fourth pin (IW3) having a longitudinal axis along the first direction (The axis of IW3 that is in the Y direction), and
the third pin and the fourth pin are aligned in the third direction (Fig. 14, where IW1 and IW3 are aligned in the third direction Y).
Regarding Claim 18, You H discloses the IC device according to claim 17, wherein:
the first cell further comprises a third electrode (G1) over a channel region of the first transistor (Fig. 14, where G1 is disposed in first cell CR1), and
the third pin is connected to the third electrode (Para. 42 and Fig. 14, where third electrode G1 is connected to third pin IW1).
Regarding Claim 19, You H discloses the IC device according to claim 18, wherein:
the second cell further comprises a fourth electrode (G3) over a channel region of the second transistor (Fig. 14, where G3 is disposed in first cell CR2), and
the fourth pin is connected to the fourth electrode (Para. 161 and Fig. 14, where fourth electrode G3 is connected to fourth pin IW3).
Regarding Claim 20, You H discloses the IC device according to claim 17, wherein the third pin or the fourth pin is an input pin (Para. 60-62 where IW1 is routinely referred to as being an input).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J HIBBERT whose telephone number is (703)756-1562. The examiner can normally be reached Monday - Friday 8am-5pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL J HIBBERT/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899