Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments made in Amendment
Applicant’s arguments, see page 8 of “Applicant Arguments/Remarks Made in an Amendment”, filed 05/18/2026, with respect to the specification objection have been fully considered and are persuasive. Examiner agrees with applicant that the specification should not be objected to and as such objection of the specification has been withdrawn.
Applicant’s arguments, see page 8 of “Applicant Arguments/Remarks Made in an Amendment”, filed 05/18/2026, with respect to 35 U.S.C. § 112(B) rejections of claims 1-3, 6, 8, and 15 have been fully considered and are persuasive. Regarding claims 1, applicant amended to resolve the antecedent issue regarding “a first/second/third portion” to now read “the first/second/third portion.” Further claims 1, 8, and 15, overcome the issue raised regarding the perpendicularity of the directions by amending out the line “third direction perpendicular to the first direction or the second direction.” Regarding claims 2 and 3, applicant argues that the use of “another” is not indefinite, and examiner agrees. Regarding claim 6, applicant amends the use of “another” to now read “a different,” which no longer renders the limitation indefinite. As such, the 35 U.S.C. § 112(B) rejections of claims 1-3, 6, 8, and 15 have been withdrawn.
Applicant's arguments, see pages 8 and 9 of “Applicant Arguments/Remarks Made in an Amendment”, filed 05/18/2026, with respect to 35 U.S.C. § 102(a)(1) have been fully considered but they are not persuasive.
In response to the argument that the new limitation of “an electrically conductive structure, wherein an access point on the electrically conductive structure is connected to one of the first electrode, the second electrode, and the third electrode” (underlined portion is new) is not disclosed by You because in You, the electrically conductive structure VA1 and/or VB1 fails to be connected to of the first electrode I1B, second electrode CA14/CW1, or third electrode CA11. Examiner disagrees with this analysis, at least in context of the claim language. The claim fails to require there needs to be direct contact, and instead that the electrically conductive structure is “connected.” Connect alone is very broad and includes when something is connected to something even with a third thing in-between. It also doesn’t restrict the type of connection, and as such includes structural connections, electrical connections, and the like. In You, it is clear that the electrically conductive structure VA1 connected to connection contact CM11 and third electrode CA11 is connected to connection contact CM11 (Para. 58, “In some embodiments, the first power supply wiring V.sub.DD may be connected to some of the source/drain contacts CA11 to CA16. For example, at least a part of the first connection contact CM11 may be placed to overlap the first power supply wiring V.sub.DD, and a first routing via VA1 which connects the first connection contact CM11 and the first power supply wiring V.sub.DD may be formed. Therefore, the first source/drain contact CA11 may be connected to the first power supply wiring V.sub.DD”). Therefore it is clear that, at least under the broadest reasonable interpretation using the current claim language, that electrically conductive structure is connected to at least third electrode CA11 by virtue of connection contact CM11 being connected to both.
In response to applicant's argument that You fails to disclose “wherein the electrically conductive structure is to receive a signal from a device; and a substrate”, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, 10-15, 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by United States Patent Application Publication by You et al. (US 20210305232 A1; You H).
Regarding Claim 1, You H discloses an integrated circuit (IC) device (Fig. 14, device in figure), comprising:
a semiconductor structure (CR1) having a longitudinal axis along a first direction (X), the semiconductor structure comprising a first portion (Space between AR1 and AR2 in CR1), a second portion (AR2), and a third portion (AR1),
wherein the first portion is between the second portion and the third portion in a second direction (Y) perpendicular to the first direction (Fig. 14, where the space between AR1 and AR2 is between them in the second [Y] direction);
a first electrode (I1b) over the first portion of the semiconductor structure in a third direction (Fig. 14, Where electrode I1b is vertically [third direction] over the first portion [Space between AR1 and AR2 in CR1]) and;
a second electrode (CA14 or CW1) over the second portion of the semiconductor structure in the third direction (Fig. 14, Where electrode CA14 or CW1 is vertically [third direction] over the second portion AR2);
a third electrode (CA11) over the third portion of the semiconductor structure in the third direction (Fig. 14, Where electrode CA11 is vertically [third direction] over the third portion AR1); and
an electrically conductive structure (VA1 connected to CA11, or VB1 connected to second electrode CW1), wherein an access point on the electrically conductive structure is connected to one of the first electrode, the second electrode, and the third electrode (Para. 58, “In some embodiments, the first power supply wiring V.sub.DD may be connected to some of the source/drain contacts CA11 to CA16. For example, at least a part of the first connection contact CM11 may be placed to overlap the first power supply wiring V.sub.DD, and a first routing via VA1 which connects the first connection contact CM11 and the first power supply wiring V.sub.DD may be formed. Therefore, the first source/drain contact CA11 may be connected to the first power supply wiring V.sub.DD. Therefore it is clear that, at least under the broadest reasonable interpretation using the current claim language, that electrically conductive structure is connected to at least third electrode CA11 by virtue of connection contact CM11 being connected to both), wherein the electrically conductive structure has a longitudinal axis (Examiner notes that there is nothing inherently special about an axis being longitudinal, only that the axis is in the length direction. However, because there is no “length direction” defined, any axis may be considered the longitudinal axis, so long as the direction remains consistent in future limitations regarding direction of length) along the third direction (Fig. 12, where electrically conductive structure VA1 has a longitudinal access in the third [vertical] direction),
wherein the first direction and the second direction are substantially parallel to a plane of the substrate, and wherein the third direction is substantially perpendicular to the plane of the substrate (First and second direction are x and Y directions from You which follow the direction of the substrate 100, and the Third direction follows the Z direction),
The Examiner notes that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. See, e.g., In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). See MPEP § 2114. The recitation of "wherein the electrically conductive structure is to receive a signal from a device; and a substrate " does not distinguish the present invention over the prior art of You who teaches the structure as claimed.
Regarding Claim 2, You H discloses the IC device according to claim 1, further comprising:
an additional electrically conductive (Para. 59, Via structure for CM16 electrode, also called VA1) structure connected to another one of the first electrode, the second electrode, and the third electrode,
wherein the additional electrically conductive structure has a longitudinal axis along the third direction (Because the VIA structure here is similar to electrically conductive structure VA1, it will similarly have a longitudinal axis).
Regarding Claim 3, You H discloses the IC device according to claim 1, further comprising:
a via (Fig. 14, VA1 with CA14) comprising a first end and a second end, the first end connected to another one of the first electrode, the second electrode, and the third electrode; and
an electrically conductive layer connected to the second end of the via (Para. 59, ”a first routing via VA1 which connects the sixth connection contact CM16 and the second power supply wiring V.sub.SS may be formed”).
Regarding Claim 4, You H discloses the IC device according to claim 1, further comprising:
an additional semiconductor structure (FR1 and/or CR2) substantially in parallel with the semiconductor structure (They are planar, making them substantially parallel. Furthermore, examiner notes that “substantially” is a term of degree where reasonable minds can disagree as to the metes and bounds of what would and would not be considered substantially parallel),
wherein the first electrode is over a portion of the additional semiconductor structure in the third direction (Fig. 14-17, The first electrode I1b overhangs the edge of the semiconductor cell CR1 in a manor such that at least a portion of the first electrode is over at least a portion of the semiconductor structure CR1 and the additional semiconductor structure FR1), and the electrically conductive structure is connected to the first electrode.
Regarding Claim 5, You H discloses the IC device according to claim 1, further comprising:
an additional semiconductor structure (FR1 and/or CR2) substantially in parallel with the semiconductor structure (They are planar, making them substantially parallel. Furthermore, examiner notes that “substantially” is a term of degree where reasonable minds can disagree as to the metes and bounds of what would and would not be considered substantially parallel),
wherein the second electrode (CW1) is over a portion of the additional semiconductor structure in the third direction (Fig. 14-18, where second electrode CW1 is vertically [third direction] over the second portion AR2 and additional semiconductor structure FR1), and the electrically conductive structure (VB1) is connected to the second electrode (Para. 69).
Regarding Claim 6, You H discloses the IC device according to claim 5, further comprising:
a fourth electrode (CW2) over a different portion of the additional semiconductor structure (Fig. 15-17, where electrode 3 and 4 are over a different part of the additional semiconductor structure in the third direction),
wherein the fourth electrode is separated from the third electrode by an electrical insulator (Para. 123 where there is fourth interlayer insulating film 410 separating the electrodes).
Regarding Claim 7, You H discloses the IC device according to claim 1, wherein the semiconductor structure has a fin or nanoribbon (Para. 140).
Regarding Claim 8, You H discloses an integrated circuit (IC) device, comprising:
a first transistor comprising (Para. 33) a first source region (160 - within AR1, Para. 97), a first drain region (160 - within AR1, Para. 97), and a first channel region (Fig. 14, vertically underneath the upper portion of gate structure G1, Para 33), wherein the first source region is over the first drain region along a horizontal axis (X axis) of the IC device (Fig. 14, along the horizontal axis chose X, it is easy to construe that the first source region is over the first drain region depending on orientation of the device);
a second transistor (Para 33) over the first transistor along a vertical axis of the IC device, the second transistor comprising a second source region (260 - within AR1, Para. 97), a second drain region (260 - within AR1, Para. 97), and a second channel region (Fig. 14, vertically underneath the bottom portion of gate structure G1, Para 33);
a gate structure (G1) comprising a first portion (Fig. 14, upper half of G1 along Y axis) and a second portion (Fig. 14, lower half of G1 along Y axis), wherein the first portion is over the first channel region, and the second portion is over the second channel region (Fig. 14); and
a pin (IW1/IW2) wherein an access point on the pin connected to the gate structure,
The Examiner notes that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. See, e.g., In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). See MPEP § 2114. The recitation of " and wherein the pin is to receive a signal from a device" does not distinguish the present invention over the prior art of You who teaches the structure as claimed,
and a substrate (100, Para 137),
wherein the horizontal axis and the vertical are substantially parallel to a plane of the substrate, and wherein a wherein a longitudinal axis of the pin is substantially perpendicular to the plane of the substrate (The horizontal axis and the vertical axis are understood to be the x and y directions in You and the longitudinal axis is the Z direction in You).
Regarding Claim 10, You H discloses the IC device according to claim 8, further comprising:
a trench electrode (DW1) comprising a third portion and a fourth portion, wherein the third portion is over the first source region or the first drain region, the fourth portion is over the second source region or the second drain region (Because trench electrode DW1 is made in the second routing level, both and/or all portions of the trench electrode will be over the first source region or the first drain region and over the second source region or the second drain region); and
an additional pin connected (VB1) to the trench electrode, the additional pin having a longitudinal axis that is substantially perpendicular to the horizontal axis or the vertical axis (Pin OW1 is rectangle in shape and any axis may be considered its longitudinal axis, where we can choose an axis to make the axis perpendicular to the horizontal axis or the vertical axis).
Regarding Claim 11, You H discloses the IC device according to claim 10, wherein the additional pin is an output pin of the IC device (Para. 63).
Regarding Claim 12, You H discloses the IC device according to claim 8, further comprising:
a trench electrode (CA11) over the first source region or the first drain region (Fig. 14);
a metal layer (Vdd – M1); and
an additional pin (VA1) having a longitudinal axis that is substantially perpendicular to the horizontal axis or the vertical axis (Pin VA1 is rectangle in shape and any axis may be considered its longitudinal axis, where we can choose an axis make it perpendicular to the horizontal axis or the vertical axis), the additional pin connected to the trench electrode and the metal layer (Para. 58, “first routing via VA1 which connects the first connection contact CM11 and the first power supply wiring V.sub.DD may be formed. Therefore, the first source/drain contact CA11 may be connected to the first power supply wiring V.sub.DD”).
Regarding Claim 13, You H discloses the IC device according to claim 12, wherein the metal layer is a power plane (As the metal layer is a power supply wiring and not simply metal traces, it would qualify as a power plane).
Regarding Claim 14, You H discloses the IC device according to claim 12, wherein:
the trench electrode is a first trench electrode (CA11),
the additional pin is a first additional pin (VA1, upper left VA1 in Fig. 14) and is connected to a first section of the metal layer (Vdd – M1), and
the IC device further comprises a second trench electrode (CA14) and a second additional pin (VA1, Still called VA1, however, this pin is the lower one connected to CA14 in Fig, 14), and
the second additional pin has a longitudinal axis that is substantially perpendicular to the horizontal axis or the vertical axis (Pin VA1 is rectangle in shape and any axis may be considered its longitudinal axis, where we can choose an axis make it perpendicular to the horizontal axis or the vertical axis) and is connected to the second trench electrode and a second section of the metal layer (Para. 59).
Regarding Claim 15, You H discloses an integrated circuit (IC) device, comprising:
a first cell (CR1) comprising:
a first electrode (CA14) over a first source region (160 - within AR2, Para. 97) or a first drain region (160 - within AR2, Para. 97) of a first transistor in a first direction (Y axis in Fig. 14), wherein the first source region is over the first drain region in a second direction perpendicular (Z axis in Fig 14) to the first direction (Para. 48, and Fig. 14, Where electrode CA14 is over the source/drain regions AR2 both in the first direction [Y labeled axis here] and the second direction [Z labeled axis]), and
a first pin (IW2) connected to the first electrode and having a longitudinal axis along the first direction (Para. 61, and Fig. 14); and
a second cell (CR2) comprising:
a second electrode (CA26) over a second source region (260 - within AR1, Para. 97) or a second drain region (260 - within AR1, Para. 97) of a second transistor in the first direction, wherein the second source region is over the second region in the second direction (Para. 161, and Fig. 14, Where electrode CA26 is over the source/drain regions AR1 both in the first direction [Y labeled axis here] and the second direction [Z labeled axis]), and
a second pin (OW3) connected to the second electrode and having a longitudinal axis along the first direction (Para. 161, and Fig. 14), and
a substrate (100, Para 137),
wherein the first pin is misaligned with the second pin in in a third direction (The third direction can be labeled X-axis in fig 14. As the pins IW2 and OW3 are not over each other in the third direction, they can be understood to be misaligned in the third direction), wherein the first direction is substantially perpendicular to a plane of the substrate, and wherein the second direction and the third direction are substantially parallel to the plane of the substrate (Second and Third directions are x and Y directions from You in Fig. 14, which follow the direction of the substrate 100, and the First direction follows the Z axis).
The Examiner notes that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. See, e.g., In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). See MPEP § 2114. The recitation of “wherein the first pin is to transmit a signal out from the first cell" and “wherein the second pin is to transmit a signal out from the second cell” do not distinguish the present invention over the prior art of You who teaches the structure as claimed,
Regarding Claim 17, You H discloses the IC device according to claim 15, wherein:
the first cell further comprises a third pin (IW1) having a longitudinal axis along the first direction (The axis of IW1 that is in the Y direction),
the second cell further comprises a fourth pin (IW3) having a longitudinal axis along the first direction (The axis of IW3 that is in the Y direction), and
the third pin and the fourth pin are aligned in the third direction (Fig. 14, where IW1 and IW3 are aligned in the third direction Y).
Regarding Claim 18, You H discloses the IC device according to claim 17, wherein:
the first cell further comprises a third electrode (G1) over a channel region of the first transistor (Fig. 14, where G1 is disposed in first cell CR1), and
the third pin is connected to the third electrode (Para. 42 and Fig. 14, where third electrode G1 is connected to third pin IW1).
Regarding Claim 19, You H discloses the IC device according to claim 18, wherein:
the second cell further comprises a fourth electrode (G3) over a channel region of the second transistor (Fig. 14, where G3 is disposed in first cell CR2), and
the fourth pin is connected to the fourth electrode (Para. 161 and Fig. 14, where fourth electrode G3 is connected to fourth pin IW3).
Regarding Claim 20, You H discloses the IC device according to claim 17, wherein the third pin or the fourth pin is an input pin (Para. 60-62 where IW1 is routinely referred to as being an input).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J HIBBERT whose telephone number is (703)756-1562. The examiner can normally be reached Monday - Friday 10am-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL J HIBBERT/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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