Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on June 13, 2023 and August 21, 2024 were in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 5, and 7-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ishii (Pub. No.: US 2001/0040246 A1).
Regarding Claim 1, Ishii discloses
a method of manufacturing a semiconductor element, the method comprising: forming a mask on a front surface of a substrate, the mask having an opening to expose the front surface (Par. 0093-0098; Figs. 6-7 – mask 4; substrate comprising buffer layer 2); growing a first semiconductor layer by epitaxially growing a semiconductor along the mask, starting from the front surface exposed through the opening (Par. 0099; Figs. 6-8 – first semiconductor layer 11 (n-GaN)); and growing a second semiconductor layer on a surface of the first semiconductor layer located opposite to the substrate in a layering direction (Par. 0099; Figs. 6-8 – second semiconductor layer 12 (12A/12B/12C)); and
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providing an electrode on a surface of the second semiconductor layer located opposite to the surface of the first semiconductor layer in the layering direction (Par. 0103; Figs. 12-14 – electrode S (source electrode)), wherein a width from an end portion of the surface to the electrode is smaller than a width of the mask (Fig. 12).
Regarding Claim 3, Ishii, as applied to claim 1, discloses
the method of manufacturing a semiconductor element, comprising: having a mesa structure in the surface of the second semiconductor layer located on an opposite side to the substrate in the layering direction and on which the electrode is provided (Fig. 9).
Regarding Claim 5, Ishii, as applied to claim 1, discloses
the method of manufacturing a semiconductor element, comprising: having a trench structure in the second semiconductor layer (Fig. 9).
Regarding Claim 7, Ishii, as applied to claim 1, implicitly discloses
the method of manufacturing a semiconductor element, wherein the first semiconductor layer and the second semiconductor layer are hexagonal when viewed in the layering direction (this prior art does not teach this limitation expressly; however, it is well-known in the art that GaN layer grown on a foreign substrate such as sapphire using ELO technique has a hexagonal shape when viewed from the top (for example, see “Selective Area Growth of GaN Directly on (0001) Sapphire by the HVPE Technique”- 1998).
Regarding Claim 8, Ishii, as applied to claim 1, discloses
the method of manufacturing a semiconductor element, wherein: the mask is interposed between the substrate and the first semiconductor layer inside the semiconductor element (Fig. 8).
Regarding Claim 9, Ishii, as applied to claim 1, discloses
a semiconductor element manufactured by the method of manufacturing a semiconductor element, wherein: the mask is interposed between the substrate and the first semiconductor layer inside the semiconductor element (Fig. 12).
Regarding Claim 10, Ishii, as applied to claim 1, discloses
a semiconductor device comprising: a semiconductor element manufactured by the method of manufacturing a semiconductor element (Fig. 12).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2 & 4 are rejected under 35 U.S.C. 103 as obvious over Ishii (Pub. No.: US 2001/0040246 A1), as applied to claim 1.
Regarding Claim 2, Ishii, as applied to claim 1, does not explicitly disclose
the method of manufacturing a semiconductor element, wherein the width of the mask is 10 µm or more. However, from the teachings of Ishii one can derive that the width of the mask would depend on the type of device, type and size of the electrode etc. For example, Ishii teaches that for the making of a vertical FET, the width of the mask would depend on the width of the source electrode, being identical or slightly larger than the width of the source electrode. Now, the width of the source electrode would depend on the details of the related device, for what application it is intended to be used etc. Ishii discloses the claimed invention except for the method of manufacturing a semiconductor element, wherein the width of the mask is 10 µm or more. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the method of manufacturing a semiconductor element, wherein the width of the mask is 10 µm or more, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding Claim 4, Ishii, as applied to claim 1, does not explicitly disclose the method of manufacturing a semiconductor element, comprising: having a field plate structure on the surface of the second semiconductor layer. However, the Examiner takes OFFICIAL NOTICE that the method of manufacturing a semiconductor element, comprising: having a field plate structure on the surface of the second semiconductor layer r is well known in the art (field plates are used to tailor the electric field in order to suppress any premature breakdown of the device). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings well-known in the industry to adapt the method of manufacturing a semiconductor element, comprising: having a field plate structure on the surface of the second semiconductor layer of Ishii in order to suppress any premature breakdown of the device.
Claim 6 is rejected under 35 U.S.C. 103 as obvious over Ishii (Pub. No.: US 2001/0040246 A1), as applied to claim 1, further in view of Dasgupta et al (Pub. No.: US 2019/0189771 A1).
Regarding Claim 6, Ishii, as applied to claim 1, does not explicitly disclose the method of manufacturing a semiconductor element, comprising: having a junction barrier Schottky (JBS) structure in the semiconductor layer which contains the first semiconductor layer and the second semiconductor layer. However, Dasgupta et al., teaches the method of manufacturing a semiconductor element, comprising: having a junction barrier Schottky (JBS) structure in the semiconductor layer which contains the first semiconductor layer and the second semiconductor layer (Par. 0038-0040; Fig. 3B – first semiconductor layer 341, second semiconductor layer 350). In short, Ishii teaches a method of making GaN field effect transistor on a foreign substrate. Dasgupta et al., on the other hand, uses similar technique to make a Schottky diode on a foreign substrate. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Dasgupta et al. to adapt the method of manufacturing a semiconductor element, comprising: having a junction barrier Schottky (JBS) structure in the semiconductor layer of Ishii which contains the first semiconductor layer and the second semiconductor layer in order to fabricate the desired circuitry.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mauk (Patent No. 5,828,088 A) – This prior art teaches all the limitations of independent claim 1 (see Fig. 1B)
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09/24/2025
/SYED I GHEYAS/Primary Examiner, Art Unit 2893