DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Non-Final Action filed on 6/22/2026 is acknowledged.
Applicant amended claims 1, 8, and 11.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 4-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 2023/0054372) (hereafter Huang).
Regarding claim 1, Huang (see upside down figure of Fig. 12A) discloses an integrated circuit (IC) device, comprising:
a first conductive structure 260b (Fig. 12A, paragraph 0064) having a first longitudinal axis (vertical axis of 260b in Fig. 12A);
a second conductive structure 260d (Fig. 12A, paragraph 0064) having a second longitudinal axis (vertical axis of 260d in Fig. 12A) that is substantially parallel to the first longitudinal axis (vertical axis of 260b in Fig. 12A);
a first semiconductor structure 204a (Fig. 12A, paragraph 0022); and
a second semiconductor structure 204b (Fig. 12A, paragraph 0022) over (see upside down figure of Fig. 12A, wherein 204b is vertically over 204a) the first semiconductor structure 204a (Fig. 12A),
wherein:
a first portion (portion of 260b formed over 204a in Fig. 12A) of the first conductive structure 260b (Fig. 12A) is over a portion of the first semiconductor structure 204a (Fig. 12A),
a second portion (portion of 260b formed over 204b in Fig. 12A) of the first conductive structure 260b (Fig. 12A) is over a portion of the second semiconductor structure 204b (Fig. 12A),
a dimension (L1 in Fig. 12A, paragraph 0053) of the first portion (portion of 260b formed over 204a in Fig. 12A) in a direction (horizontal direction in Fig. 12A) substantially perpendicular to the first longitudinal axis (vertical axis of 260b in Fig. 12A) is greater than a dimension (L2 in Fig. 12A, paragraph 0053) of the second portion (portion of 260b formed over 204b in Fig. 12A) in the direction (horizontal direction in Fig. 12A),
a distance from a center of the first portion (portion of 260b formed over 204a in Fig. 12A) to the second longitudinal axis (vertical axis of 260d in Fig. 12A) is the same or substantially similar as a distance from a center of the second portion (portion of 260b formed over 204b in Fig. 12A) to the second longitudinal axis (vertical axis of 260d in Fig. 12A), and
a dimension (vertical length of 260b in Fig. 12A) of the first conductive structure 260b (Fig. 12A) along the first longitudinal axis (vertical axis of 260b in Fig. 12A) is greater (see Fig. 2A and paragraph 0029, wherein “a distance S, which may range from about 20 nm to about 100 nm” such that the vertical length of 260b in Fig. 12A is greater than about 20 nm; and see Fig. 12A and paragraph 0053, wherein “L1 and L2 is about 8 nm to about 13 nm” such that the horizontal length of 260b in Fig. 12A is about 8 nm to about 13 nm) than a dimension (horizontal length of 260b in Fig. 12A) of the first conductive structure 260b (Fig. 12A) in the direction (horizontal direction in Fig. 12A).
Regarding claim 4, Huang further discloses the IC device according to claim 1, further comprising: a first dielectric structure 272 (Fig. 12D, paragraph 0066) over the first portion 260b (Fig. 12D) of the first conductive structure 260b (Fig. 12D) in the direction (horizontal direction in Fig. 12D); and
a second dielectric structure 222a (Fig. 12E, paragraph 0057) over the second portion 260b (Fig. 12E) of the first conductive structure 260b (Fig. 12E) in the direction (horizontal direction in Fig. 12E), wherein a dimension of the first dielectric structure 272 (Fig. 12D) in the direction (horizontal direction in Fig. 12D) is smaller than a dimension of the second dielectric structure 222a (Fig. 12E) in the direction (horizontal direction in Fig. 12D).
Regarding claim 5, Huang further discloses the IC device according to claim 1, further comprising: a first dielectric structure 259 (Fig. 12D, paragraph 0062) at least partially between (see Fig. 12D, wherein 259 is diagonally between 260b and 224) the first portion 260b (Fig. 12D) of the first conductive structure 260b (Fig. 12D) and the portion of the first semiconductor structure (224 and 206 in Fig. 12D); and
a second dielectric structure 258 (Fig. 12E, paragraph 0062) at least partially between (see Fig. 12E, wherein 258 is diagonally between 260b and 224) the second portion 260b (Fig. 12E) of the first conductive structure 260b (Fig. 12E) and the portion of the second semiconductor structure (224 and 206 in Fig. 12E), wherein a dimension of the first dielectric structure 259 (Fig. 12D) in the direction (horizontal direction in Fig. 12D) is smaller than a dimension of the second dielectric structure 258 (Fig. 12E) in the direction (horizontal direction in Fig. 12E).
Regarding claim 6, Huang further discloses the IC device according to claim 1, further comprising: a first dielectric region (second 272 from the left corner of Fig. 12D, paragraph 0066) over the first portion 260b (Fig. 12D) of the first conductive structure 260b (Fig. 12D) in a different direction (vertical direction in Fig. 12D) that is substantially perpendicular to the direction (horizontal direction in Fig. 12D) and the first longitudinal axis (stacking direction in Fig. 12D); and
a second dielectric region (region between first 272 and third 272 from the left corner of Fig. 12E, paragraph 0066) over the second portion 260b (Fig. 12E) of the first conductive structure in the different direction, wherein a dimension of the first dielectric region (second 272 from the left corner of Fig. 12D) is smaller than a dimension of the second dielectric region (region between first 272 and third 272 from the left corner of Fig. 12E.
Regarding claim 7, Huang further discloses the IC device according to claim 1, wherein the first semiconductor structure 204a (Fig. 12A, paragraph 0022, wherein “fins 204a and 204b”) has a fin or nanoribbon.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2023/0054372) (hereafter Huang).
Regarding claim 2, Huang discloses the IC device according to claim 1, however Huang does not explicitly disclose a difference between the dimension of the first portion and the dimension of the second portion is up to approximately 3 nanometers.
Regarding the limitation, “a difference between the dimension of the first portion and the dimension of the second portion is up to approximately 3 nanometers”, Huang discloses a difference between the dimension (L1 in Fig. 12A, paragraph 0053) of the first portion (portion of 260b formed over 204a in Fig. 12A) and the dimension (L2 in Fig. 12A, paragraph 0053) of the second portion (portion of 260b formed over 204b in Fig. 12A) is at least about 0.5 nm to about 5 nm (see paragraph 0053). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Huang to form a difference between the dimension of the first portion and the dimension of the second portion is up to approximately 3 nanometers, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 3, Huang discloses the IC device according to claim 2, however Huang does not explicitly disclose the difference between the dimension of the first portion and the dimension of the second portion is at least approximately 0.5 nanometer.
Regarding the limitation, “the difference between the dimension of the first portion and the dimension of the second portion is at least approximately 0.5 nanometer”, Huang discloses a difference between the dimension (L1 in Fig. 12A, paragraph 0053) of the first portion (portion of 260b formed over 204a in Fig. 12A) and the dimension (L2 in Fig. 12A, paragraph 0053) of the second portion (portion of 260b formed over 204b in Fig. 12A) is at least about 0.5 nm to about 5 nm (see paragraph 0053). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Huang to form a difference between the dimension of the first portion and the dimension of the second portion is at least approximately 0.5 nanometer, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claims 8-14 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2023/0054372) (hereafter Huang), in view of Shin et al. (US 2021/0057538) (hereafter Shin).
Regarding claim 8, Huang (see upside down figure of Fig. 12A) discloses an integrated circuit (IC) device, comprising:
a first transistor (transistor with 260b and 204a in Fig. 12A, paragraph 0021) comprising a first source region (third 224 from the left corner of Fig. 12D, paragraph 0058), a first drain region (second 224 from the left corner of Fig. 12D, paragraph 0058), and a first channel region (second 206 from the left corner of Fig. 12D, paragraph 0024), wherein the first source region (third 224 from the left corner of Fig. 12D) is over the first drain region (second 224 from the left corner of Fig. 12D) along a horizontal axis (horizontal direction in Figs. 12D and 12A) of the IC device;
a second transistor (transistor with 260b and 204b in Fig. 12A, paragraph 0021) over (see upside down figure of Fig. 12A, wherein 204b formed vertically over 204a) the first transistor (transistor with 260b and 204a in Fig. 12A) along a vertical axis (vertical direction in Fig. 12A) of the IC device, the second transistor comprising a second source region (third 224 from the left corner of Fig. 12E), a second drain region (second 224 from the left corner of Fig. 12E), and a second channel region (second 206 from the left corner of Fig. 12E);
a first gate electrode 260b (Fig. 12A, paragraph 0064) comprising a first portion (portion of 260b above 204a in Fig. 12A) and a second portion (portion of 260b above 204b in Fig. 12A), wherein the first portion 260b (Fig. 12D) is over the first channel region (second 206 from the left corner of Fig. 12D), and the second portion 260b (Fig. 12E) is over the second channel region (second 206 from the left corner of Fig. 12E); and
a second gate electrode 260c (Fig. 12A, paragraph 0064) over the first gate electrode 260b (Fig. 12A) along a horizontal axis (horizontal direction in Fig. 12A) of the IC device, wherein a dimension (L1 in Fig. 12A, paragraph 0053) of the first portion (portion of 260b above 204a in Fig. 12A) along the horizontal axis (horizontal direction in Fig. 12A) is greater than a dimension (L2 in Fig. 12A, paragraph 0053) of the second portion (portion of 260b above 204b in Fig. 12A) along the horizontal axis (horizontal direction in Fig. 12A), and a distance from the first portion (portion of 260b above 204a in Fig. 12A) to the second gate electrode 260d (Fig. 12A) along the horizontal axis (horizontal direction in Fig. 12A) is the same or substantially similar as a distance from the second portion (portion of 260b above 204b in Fig. 12A) to the second gate electrode 260d (Fig. 12A).
Huang does not disclose a first trench electrode over the first source region or the first drain region;
a second trench electrode over the second source region or the second drain region;
the first trench electrode and the second trench electrode are between the first gate electrode and the second gate electrode along the vertical axis, and
a dimension of the first trench electrode is the same or substantially similar as a dimension of the second trench electrode along the horizontal axis.
Shin discloses a first trench electrode (first SCT from the left corner of Fig. 1C, paragraph 0037) over the first source region (first SD from the left corner of Fig. 1C, paragraph 0030) or the first drain region;
a second trench electrode (second SCT from the left corner of Fig. 1C, paragraph 0037) over the second source region (second SD from the left corner of Fig. 1C, paragraph 0030) or the second drain region;
the first trench electrode (first SCT from the left corner of Fig. 1C) and the second trench electrode second SCT from the left corner of Fig. 1C) are between the first gate electrode (first GE from the left corner of Fig. 1C, paragraph 0041) and the second gate electrode (third GE from the left corner of Fig. 1C, paragraph 0041) along the vertical axis (vertical direction in Fig. 1A), and
a dimension of the first trench electrode (first SCT from the left corner of Fig. 1C) is the same or substantially similar as a dimension of the second trench electrode (second SCT from the left corner of Fig. 1C) along the horizontal axis (horizontal direction in Fig. 1A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Huang to form a first trench electrode over the first source region or the first drain region; a second trench electrode over the second source region or the second drain region; the first trench electrode and the second trench electrode are between the first gate electrode and the second gate electrode along the vertical axis, and a dimension of the first trench electrode is the same or substantially similar as a dimension of the second trench electrode along the horizontal axis, as taught by Shin, since
Regarding claim 9, Huang further discloses the IC device according to claim 8, wherein: the first gate electrode 260b (Fig. 12A) has a longitudinal axis (vertical direction in Fig. 12A) along the vertical axis, and the first source region (third 224 from the bottom of Fig. 12D), a first drain region (second 224 from the bottom of Fig. 12D), and a first channel region (second 206 from the bottom of Fig. 12D) are in a semiconductor structure 204a (Fig. 12A, paragraph 0022) having a longitudinal axis along the horizontal axis (vertical direction in Fig. 12D).
Regarding claim 10, Huang further discloses the IC device according to claim 9, wherein the semiconductor structure 204a (Fig. 12A, paragraph 0022, wherein “fins 204a and 204b”) comprises a fin or nanoribbon.
Regarding claim 11, Huang further discloses the IC device according to claim 8, wherein: the first source region (third 224 from the left corner of Fig. 12D), the first drain region (second 224 from the left corner of Fig. 12D), and the first channel region (second 206 from the left corner of Fig. 12D) are in a first semiconductor structure 204a (Fig. 12A), the second source region (third 224 from the left corner of Fig. 12E), the second drain region (second 224 from the left corner of Fig. 12E), and the second channel region (second 206 from the left corner of Fig. 12E) are in a second semiconductor structure 204b (Fig. 12A), and the first semiconductor structure 204a (Fig. 12A) is over the second semiconductor structure 204b (Fig. 12A) in a direction (vertical direction in Fig. 12A) along the vertical axis.
Regarding claim 12, Huang further discloses the IC device according to claim 8, wherein: the second gate 260c (Fig. 12A) comprises a third portion (portion of 260c above 204a in Fig. 12A) and a fourth portion (portion of 260c above 204b in Fig. 12A), and a dimension of the third portion (portion of 260c above 204a in Fig. 12A) along the horizontal axis (horizontal direction in Fig. 12A) is greater than a dimension of the fourth portion (portion of 260c above 204b in Fig. 12A) along the horizontal axis (horizontal direction in Fig. 12A).
Regarding claim 13, Huang in view of Shin discloses the IC device according to claim 8, however Huang does not explicitly disclose a difference between the dimension of the first portion and the dimension of the second portion is in a range from approximately 0.5 nanometer to approximately 3 nanometers.
Regarding the limitation, “a difference between the dimension of the first portion and the dimension of the second portion is in a range from approximately 0.5 nanometer to approximately 3 nanometers”, Huang discloses a difference between the dimension (L1 in Fig. 12A, paragraph 0053) of the first portion (portion of 260b formed over 204a in Fig. 12A) and the dimension (L2 in Fig. 12A, paragraph 0053) of the second portion (portion of 260b formed over 204b in Fig. 12A) is at least about 0.5 nm to about 5 nm (see paragraph 0053). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Huang to form a difference between the dimension of the first portion and the dimension of the second portion is in a range from approximately 0.5 nanometer to approximately 3 nanometers, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 14, Huang further discloses the IC device according to claim 8, wherein: the first transistor (transistor with 260b and 204a in Fig. 12A) further comprises a first gate insulator 262 (Fig. 12D, paragraph 0070) between the first portion (portion of 264 of 260b above 204a in Fig. 12A) of the first gate electrode (264 of 260b in Fig. 12D) and the first channel region (second 206 from the left corner of Fig. 12D); and
the second transistor (transistor with 260b and 204b in Fig. 12A) further comprises a second gate insulator (262, 222a, and 259 in Fig. 12E) between the second portion of the first gate electrode (264 of 260b in Fig. 12E) and the second channel region (second 206 from the left corner of Fig. 12E), wherein a dimension of the first gate insulator 262 (Fig. 12D) along the horizontal axis (horizontal direction in Fig. 12D) is smaller than a dimension of the second gate insulator (262, 222a, and 259 in Fig. 12E) along the horizontal axis (horizontal direction in Fig. 12E).
Response to Arguments
1. Applicant's arguments filed 6/22/2026 have been fully considered.
2. The applicant argues (REMARKS, fourth paragraph in page 7) that “Claim 1 is amended to recite "a dimension of the first portion in a direction substantially perpendicular to the first longitudinal axis is greater than a dimension of the second portion in the direction ... and a dimension of the first conductive structure along the first longitudinal axis is greater than a dimension of the first conductive structure in the direction." Huang is silent regarding at least these limitations as the semiconductor structure in FIG. 12A of Huang has a greater dimension along the X axis, which is parallel to L1 and L2. Therefore, Huang cannot anticipate amended claim 1.” However, Huang et al. (US 2023/0054372) disclose a dimension (vertical length of 260b in Fig. 12A) of the first conductive structure 260b (Fig. 12A) along the first longitudinal axis (vertical axis of 260b in Fig. 12A) is greater (see Fig. 2A and paragraph 0029, wherein “a distance S, which may range from about 20 nm to about 100 nm” such that the vertical length of 260b in Fig. 12A is greater than about 20 nm; and see Fig. 12A and paragraph 0053, wherein “L1 and L2 is about 8 nm to about 13 nm” such that the horizontal length of 260b in Fig. 12A is about 8 nm to about 13 nm) than a dimension (horizontal length of 260b in Fig. 12A) of the first conductive structure 260b (Fig. 12A) in the direction (horizontal direction in Fig. 12A).
Applicant's arguments with respect to claims 8-14 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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