DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Group 1, claims 1-14, in the reply filed on November 20, 2025 is acknowledged. Therefore, claims 1-14 are presented for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-10 and 12-14 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by You et al. (US 2022/0045051, hereinafter You).
Regarding claim 1, You discloses for a semiconductor integrated circuit (IC) device comprising that
a gate structure (gate electrode layer 266/gate dielectric layer 264, Fig. 31) between a first gate spacer (filler layer 222 or liner 220 on the left side of Fig. 31) and a second gate spacer (filler layer 222 or liner 220 on the right side of Fig. 31),
the gate structure (266/264, Fig. 1) comprising a first gate (266 on the left side of Fig. 31) and a second gate (266 on the right side of Fig. 31); and
an inverted gate cut region (isolation structure 280, Fig. 31) between the first gate spacer (222 or 220 on the left side of Fig. 31) and the second gate spacer (222 or 220 on the right side of Fig. 31),
wherein the inverted gate cut region (280, Fig. 31) separates the first gate (266 on the left side of Fig. 31) from the second gate (266 on the right side of Fig. 31) and comprises a bottom surface (bottom surface of 280, Fig. 31) and a top surface (top surface of 280, Fig. 31),
wherein a surface area of the top surface is smaller than a surface area of the bottom surface, because as shown in the attached Fig. 31 of You below (also see Fig. 20), a width of top surface of the isolation structure 280 is less than a width of bottom surface of the isolation structure 280 in the cross section, therefore, since length would be the same at the top and bottom surface of 280, the surface area of the top surface of 280 is smaller than the surface area of the bottom surface of 280 (Fig. 31).
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Regarding claim 2, You further discloses for the semiconductor IC device of claim 1 that an air pocket (void 297, Fig. 31) within the inverted gate cut region (within 280, Fig. 31).
Regarding claim 3, You further discloses for the semiconductor IC device of claim 1 that a first transistor (transistor on the left side of Fig. 31) associated with the first gate (266 on the left side of Fig. 31), the first transistor comprising a top channel (top channel member 2080 on the left side, Fig. 31) that is vertically above a bottom channel (bottom channel member 2080 on the left side, Fig. 31).
Regarding claim 5, You further discloses for the semiconductor IC device of claim 1 that the gate structure is a replacement gate structure, because “a gate replacement process (or gate-last process) is adopted where the dummy gate stack 240 serves as a placeholder for a functional gate structure” (emphasis added, [0024]).
Regarding claim 6, You further discloses for the semiconductor IC device of claim 1 that the gate structure is a sacrificial gate structure, because the dummy gate stack 240 is formed and it is then replaced by a functional gate structure 266 ([0024]), therefore, the dummy gate stack 240 can correspond to the sacrificial gate structure in the claimed invention.
Regarding claim 7, You further discloses for the semiconductor IC device of claim 1 that the first gate (266 on the left side of Fig. 31) comprises a frontside contact landing area (top surface area of 266, Fig. 31) that is greater than a bottom surface area of the first gate (bottom surface area of 266, see attached Fig. 31 below), because the gate electrode layer 266 by You has downwardly protruded regions in the far-left and far-right sides and the bottom surface of the regions can correspond to the bottom surface area of the first gate in the claimed invention, in this case, a top surface area of 266 is greater than a bottom surface area of 266 (Fig. 31 below).
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Regarding claim 8, You further discloses for a semiconductor integrated circuit (IC) device comprising that
a gate structure (gate electrode layer 266/gate dielectric layer 264, Fig. 31) between a first gate spacer (filler layer 222 or liner 220 on the left side of Fig. 31) and a second gate spacer (filler layer 222 or liner 220 on the right side of Fig. 31),
the gate structure (266/264, Fig. 31) comprising a first gate (266 on the left side of Fig. 31) and a second gate (266 on the right side of Fig. 31); and
an inverted gate cut region (isolation structure 280, Fig. 31) between the first gate spacer (222 or 220 on the left side of Fig. 31) and the second gate spacer (222 or 220 on the right side of Fig. 31),
wherein the inverted gate cut region (280, Fig. 31) separates the first gate (266 on the left side of Fig. 31) from the second gate (266 on the right side of Fig. 31) and comprises a bottom surface width (width of the bottom surface of 280, Fig. 31) and a top surface (width of the top surface of 280, Fig. 31) that is smaller than the bottom surface width (width of the bottom surface of 280, see attached Fig. 31 above).
Regarding claim 9, You further discloses for the semiconductor IC device of claim 8 that an air pocket (void 297, Fig. 31) within the inverted gate cut region (280, Fig. 31)
Regarding claim 10, You further discloses for the semiconductor IC device of claim 8 that a first transistor (left transistor, Fig. 31) associated with the first gate (266 on the left side of Fig. 31), the first transistor comprising a top channel (top channel member 2080, Fig. 31) that is vertically above a bottom channel (bottom channel member 2080, Fig. 31).
Regarding claim 12, You further discloses for the semiconductor IC device of claim 8 that the gate structure is a replacement gate structure, because “a gate replacement process (or gate-last process) is adopted where the dummy gate stack 240 serves as a placeholder for a functional gate structure” (emphasis added, [0024]).
Regarding claim 13, You further discloses for the semiconductor IC device of claim 8 that the gate structure is a sacrificial gate structure, because the dummy gate stack 240 is formed and it is then replaced by a functional gate structure 266 ([0024]), therefore, the dummy gate stack 240 can correspond to the sacrificial gate structure in the claimed invention.
Regarding claim 14, You further discloses for the semiconductor IC device of claim 8 that the first gate (266 on the left side of Fig. 31) comprises a frontside contact landing area (top surface area of 266, Fig. 31) that is greater than a bottom surface area of the first gate (bottom surface area of 266, see attached Fig. 31 above), as the same reason discussed in claim 7 above.
Allowable Subject Matter
Claims 4 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, because the prior art cited in this Office Action (You) does not teach the claim limitations, “a first dimensions… is greater than a second dimension…” of claims 4 and 11.
Conclusion
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/WOO K LEE/Examiner, Art Unit 2815